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-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c758
1 files changed, 0 insertions, 758 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
deleted file mode 100644
index ffd56deb9e81..000000000000
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ /dev/null
@@ -1,758 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 based common clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/sysdev.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <mach/map.h>
27
28#include <plat/cpu-freq.h>
29
30#include <plat/regs-clock.h>
31#include <plat/clock.h>
32#include <plat/cpu.h>
33#include <plat/pll.h>
34
35/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
36 * ext_xtal_mux for want of an actual name from the manual.
37*/
38
39static struct clk clk_ext_xtal_mux = {
40 .name = "ext_xtal",
41 .id = -1,
42};
43
44#define clk_fin_apll clk_ext_xtal_mux
45#define clk_fin_mpll clk_ext_xtal_mux
46#define clk_fin_epll clk_ext_xtal_mux
47
48#define clk_fout_mpll clk_mpll
49#define clk_fout_epll clk_epll
50
51struct clk_sources {
52 unsigned int nr_sources;
53 struct clk **sources;
54};
55
56struct clksrc_clk {
57 struct clk clk;
58 unsigned int mask;
59 unsigned int shift;
60
61 struct clk_sources *sources;
62
63 unsigned int divider_shift;
64 void __iomem *reg_divider;
65};
66
67static struct clk clk_fout_apll = {
68 .name = "fout_apll",
69 .id = -1,
70};
71
72static struct clk *clk_src_apll_list[] = {
73 [0] = &clk_fin_apll,
74 [1] = &clk_fout_apll,
75};
76
77static struct clk_sources clk_src_apll = {
78 .sources = clk_src_apll_list,
79 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
80};
81
82static struct clksrc_clk clk_mout_apll = {
83 .clk = {
84 .name = "mout_apll",
85 .id = -1,
86 },
87 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
88 .mask = S3C6400_CLKSRC_APLL_MOUT,
89 .sources = &clk_src_apll,
90};
91
92static struct clk *clk_src_epll_list[] = {
93 [0] = &clk_fin_epll,
94 [1] = &clk_fout_epll,
95};
96
97static struct clk_sources clk_src_epll = {
98 .sources = clk_src_epll_list,
99 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
100};
101
102static struct clksrc_clk clk_mout_epll = {
103 .clk = {
104 .name = "mout_epll",
105 .id = -1,
106 },
107 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
108 .mask = S3C6400_CLKSRC_EPLL_MOUT,
109 .sources = &clk_src_epll,
110};
111
112static struct clk *clk_src_mpll_list[] = {
113 [0] = &clk_fin_mpll,
114 [1] = &clk_fout_mpll,
115};
116
117static struct clk_sources clk_src_mpll = {
118 .sources = clk_src_mpll_list,
119 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
120};
121
122static struct clksrc_clk clk_mout_mpll = {
123 .clk = {
124 .name = "mout_mpll",
125 .id = -1,
126 },
127 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
128 .mask = S3C6400_CLKSRC_MPLL_MOUT,
129 .sources = &clk_src_mpll,
130};
131
132static unsigned int armclk_mask;
133
134static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
135{
136 unsigned long rate = clk_get_rate(clk->parent);
137 u32 clkdiv;
138
139 /* divisor mask starts at bit0, so no need to shift */
140 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
141
142 return rate / (clkdiv + 1);
143}
144
145static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
146 unsigned long rate)
147{
148 unsigned long parent = clk_get_rate(clk->parent);
149 u32 div;
150
151 if (parent < rate)
152 return parent;
153
154 div = (parent / rate) - 1;
155 if (div > armclk_mask)
156 div = armclk_mask;
157
158 return parent / (div + 1);
159}
160
161static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
162{
163 unsigned long parent = clk_get_rate(clk->parent);
164 u32 div;
165 u32 val;
166
167 if (rate < parent / (armclk_mask + 1))
168 return -EINVAL;
169
170 rate = clk_round_rate(clk, rate);
171 div = clk_get_rate(clk->parent) / rate;
172
173 val = __raw_readl(S3C_CLK_DIV0);
174 val &= ~armclk_mask;
175 val |= (div - 1);
176 __raw_writel(val, S3C_CLK_DIV0);
177
178 return 0;
179
180}
181
182static struct clk clk_arm = {
183 .name = "armclk",
184 .id = -1,
185 .parent = &clk_mout_apll.clk,
186 .get_rate = s3c64xx_clk_arm_get_rate,
187 .set_rate = s3c64xx_clk_arm_set_rate,
188 .round_rate = s3c64xx_clk_arm_round_rate,
189};
190
191static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
192{
193 unsigned long rate = clk_get_rate(clk->parent);
194
195 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
196
197 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
198 rate /= 2;
199
200 return rate;
201}
202
203static struct clk clk_dout_mpll = {
204 .name = "dout_mpll",
205 .id = -1,
206 .parent = &clk_mout_mpll.clk,
207 .get_rate = s3c64xx_clk_doutmpll_get_rate,
208};
209
210static struct clk *clkset_spi_mmc_list[] = {
211 &clk_mout_epll.clk,
212 &clk_dout_mpll,
213 &clk_fin_epll,
214 &clk_27m,
215};
216
217static struct clk_sources clkset_spi_mmc = {
218 .sources = clkset_spi_mmc_list,
219 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
220};
221
222static struct clk *clkset_irda_list[] = {
223 &clk_mout_epll.clk,
224 &clk_dout_mpll,
225 NULL,
226 &clk_27m,
227};
228
229static struct clk_sources clkset_irda = {
230 .sources = clkset_irda_list,
231 .nr_sources = ARRAY_SIZE(clkset_irda_list),
232};
233
234static struct clk *clkset_uart_list[] = {
235 &clk_mout_epll.clk,
236 &clk_dout_mpll,
237 NULL,
238 NULL
239};
240
241static struct clk_sources clkset_uart = {
242 .sources = clkset_uart_list,
243 .nr_sources = ARRAY_SIZE(clkset_uart_list),
244};
245
246static struct clk *clkset_uhost_list[] = {
247 &clk_48m,
248 &clk_mout_epll.clk,
249 &clk_dout_mpll,
250 &clk_fin_epll,
251};
252
253static struct clk_sources clkset_uhost = {
254 .sources = clkset_uhost_list,
255 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
256};
257
258
259/* The peripheral clocks are all controlled via clocksource followed
260 * by an optional divider and gate stage. We currently roll this into
261 * one clock which hides the intermediate clock from the mux.
262 *
263 * Note, the JPEG clock can only be an even divider...
264 *
265 * The scaler and LCD clocks depend on the S3C64XX version, and also
266 * have a common parent divisor so are not included here.
267 */
268
269static inline struct clksrc_clk *to_clksrc(struct clk *clk)
270{
271 return container_of(clk, struct clksrc_clk, clk);
272}
273
274static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
275{
276 struct clksrc_clk *sclk = to_clksrc(clk);
277 unsigned long rate = clk_get_rate(clk->parent);
278 u32 clkdiv = __raw_readl(sclk->reg_divider);
279
280 clkdiv >>= sclk->divider_shift;
281 clkdiv &= 0xf;
282 clkdiv++;
283
284 rate /= clkdiv;
285 return rate;
286}
287
288static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
289{
290 struct clksrc_clk *sclk = to_clksrc(clk);
291 void __iomem *reg = sclk->reg_divider;
292 unsigned int div;
293 u32 val;
294
295 rate = clk_round_rate(clk, rate);
296 div = clk_get_rate(clk->parent) / rate;
297 if (div > 16)
298 return -EINVAL;
299
300 val = __raw_readl(reg);
301 val &= ~(0xf << sclk->divider_shift);
302 val |= (div - 1) << sclk->divider_shift;
303 __raw_writel(val, reg);
304
305 return 0;
306}
307
308static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
309{
310 struct clksrc_clk *sclk = to_clksrc(clk);
311 struct clk_sources *srcs = sclk->sources;
312 u32 clksrc = __raw_readl(S3C_CLK_SRC);
313 int src_nr = -1;
314 int ptr;
315
316 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
317 if (srcs->sources[ptr] == parent) {
318 src_nr = ptr;
319 break;
320 }
321
322 if (src_nr >= 0) {
323 clksrc &= ~sclk->mask;
324 clksrc |= src_nr << sclk->shift;
325
326 __raw_writel(clksrc, S3C_CLK_SRC);
327
328 clk->parent = parent;
329 return 0;
330 }
331
332 return -EINVAL;
333}
334
335static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
336 unsigned long rate)
337{
338 unsigned long parent_rate = clk_get_rate(clk->parent);
339 int div;
340
341 if (rate > parent_rate)
342 rate = parent_rate;
343 else {
344 div = parent_rate / rate;
345
346 if (div == 0)
347 div = 1;
348 if (div > 16)
349 div = 16;
350
351 rate = parent_rate / div;
352 }
353
354 return rate;
355}
356
357static struct clksrc_clk clk_mmc0 = {
358 .clk = {
359 .name = "mmc_bus",
360 .id = 0,
361 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
362 .enable = s3c64xx_sclk_ctrl,
363 .set_parent = s3c64xx_setparent_clksrc,
364 .get_rate = s3c64xx_getrate_clksrc,
365 .set_rate = s3c64xx_setrate_clksrc,
366 .round_rate = s3c64xx_roundrate_clksrc,
367 },
368 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
369 .mask = S3C6400_CLKSRC_MMC0_MASK,
370 .sources = &clkset_spi_mmc,
371 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
372 .reg_divider = S3C_CLK_DIV1,
373};
374
375static struct clksrc_clk clk_mmc1 = {
376 .clk = {
377 .name = "mmc_bus",
378 .id = 1,
379 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
380 .enable = s3c64xx_sclk_ctrl,
381 .get_rate = s3c64xx_getrate_clksrc,
382 .set_rate = s3c64xx_setrate_clksrc,
383 .set_parent = s3c64xx_setparent_clksrc,
384 .round_rate = s3c64xx_roundrate_clksrc,
385 },
386 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
387 .mask = S3C6400_CLKSRC_MMC1_MASK,
388 .sources = &clkset_spi_mmc,
389 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
390 .reg_divider = S3C_CLK_DIV1,
391};
392
393static struct clksrc_clk clk_mmc2 = {
394 .clk = {
395 .name = "mmc_bus",
396 .id = 2,
397 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
398 .enable = s3c64xx_sclk_ctrl,
399 .get_rate = s3c64xx_getrate_clksrc,
400 .set_rate = s3c64xx_setrate_clksrc,
401 .set_parent = s3c64xx_setparent_clksrc,
402 .round_rate = s3c64xx_roundrate_clksrc,
403 },
404 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
405 .mask = S3C6400_CLKSRC_MMC2_MASK,
406 .sources = &clkset_spi_mmc,
407 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
408 .reg_divider = S3C_CLK_DIV1,
409};
410
411static struct clksrc_clk clk_usbhost = {
412 .clk = {
413 .name = "usb-bus-host",
414 .id = -1,
415 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
416 .enable = s3c64xx_sclk_ctrl,
417 .set_parent = s3c64xx_setparent_clksrc,
418 .get_rate = s3c64xx_getrate_clksrc,
419 .set_rate = s3c64xx_setrate_clksrc,
420 .round_rate = s3c64xx_roundrate_clksrc,
421 },
422 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
423 .mask = S3C6400_CLKSRC_UHOST_MASK,
424 .sources = &clkset_uhost,
425 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
426 .reg_divider = S3C_CLK_DIV1,
427};
428
429static struct clksrc_clk clk_uart_uclk1 = {
430 .clk = {
431 .name = "uclk1",
432 .id = -1,
433 .ctrlbit = S3C_CLKCON_SCLK_UART,
434 .enable = s3c64xx_sclk_ctrl,
435 .set_parent = s3c64xx_setparent_clksrc,
436 .get_rate = s3c64xx_getrate_clksrc,
437 .set_rate = s3c64xx_setrate_clksrc,
438 .round_rate = s3c64xx_roundrate_clksrc,
439 },
440 .shift = S3C6400_CLKSRC_UART_SHIFT,
441 .mask = S3C6400_CLKSRC_UART_MASK,
442 .sources = &clkset_uart,
443 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
444 .reg_divider = S3C_CLK_DIV2,
445};
446
447/* Where does UCLK0 come from? */
448
449static struct clksrc_clk clk_spi0 = {
450 .clk = {
451 .name = "spi-bus",
452 .id = 0,
453 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
454 .enable = s3c64xx_sclk_ctrl,
455 .set_parent = s3c64xx_setparent_clksrc,
456 .get_rate = s3c64xx_getrate_clksrc,
457 .set_rate = s3c64xx_setrate_clksrc,
458 .round_rate = s3c64xx_roundrate_clksrc,
459 },
460 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
461 .mask = S3C6400_CLKSRC_SPI0_MASK,
462 .sources = &clkset_spi_mmc,
463 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
464 .reg_divider = S3C_CLK_DIV2,
465};
466
467static struct clksrc_clk clk_spi1 = {
468 .clk = {
469 .name = "spi-bus",
470 .id = 1,
471 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
472 .enable = s3c64xx_sclk_ctrl,
473 .set_parent = s3c64xx_setparent_clksrc,
474 .get_rate = s3c64xx_getrate_clksrc,
475 .set_rate = s3c64xx_setrate_clksrc,
476 .round_rate = s3c64xx_roundrate_clksrc,
477 },
478 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
479 .mask = S3C6400_CLKSRC_SPI1_MASK,
480 .sources = &clkset_spi_mmc,
481 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
482 .reg_divider = S3C_CLK_DIV2,
483};
484
485static struct clk clk_iis_cd0 = {
486 .name = "iis_cdclk0",
487 .id = -1,
488};
489
490static struct clk clk_iis_cd1 = {
491 .name = "iis_cdclk1",
492 .id = -1,
493};
494
495static struct clk clk_pcm_cd = {
496 .name = "pcm_cdclk",
497 .id = -1,
498};
499
500static struct clk *clkset_audio0_list[] = {
501 [0] = &clk_mout_epll.clk,
502 [1] = &clk_dout_mpll,
503 [2] = &clk_fin_epll,
504 [3] = &clk_iis_cd0,
505 [4] = &clk_pcm_cd,
506};
507
508static struct clk_sources clkset_audio0 = {
509 .sources = clkset_audio0_list,
510 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
511};
512
513static struct clksrc_clk clk_audio0 = {
514 .clk = {
515 .name = "audio-bus",
516 .id = 0,
517 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
518 .enable = s3c64xx_sclk_ctrl,
519 .set_parent = s3c64xx_setparent_clksrc,
520 .get_rate = s3c64xx_getrate_clksrc,
521 .set_rate = s3c64xx_setrate_clksrc,
522 .round_rate = s3c64xx_roundrate_clksrc,
523 },
524 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
525 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
526 .sources = &clkset_audio0,
527 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
528 .reg_divider = S3C_CLK_DIV2,
529};
530
531static struct clk *clkset_audio1_list[] = {
532 [0] = &clk_mout_epll.clk,
533 [1] = &clk_dout_mpll,
534 [2] = &clk_fin_epll,
535 [3] = &clk_iis_cd1,
536 [4] = &clk_pcm_cd,
537};
538
539static struct clk_sources clkset_audio1 = {
540 .sources = clkset_audio1_list,
541 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
542};
543
544static struct clksrc_clk clk_audio1 = {
545 .clk = {
546 .name = "audio-bus",
547 .id = 1,
548 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
549 .enable = s3c64xx_sclk_ctrl,
550 .set_parent = s3c64xx_setparent_clksrc,
551 .get_rate = s3c64xx_getrate_clksrc,
552 .set_rate = s3c64xx_setrate_clksrc,
553 .round_rate = s3c64xx_roundrate_clksrc,
554 },
555 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
556 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
557 .sources = &clkset_audio1,
558 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
559 .reg_divider = S3C_CLK_DIV2,
560};
561
562static struct clksrc_clk clk_irda = {
563 .clk = {
564 .name = "irda-bus",
565 .id = 0,
566 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
567 .enable = s3c64xx_sclk_ctrl,
568 .set_parent = s3c64xx_setparent_clksrc,
569 .get_rate = s3c64xx_getrate_clksrc,
570 .set_rate = s3c64xx_setrate_clksrc,
571 .round_rate = s3c64xx_roundrate_clksrc,
572 },
573 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
574 .mask = S3C6400_CLKSRC_IRDA_MASK,
575 .sources = &clkset_irda,
576 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
577 .reg_divider = S3C_CLK_DIV2,
578};
579
580static struct clk *clkset_camif_list[] = {
581 &clk_h2,
582};
583
584static struct clk_sources clkset_camif = {
585 .sources = clkset_camif_list,
586 .nr_sources = ARRAY_SIZE(clkset_camif_list),
587};
588
589static struct clksrc_clk clk_camif = {
590 .clk = {
591 .name = "camera",
592 .id = -1,
593 .ctrlbit = S3C_CLKCON_SCLK_CAM,
594 .enable = s3c64xx_sclk_ctrl,
595 .set_parent = s3c64xx_setparent_clksrc,
596 .get_rate = s3c64xx_getrate_clksrc,
597 .set_rate = s3c64xx_setrate_clksrc,
598 .round_rate = s3c64xx_roundrate_clksrc,
599 },
600 .shift = 0,
601 .mask = 0,
602 .sources = &clkset_camif,
603 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
604 .reg_divider = S3C_CLK_DIV0,
605};
606
607/* Clock initialisation code */
608
609static struct clksrc_clk *init_parents[] = {
610 &clk_mout_apll,
611 &clk_mout_epll,
612 &clk_mout_mpll,
613 &clk_mmc0,
614 &clk_mmc1,
615 &clk_mmc2,
616 &clk_usbhost,
617 &clk_uart_uclk1,
618 &clk_spi0,
619 &clk_spi1,
620 &clk_audio0,
621 &clk_audio1,
622 &clk_irda,
623 &clk_camif,
624};
625
626static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
627{
628 struct clk_sources *srcs = clk->sources;
629 u32 clksrc = __raw_readl(S3C_CLK_SRC);
630
631 clksrc &= clk->mask;
632 clksrc >>= clk->shift;
633
634 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
635 printk(KERN_ERR "%s: bad source %d\n",
636 clk->clk.name, clksrc);
637 return;
638 }
639
640 clk->clk.parent = srcs->sources[clksrc];
641
642 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
643 clk->clk.name, clk->clk.parent->name, clksrc,
644 clk_get_rate(&clk->clk));
645}
646
647#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
648
649void __init_or_cpufreq s3c6400_setup_clocks(void)
650{
651 struct clk *xtal_clk;
652 unsigned long xtal;
653 unsigned long fclk;
654 unsigned long hclk;
655 unsigned long hclk2;
656 unsigned long pclk;
657 unsigned long epll;
658 unsigned long apll;
659 unsigned long mpll;
660 unsigned int ptr;
661 u32 clkdiv0;
662
663 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
664
665 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
666 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
667
668 xtal_clk = clk_get(NULL, "xtal");
669 BUG_ON(IS_ERR(xtal_clk));
670
671 xtal = clk_get_rate(xtal_clk);
672 clk_put(xtal_clk);
673
674 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
675
676 /* For now assume the mux always selects the crystal */
677 clk_ext_xtal_mux.parent = xtal_clk;
678
679 epll = s3c6400_get_epll(xtal);
680 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
681 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
682
683 fclk = mpll;
684
685 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
686 apll, mpll, epll);
687
688 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
689 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
690 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
691
692 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
693 hclk2, hclk, pclk);
694
695 clk_fout_mpll.rate = mpll;
696 clk_fout_epll.rate = epll;
697 clk_fout_apll.rate = apll;
698
699 clk_h2.rate = hclk2;
700 clk_h.rate = hclk;
701 clk_p.rate = pclk;
702 clk_f.rate = fclk;
703
704 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
705 s3c6400_set_clksrc(init_parents[ptr]);
706}
707
708static struct clk *clks[] __initdata = {
709 &clk_ext_xtal_mux,
710 &clk_iis_cd0,
711 &clk_iis_cd1,
712 &clk_pcm_cd,
713 &clk_mout_epll.clk,
714 &clk_mout_mpll.clk,
715 &clk_dout_mpll,
716 &clk_mmc0.clk,
717 &clk_mmc1.clk,
718 &clk_mmc2.clk,
719 &clk_usbhost.clk,
720 &clk_uart_uclk1.clk,
721 &clk_spi0.clk,
722 &clk_spi1.clk,
723 &clk_audio0.clk,
724 &clk_audio1.clk,
725 &clk_irda.clk,
726 &clk_camif.clk,
727 &clk_arm,
728};
729
730/**
731 * s3c6400_register_clocks - register clocks for s3c6400 and above
732 * @armclk_divlimit: Divisor mask for ARMCLK
733 *
734 * Register the clocks for the S3C6400 and above SoC range, such
735 * as ARMCLK and the clocks which have divider chains attached.
736 *
737 * This call does not setup the clocks, which is left to the
738 * s3c6400_setup_clocks() call which may be needed by the cpufreq
739 * or resume code to re-set the clocks if the bootloader has changed
740 * them.
741 */
742void __init s3c6400_register_clocks(unsigned armclk_divlimit)
743{
744 struct clk *clkp;
745 int ret;
746 int ptr;
747
748 armclk_mask = armclk_divlimit;
749
750 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
751 clkp = clks[ptr];
752 ret = s3c24xx_register_clock(clkp);
753 if (ret < 0) {
754 printk(KERN_ERR "Failed to register clock %s (%d)\n",
755 clkp->name, ret);
756 }
757 }
758}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 18:00:55 -0500