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diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
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1/* linux/arch/arm/plat-s3c24xx/cpu.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33
34#include <mach/hardware.h>
35#include <mach/regs-clock.h>
36#include <asm/irq.h>
37#include <asm/cacheflush.h>
38#include <asm/system_info.h>
39#include <asm/system_misc.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43
44#include <mach/regs-gpio.h>
45#include <plat/regs-serial.h>
46
47#include <plat/cpu.h>
48#include <plat/devs.h>
49#include <plat/clock.h>
50#include <plat/s3c2410.h>
51#include <plat/s3c2412.h>
52#include <plat/s3c2416.h>
53#include <plat/s3c244x.h>
54#include <plat/s3c2443.h>
55
56/* table of supported CPUs */
57
58static const char name_s3c2410[] = "S3C2410";
59static const char name_s3c2412[] = "S3C2412";
60static const char name_s3c2416[] = "S3C2416/S3C2450";
61static const char name_s3c2440[] = "S3C2440";
62static const char name_s3c2442[] = "S3C2442";
63static const char name_s3c2442b[] = "S3C2442B";
64static const char name_s3c2443[] = "S3C2443";
65static const char name_s3c2410a[] = "S3C2410A";
66static const char name_s3c2440a[] = "S3C2440A";
67
68static struct cpu_table cpu_ids[] __initdata = {
69 {
70 .idcode = 0x32410000,
71 .idmask = 0xffffffff,
72 .map_io = s3c2410_map_io,
73 .init_clocks = s3c2410_init_clocks,
74 .init_uarts = s3c2410_init_uarts,
75 .init = s3c2410_init,
76 .name = name_s3c2410
77 },
78 {
79 .idcode = 0x32410002,
80 .idmask = 0xffffffff,
81 .map_io = s3c2410_map_io,
82 .init_clocks = s3c2410_init_clocks,
83 .init_uarts = s3c2410_init_uarts,
84 .init = s3c2410a_init,
85 .name = name_s3c2410a
86 },
87 {
88 .idcode = 0x32440000,
89 .idmask = 0xffffffff,
90 .map_io = s3c2440_map_io,
91 .init_clocks = s3c244x_init_clocks,
92 .init_uarts = s3c244x_init_uarts,
93 .init = s3c2440_init,
94 .name = name_s3c2440
95 },
96 {
97 .idcode = 0x32440001,
98 .idmask = 0xffffffff,
99 .map_io = s3c2440_map_io,
100 .init_clocks = s3c244x_init_clocks,
101 .init_uarts = s3c244x_init_uarts,
102 .init = s3c2440_init,
103 .name = name_s3c2440a
104 },
105 {
106 .idcode = 0x32440aaa,
107 .idmask = 0xffffffff,
108 .map_io = s3c2442_map_io,
109 .init_clocks = s3c244x_init_clocks,
110 .init_uarts = s3c244x_init_uarts,
111 .init = s3c2442_init,
112 .name = name_s3c2442
113 },
114 {
115 .idcode = 0x32440aab,
116 .idmask = 0xffffffff,
117 .map_io = s3c2442_map_io,
118 .init_clocks = s3c244x_init_clocks,
119 .init_uarts = s3c244x_init_uarts,
120 .init = s3c2442_init,
121 .name = name_s3c2442b
122 },
123 {
124 .idcode = 0x32412001,
125 .idmask = 0xffffffff,
126 .map_io = s3c2412_map_io,
127 .init_clocks = s3c2412_init_clocks,
128 .init_uarts = s3c2412_init_uarts,
129 .init = s3c2412_init,
130 .name = name_s3c2412,
131 },
132 { /* a newer version of the s3c2412 */
133 .idcode = 0x32412003,
134 .idmask = 0xffffffff,
135 .map_io = s3c2412_map_io,
136 .init_clocks = s3c2412_init_clocks,
137 .init_uarts = s3c2412_init_uarts,
138 .init = s3c2412_init,
139 .name = name_s3c2412,
140 },
141 { /* a strange version of the s3c2416 */
142 .idcode = 0x32450003,
143 .idmask = 0xffffffff,
144 .map_io = s3c2416_map_io,
145 .init_clocks = s3c2416_init_clocks,
146 .init_uarts = s3c2416_init_uarts,
147 .init = s3c2416_init,
148 .name = name_s3c2416,
149 },
150 {
151 .idcode = 0x32443001,
152 .idmask = 0xffffffff,
153 .map_io = s3c2443_map_io,
154 .init_clocks = s3c2443_init_clocks,
155 .init_uarts = s3c2443_init_uarts,
156 .init = s3c2443_init,
157 .name = name_s3c2443,
158 },
159};
160
161/* minimal IO mapping */
162
163static struct map_desc s3c_iodesc[] __initdata = {
164 IODESC_ENT(GPIO),
165 IODESC_ENT(IRQ),
166 IODESC_ENT(MEMCTRL),
167 IODESC_ENT(UART)
168};
169
170/* read cpu identificaiton code */
171
172static unsigned long s3c24xx_read_idcode_v5(void)
173{
174#if defined(CONFIG_CPU_S3C2416)
175 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
176
177 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
178
179 /* test for s3c2416 or similar device */
180 if ((gs >> 16) == 0x3245)
181 return gs;
182#endif
183
184#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
185 return __raw_readl(S3C2412_GSTATUS1);
186#else
187 return 1UL; /* don't look like an 2400 */
188#endif
189}
190
191static unsigned long s3c24xx_read_idcode_v4(void)
192{
193 return __raw_readl(S3C2410_GSTATUS1);
194}
195
196static void s3c24xx_default_idle(void)
197{
198 unsigned long tmp;
199 int i;
200
201 /* idle the system by using the idle mode which will wait for an
202 * interrupt to happen before restarting the system.
203 */
204
205 /* Warning: going into idle state upsets jtag scanning */
206
207 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
208 S3C2410_CLKCON);
209
210 /* the samsung port seems to do a loop and then unset idle.. */
211 for (i = 0; i < 50; i++)
212 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
213
214 /* this bit is not cleared on re-start... */
215
216 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
217 S3C2410_CLKCON);
218}
219
220void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
221{
222 arm_pm_idle = s3c24xx_default_idle;
223
224 /* initialise the io descriptors we need for initialisation */
225 iotable_init(mach_desc, size);
226 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
227
228 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
229 samsung_cpu_id = s3c24xx_read_idcode_v5();
230 } else {
231 samsung_cpu_id = s3c24xx_read_idcode_v4();
232 }
233 s3c24xx_init_cpu();
234
235 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
236}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 06:00:44 -0500