diff options
Diffstat (limited to 'arch/arm/plat-s3c/include')
-rw-r--r-- | arch/arm/plat-s3c/include/plat/adc.h | 29 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/clock.h | 5 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/cpu.h | 1 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-timer.h | 8 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/uncompress.h | 28 |
5 files changed, 71 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h new file mode 100644 index 000000000000..43df2a404b0b --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/adc.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/adc.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simnte.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX ADC driver information | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_PLAT_ADC_H | ||
15 | #define __ASM_PLAT_ADC_H __FILE__ | ||
16 | |||
17 | struct s3c_adc_client; | ||
18 | |||
19 | extern int s3c_adc_start(struct s3c_adc_client *client, | ||
20 | unsigned int channel, unsigned int nr_samples); | ||
21 | |||
22 | extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, | ||
23 | void (*select)(unsigned selected), | ||
24 | void (*conv)(unsigned d0, unsigned d1), | ||
25 | unsigned int is_ts); | ||
26 | |||
27 | extern void s3c_adc_release(struct s3c_adc_client *client); | ||
28 | |||
29 | #endif /* __ASM_PLAT_ADC_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h index ea1f3ffa9717..a10622eed43a 100644 --- a/arch/arm/plat-s3c/include/plat/clock.h +++ b/arch/arm/plat-s3c/include/plat/clock.h | |||
@@ -81,3 +81,8 @@ extern void s3c2443_setup_clocks(void); | |||
81 | /* S3C64XX specific functions and clocks */ | 81 | /* S3C64XX specific functions and clocks */ |
82 | 82 | ||
83 | extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); | 83 | extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); |
84 | |||
85 | /* Init for pwm clock code */ | ||
86 | |||
87 | extern void s3c_pwmclk_init(void); | ||
88 | |||
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index 6d89a4637f30..e62ae0fcfe56 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h | |||
@@ -47,6 +47,7 @@ extern void s3c24xx_init_irq(void); | |||
47 | extern void s3c64xx_init_irq(u32 vic0, u32 vic1); | 47 | extern void s3c64xx_init_irq(u32 vic0, u32 vic1); |
48 | 48 | ||
49 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); | 49 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); |
50 | extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); | ||
50 | 51 | ||
51 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 52 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
52 | 53 | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h index 086ce2685836..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h | |||
@@ -73,6 +73,14 @@ | |||
73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) | 73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) |
74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) | 74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) |
75 | 75 | ||
76 | #define S3C64XX_TCFG1_MUX_DIV1 (0<<0) | ||
77 | #define S3C64XX_TCFG1_MUX_DIV2 (1<<0) | ||
78 | #define S3C64XX_TCFG1_MUX_DIV4 (2<<0) | ||
79 | #define S3C64XX_TCFG1_MUX_DIV8 (3<<0) | ||
80 | #define S3C64XX_TCFG1_MUX_DIV16 (4<<0) | ||
81 | #define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ | ||
82 | #define S3C64XX_TCFG1_MUX_MASK (15<<0) | ||
83 | |||
76 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) | 84 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) |
77 | 85 | ||
78 | /* for each timer, we have an count buffer, an compare buffer and | 86 | /* for each timer, we have an count buffer, an compare buffer and |
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index eeef32c4312d..6061de87f225 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h | |||
@@ -139,6 +139,28 @@ static void arch_decomp_error(const char *x) | |||
139 | 139 | ||
140 | static void error(char *err); | 140 | static void error(char *err); |
141 | 141 | ||
142 | #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO | ||
143 | static inline void arch_enable_uart_fifo(void) | ||
144 | { | ||
145 | u32 fifocon = uart_rd(S3C2410_UFCON); | ||
146 | |||
147 | if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { | ||
148 | fifocon |= S3C2410_UFCON_RESETBOTH; | ||
149 | uart_wr(S3C2410_UFCON, fifocon); | ||
150 | |||
151 | /* wait for fifo reset to complete */ | ||
152 | while (1) { | ||
153 | fifocon = uart_rd(S3C2410_UFCON); | ||
154 | if (!(fifocon & S3C2410_UFCON_RESETBOTH)) | ||
155 | break; | ||
156 | } | ||
157 | } | ||
158 | } | ||
159 | #else | ||
160 | #define arch_enable_uart_fifo() do { } while(0) | ||
161 | #endif | ||
162 | |||
163 | |||
142 | static void | 164 | static void |
143 | arch_decomp_setup(void) | 165 | arch_decomp_setup(void) |
144 | { | 166 | { |
@@ -149,6 +171,12 @@ arch_decomp_setup(void) | |||
149 | 171 | ||
150 | arch_detect_cpu(); | 172 | arch_detect_cpu(); |
151 | arch_decomp_wdog_start(); | 173 | arch_decomp_wdog_start(); |
174 | |||
175 | /* Enable the UART FIFOs if they where not enabled and our | ||
176 | * configuration says we should turn them on. | ||
177 | */ | ||
178 | |||
179 | arch_enable_uart_fifo(); | ||
152 | } | 180 | } |
153 | 181 | ||
154 | 182 | ||