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Diffstat (limited to 'arch/arm/plat-orion/gpio.c')
-rw-r--r--arch/arm/plat-orion/gpio.c73
1 files changed, 25 insertions, 48 deletions
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 967186425ca1..0d12c2164766 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -265,51 +265,36 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
265 * polarity LEVEL mask 265 * polarity LEVEL mask
266 * 266 *
267 ****************************************************************************/ 267 ****************************************************************************/
268static void gpio_irq_edge_ack(u32 irq)
269{
270 int pin = irq_to_gpio(irq);
271
272 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
273}
274
275static void gpio_irq_edge_mask(u32 irq)
276{
277 int pin = irq_to_gpio(irq);
278 u32 u;
279
280 u = readl(GPIO_EDGE_MASK(pin));
281 u &= ~(1 << (pin & 31));
282 writel(u, GPIO_EDGE_MASK(pin));
283}
284 268
285static void gpio_irq_edge_unmask(u32 irq) 269static void gpio_irq_ack(u32 irq)
286{ 270{
287 int pin = irq_to_gpio(irq); 271 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
288 u32 u; 272 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
289 273 int pin = irq_to_gpio(irq);
290 u = readl(GPIO_EDGE_MASK(pin)); 274 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
291 u |= 1 << (pin & 31); 275 }
292 writel(u, GPIO_EDGE_MASK(pin));
293} 276}
294 277
295static void gpio_irq_level_mask(u32 irq) 278static void gpio_irq_mask(u32 irq)
296{ 279{
297 int pin = irq_to_gpio(irq); 280 int pin = irq_to_gpio(irq);
298 u32 u; 281 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
299 282 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
300 u = readl(GPIO_LEVEL_MASK(pin)); 283 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
284 u32 u = readl(reg);
301 u &= ~(1 << (pin & 31)); 285 u &= ~(1 << (pin & 31));
302 writel(u, GPIO_LEVEL_MASK(pin)); 286 writel(u, reg);
303} 287}
304 288
305static void gpio_irq_level_unmask(u32 irq) 289static void gpio_irq_unmask(u32 irq)
306{ 290{
307 int pin = irq_to_gpio(irq); 291 int pin = irq_to_gpio(irq);
308 u32 u; 292 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
309 293 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
310 u = readl(GPIO_LEVEL_MASK(pin)); 294 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
295 u32 u = readl(reg);
311 u |= 1 << (pin & 31); 296 u |= 1 << (pin & 31);
312 writel(u, GPIO_LEVEL_MASK(pin)); 297 writel(u, reg);
313} 298}
314 299
315static int gpio_irq_set_type(u32 irq, u32 type) 300static int gpio_irq_set_type(u32 irq, u32 type)
@@ -331,9 +316,9 @@ static int gpio_irq_set_type(u32 irq, u32 type)
331 * Set edge/level type. 316 * Set edge/level type.
332 */ 317 */
333 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 318 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
334 desc->chip = &orion_gpio_irq_edge_chip; 319 desc->handle_irq = handle_edge_irq;
335 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 320 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
336 desc->chip = &orion_gpio_irq_level_chip; 321 desc->handle_irq = handle_level_irq;
337 } else { 322 } else {
338 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); 323 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
339 return -EINVAL; 324 return -EINVAL;
@@ -371,19 +356,11 @@ static int gpio_irq_set_type(u32 irq, u32 type)
371 return 0; 356 return 0;
372} 357}
373 358
374struct irq_chip orion_gpio_irq_edge_chip = { 359struct irq_chip orion_gpio_irq_chip = {
375 .name = "orion_gpio_irq_edge", 360 .name = "orion_gpio",
376 .ack = gpio_irq_edge_ack, 361 .ack = gpio_irq_ack,
377 .mask = gpio_irq_edge_mask, 362 .mask = gpio_irq_mask,
378 .unmask = gpio_irq_edge_unmask, 363 .unmask = gpio_irq_unmask,
379 .set_type = gpio_irq_set_type,
380};
381
382struct irq_chip orion_gpio_irq_level_chip = {
383 .name = "orion_gpio_irq_level",
384 .mask = gpio_irq_level_mask,
385 .mask_ack = gpio_irq_level_mask,
386 .unmask = gpio_irq_level_unmask,
387 .set_type = gpio_irq_set_type, 364 .set_type = gpio_irq_set_type,
388}; 365};
389 366