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-rw-r--r--arch/arm/plat-orion/addr-map.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
48static void __init __iomem * 48static void __init __iomem *
49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) 49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
50{ 50{
51 return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); 51 return cfg->bridge_virt_base + (win << 4);
52} 52}
53 53
54/* 54/*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
143 * Setup MBUS dram target info. 143 * Setup MBUS dram target info.
144 */ 144 */
145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
146 const u32 ddr_window_cpu_base) 146 const void __iomem *ddr_window_cpu_base)
147{ 147{
148 void __iomem *addr;
149 int i; 148 int i;
150 int cs; 149 int cs;
151 150
152 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 151 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
153 152
154 addr = (void __iomem *)ddr_window_cpu_base;
155
156 for (i = 0, cs = 0; i < 4; i++) { 153 for (i = 0, cs = 0; i < 4; i++) {
157 u32 base = readl(addr + DDR_BASE_CS_OFF(i)); 154 u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
158 u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); 155 u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
159 156
160 /* 157 /*
161 * Chip select enabled? 158 * Chip select enabled?