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-rw-r--r--arch/arm/plat-omap/debug-devices.c8
-rw-r--r--arch/arm/plat-omap/debug-leds.c10
-rw-r--r--arch/arm/plat-omap/dma.c15
-rw-r--r--arch/arm/plat-omap/dmtimer.c11
-rw-r--r--arch/arm/plat-omap/gpio.c127
-rw-r--r--arch/arm/plat-omap/i2c.c55
-rw-r--r--arch/arm/plat-omap/include/mach/board-apollon.h4
-rw-r--r--arch/arm/plat-omap/include/mach/board-ldp.h5
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h82
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h31
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h41
-rw-r--r--arch/arm/plat-omap/include/mach/omapfb.h4
-rw-r--r--arch/arm/plat-omap/sram.c11
13 files changed, 219 insertions, 185 deletions
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index e31154b15d9e..f6684832ca8f 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -69,15 +69,15 @@ int __init debug_card_init(u32 addr, unsigned gpio)
69 smc91x_resources[0].start = addr + 0x300; 69 smc91x_resources[0].start = addr + 0x300;
70 smc91x_resources[0].end = addr + 0x30f; 70 smc91x_resources[0].end = addr + 0x30f;
71 71
72 smc91x_resources[1].start = OMAP_GPIO_IRQ(gpio); 72 smc91x_resources[1].start = gpio_to_irq(gpio);
73 smc91x_resources[1].end = OMAP_GPIO_IRQ(gpio); 73 smc91x_resources[1].end = gpio_to_irq(gpio);
74 74
75 status = omap_request_gpio(gpio); 75 status = gpio_request(gpio, "SMC91x irq");
76 if (status < 0) { 76 if (status < 0) {
77 printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio); 77 printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio);
78 return status; 78 return status;
79 } 79 }
80 omap_set_gpio_direction(gpio, 1); 80 gpio_direction_input(gpio);
81 81
82 led_resources[0].start = addr; 82 led_resources[0].start = addr;
83 led_resources[0].end = addr + SZ_4K - 1; 83 led_resources[0].end = addr + SZ_4K - 1;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 2f4c0cabfd34..be4eefda4767 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -83,8 +83,8 @@ static void h2p2_dbg_leds_event(led_event_t evt)
83 /* all leds off during suspend or shutdown */ 83 /* all leds off during suspend or shutdown */
84 84
85 if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) { 85 if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
86 omap_set_gpio_dataout(GPIO_TIMER, 0); 86 gpio_set_value(GPIO_TIMER, 0);
87 omap_set_gpio_dataout(GPIO_IDLE, 0); 87 gpio_set_value(GPIO_IDLE, 0);
88 } 88 }
89 89
90 __raw_writew(~0, &fpga->leds); 90 __raw_writew(~0, &fpga->leds);
@@ -107,7 +107,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
107 if (machine_is_omap_perseus2() || machine_is_omap_h4()) 107 if (machine_is_omap_perseus2() || machine_is_omap_h4())
108 hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER; 108 hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
109 else { 109 else {
110 omap_set_gpio_dataout(GPIO_TIMER, 110 gpio_set_value(GPIO_TIMER,
111 led_state & LED_TIMER_ON); 111 led_state & LED_TIMER_ON);
112 goto done; 112 goto done;
113 } 113 }
@@ -121,7 +121,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
121 if (machine_is_omap_perseus2() || machine_is_omap_h4()) 121 if (machine_is_omap_perseus2() || machine_is_omap_h4())
122 hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE; 122 hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
123 else { 123 else {
124 omap_set_gpio_dataout(GPIO_IDLE, 1); 124 gpio_set_value(GPIO_IDLE, 1);
125 goto done; 125 goto done;
126 } 126 }
127 127
@@ -131,7 +131,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
131 if (machine_is_omap_perseus2() || machine_is_omap_h4()) 131 if (machine_is_omap_perseus2() || machine_is_omap_h4())
132 hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE; 132 hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
133 else { 133 else {
134 omap_set_gpio_dataout(GPIO_IDLE, 0); 134 gpio_set_value(GPIO_IDLE, 0);
135 goto done; 135 goto done;
136 } 136 }
137 137
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7686b9fa53f2..692d2b495af3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1848,9 +1848,22 @@ static int omap2_dma_handle_ch(int ch)
1848 printk(KERN_INFO 1848 printk(KERN_INFO
1849 "DMA synchronization event drop occurred with device " 1849 "DMA synchronization event drop occurred with device "
1850 "%d\n", dma_chan[ch].dev_id); 1850 "%d\n", dma_chan[ch].dev_id);
1851 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) 1851 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1852 printk(KERN_INFO "DMA transaction error with device %d\n", 1852 printk(KERN_INFO "DMA transaction error with device %d\n",
1853 dma_chan[ch].dev_id); 1853 dma_chan[ch].dev_id);
1854 if (cpu_class_is_omap2()) {
1855 /* Errata: sDMA Channel is not disabled
1856 * after a transaction error. So we explicitely
1857 * disable the channel
1858 */
1859 u32 ccr;
1860
1861 ccr = dma_read(CCR(ch));
1862 ccr &= ~OMAP_DMA_CCR_EN;
1863 dma_write(ccr, CCR(ch));
1864 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1865 }
1866 }
1854 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) 1867 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1855 printk(KERN_INFO "DMA secure error with device %d\n", 1868 printk(KERN_INFO "DMA secure error with device %d\n",
1856 dma_chan[ch].dev_id); 1869 dma_chan[ch].dev_id);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 963c31cd1541..e4f0ce04ba92 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -539,10 +539,6 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
540 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 540 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
541 541
542 /* REVISIT: hw feature, ttgr overtaking tldr? */
543 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
544 cpu_relax();
545
546 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 542 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
547} 543}
548 544
@@ -553,14 +549,15 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
553 u32 l; 549 u32 l;
554 550
555 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 551 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
556 if (autoreload) 552 if (autoreload) {
557 l |= OMAP_TIMER_CTRL_AR; 553 l |= OMAP_TIMER_CTRL_AR;
558 else 554 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
555 } else {
559 l &= ~OMAP_TIMER_CTRL_AR; 556 l &= ~OMAP_TIMER_CTRL_AR;
557 }
560 l |= OMAP_TIMER_CTRL_ST; 558 l |= OMAP_TIMER_CTRL_ST;
561 559
562 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); 560 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
563 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 561 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
565} 562}
566 563
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 424049d83fbe..07b6968a7d16 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -152,6 +152,7 @@ struct gpio_bank {
152 u32 level_mask; 152 u32 level_mask;
153 spinlock_t lock; 153 spinlock_t lock;
154 struct gpio_chip chip; 154 struct gpio_chip chip;
155 struct clk *dbck;
155}; 156};
156 157
157#define METHOD_MPUIO 0 158#define METHOD_MPUIO 0
@@ -244,6 +245,8 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
244 return &gpio_bank[gpio >> 5]; 245 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx()) 246 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5]; 247 return &gpio_bank[gpio >> 5];
248 BUG();
249 return NULL;
247} 250}
248 251
249static inline int get_gpio_index(int gpio) 252static inline int get_gpio_index(int gpio)
@@ -332,19 +335,6 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
332 __raw_writel(l, reg); 335 __raw_writel(l, reg);
333} 336}
334 337
335void omap_set_gpio_direction(int gpio, int is_input)
336{
337 struct gpio_bank *bank;
338 unsigned long flags;
339
340 if (check_gpio(gpio) < 0)
341 return;
342 bank = get_gpio_bank(gpio);
343 spin_lock_irqsave(&bank->lock, flags);
344 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
345 spin_unlock_irqrestore(&bank->lock, flags);
346}
347
348static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 338static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
349{ 339{
350 void __iomem *reg = bank->base; 340 void __iomem *reg = bank->base;
@@ -406,20 +396,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
406 __raw_writel(l, reg); 396 __raw_writel(l, reg);
407} 397}
408 398
409void omap_set_gpio_dataout(int gpio, int enable) 399static int __omap_get_gpio_datain(int gpio)
410{
411 struct gpio_bank *bank;
412 unsigned long flags;
413
414 if (check_gpio(gpio) < 0)
415 return;
416 bank = get_gpio_bank(gpio);
417 spin_lock_irqsave(&bank->lock, flags);
418 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
419 spin_unlock_irqrestore(&bank->lock, flags);
420}
421
422int omap_get_gpio_datain(int gpio)
423{ 400{
424 struct gpio_bank *bank; 401 struct gpio_bank *bank;
425 void __iomem *reg; 402 void __iomem *reg;
@@ -473,6 +450,7 @@ void omap_set_gpio_debounce(int gpio, int enable)
473{ 450{
474 struct gpio_bank *bank; 451 struct gpio_bank *bank;
475 void __iomem *reg; 452 void __iomem *reg;
453 unsigned long flags;
476 u32 val, l = 1 << get_gpio_index(gpio); 454 u32 val, l = 1 << get_gpio_index(gpio);
477 455
478 if (cpu_class_is_omap1()) 456 if (cpu_class_is_omap1())
@@ -480,16 +458,28 @@ void omap_set_gpio_debounce(int gpio, int enable)
480 458
481 bank = get_gpio_bank(gpio); 459 bank = get_gpio_bank(gpio);
482 reg = bank->base; 460 reg = bank->base;
483
484 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 461 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
462
463 spin_lock_irqsave(&bank->lock, flags);
485 val = __raw_readl(reg); 464 val = __raw_readl(reg);
486 465
487 if (enable) 466 if (enable && !(val & l))
488 val |= l; 467 val |= l;
489 else 468 else if (!enable && (val & l))
490 val &= ~l; 469 val &= ~l;
470 else
471 goto done;
472
473 if (cpu_is_omap34xx()) {
474 if (enable)
475 clk_enable(bank->dbck);
476 else
477 clk_disable(bank->dbck);
478 }
491 479
492 __raw_writel(val, reg); 480 __raw_writel(val, reg);
481done:
482 spin_unlock_irqrestore(&bank->lock, flags);
493} 483}
494EXPORT_SYMBOL(omap_set_gpio_debounce); 484EXPORT_SYMBOL(omap_set_gpio_debounce);
495 485
@@ -906,26 +896,17 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
906 return retval; 896 return retval;
907} 897}
908 898
909int omap_request_gpio(int gpio) 899static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
910{ 900{
911 struct gpio_bank *bank; 901 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
912 unsigned long flags; 902 unsigned long flags;
913 int status;
914
915 if (check_gpio(gpio) < 0)
916 return -EINVAL;
917 903
918 status = gpio_request(gpio, NULL);
919 if (status < 0)
920 return status;
921
922 bank = get_gpio_bank(gpio);
923 spin_lock_irqsave(&bank->lock, flags); 904 spin_lock_irqsave(&bank->lock, flags);
924 905
925 /* Set trigger to none. You need to enable the desired trigger with 906 /* Set trigger to none. You need to enable the desired trigger with
926 * request_irq() or set_irq_type(). 907 * request_irq() or set_irq_type().
927 */ 908 */
928 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 909 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
929 910
930#ifdef CONFIG_ARCH_OMAP15XX 911#ifdef CONFIG_ARCH_OMAP15XX
931 if (bank->method == METHOD_GPIO_1510) { 912 if (bank->method == METHOD_GPIO_1510) {
@@ -933,7 +914,7 @@ int omap_request_gpio(int gpio)
933 914
934 /* Claim the pin for MPU */ 915 /* Claim the pin for MPU */
935 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; 916 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
936 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); 917 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
937 } 918 }
938#endif 919#endif
939 spin_unlock_irqrestore(&bank->lock, flags); 920 spin_unlock_irqrestore(&bank->lock, flags);
@@ -941,39 +922,28 @@ int omap_request_gpio(int gpio)
941 return 0; 922 return 0;
942} 923}
943 924
944void omap_free_gpio(int gpio) 925static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
945{ 926{
946 struct gpio_bank *bank; 927 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
947 unsigned long flags; 928 unsigned long flags;
948 929
949 if (check_gpio(gpio) < 0)
950 return;
951 bank = get_gpio_bank(gpio);
952 spin_lock_irqsave(&bank->lock, flags); 930 spin_lock_irqsave(&bank->lock, flags);
953 if (unlikely(!gpiochip_is_requested(&bank->chip,
954 get_gpio_index(gpio)))) {
955 spin_unlock_irqrestore(&bank->lock, flags);
956 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
957 dump_stack();
958 return;
959 }
960#ifdef CONFIG_ARCH_OMAP16XX 931#ifdef CONFIG_ARCH_OMAP16XX
961 if (bank->method == METHOD_GPIO_1610) { 932 if (bank->method == METHOD_GPIO_1610) {
962 /* Disable wake-up during idle for dynamic tick */ 933 /* Disable wake-up during idle for dynamic tick */
963 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 934 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
964 __raw_writel(1 << get_gpio_index(gpio), reg); 935 __raw_writel(1 << offset, reg);
965 } 936 }
966#endif 937#endif
967#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 938#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
968 if (bank->method == METHOD_GPIO_24XX) { 939 if (bank->method == METHOD_GPIO_24XX) {
969 /* Disable wake-up during idle for dynamic tick */ 940 /* Disable wake-up during idle for dynamic tick */
970 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 941 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
971 __raw_writel(1 << get_gpio_index(gpio), reg); 942 __raw_writel(1 << offset, reg);
972 } 943 }
973#endif 944#endif
974 _reset_gpio(bank, gpio); 945 _reset_gpio(bank, bank->chip.base + offset);
975 spin_unlock_irqrestore(&bank->lock, flags); 946 spin_unlock_irqrestore(&bank->lock, flags);
976 gpio_free(gpio);
977} 947}
978 948
979/* 949/*
@@ -1252,7 +1222,7 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
1252 1222
1253static int gpio_get(struct gpio_chip *chip, unsigned offset) 1223static int gpio_get(struct gpio_chip *chip, unsigned offset)
1254{ 1224{
1255 return omap_get_gpio_datain(chip->base + offset); 1225 return __omap_get_gpio_datain(chip->base + offset);
1256} 1226}
1257 1227
1258static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) 1228static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1279,6 +1249,14 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1279 spin_unlock_irqrestore(&bank->lock, flags); 1249 spin_unlock_irqrestore(&bank->lock, flags);
1280} 1250}
1281 1251
1252static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1253{
1254 struct gpio_bank *bank;
1255
1256 bank = container_of(chip, struct gpio_bank, chip);
1257 return bank->virtual_irq_start + offset;
1258}
1259
1282/*---------------------------------------------------------------------*/ 1260/*---------------------------------------------------------------------*/
1283 1261
1284static int initialized; 1262static int initialized;
@@ -1296,7 +1274,6 @@ static struct clk * gpio5_fck;
1296#endif 1274#endif
1297 1275
1298#if defined(CONFIG_ARCH_OMAP3) 1276#if defined(CONFIG_ARCH_OMAP3)
1299static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1300static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1277static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1301#endif 1278#endif
1302 1279
@@ -1310,9 +1287,7 @@ static int __init _omap_gpio_init(void)
1310 int i; 1287 int i;
1311 int gpio = 0; 1288 int gpio = 0;
1312 struct gpio_bank *bank; 1289 struct gpio_bank *bank;
1313#if defined(CONFIG_ARCH_OMAP3)
1314 char clk_name[11]; 1290 char clk_name[11];
1315#endif
1316 1291
1317 initialized = 1; 1292 initialized = 1;
1318 1293
@@ -1367,12 +1342,6 @@ static int __init _omap_gpio_init(void)
1367 printk(KERN_ERR "Could not get %s\n", clk_name); 1342 printk(KERN_ERR "Could not get %s\n", clk_name);
1368 else 1343 else
1369 clk_enable(gpio_iclks[i]); 1344 clk_enable(gpio_iclks[i]);
1370 sprintf(clk_name, "gpio%d_fck", i + 1);
1371 gpio_fclks[i] = clk_get(NULL, clk_name);
1372 if (IS_ERR(gpio_fclks[i]))
1373 printk(KERN_ERR "Could not get %s\n", clk_name);
1374 else
1375 clk_enable(gpio_fclks[i]);
1376 } 1345 }
1377 } 1346 }
1378#endif 1347#endif
@@ -1479,10 +1448,13 @@ static int __init _omap_gpio_init(void)
1479 /* REVISIT eventually switch from OMAP-specific gpio structs 1448 /* REVISIT eventually switch from OMAP-specific gpio structs
1480 * over to the generic ones 1449 * over to the generic ones
1481 */ 1450 */
1451 bank->chip.request = omap_gpio_request;
1452 bank->chip.free = omap_gpio_free;
1482 bank->chip.direction_input = gpio_input; 1453 bank->chip.direction_input = gpio_input;
1483 bank->chip.get = gpio_get; 1454 bank->chip.get = gpio_get;
1484 bank->chip.direction_output = gpio_output; 1455 bank->chip.direction_output = gpio_output;
1485 bank->chip.set = gpio_set; 1456 bank->chip.set = gpio_set;
1457 bank->chip.to_irq = gpio_2irq;
1486 if (bank_is_mpuio(bank)) { 1458 if (bank_is_mpuio(bank)) {
1487 bank->chip.label = "mpuio"; 1459 bank->chip.label = "mpuio";
1488#ifdef CONFIG_ARCH_OMAP16XX 1460#ifdef CONFIG_ARCH_OMAP16XX
@@ -1511,6 +1483,13 @@ static int __init _omap_gpio_init(void)
1511 } 1483 }
1512 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1484 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1513 set_irq_data(bank->irq, bank); 1485 set_irq_data(bank->irq, bank);
1486
1487 if (cpu_is_omap34xx()) {
1488 sprintf(clk_name, "gpio%d_dbck", i + 1);
1489 bank->dbck = clk_get(NULL, clk_name);
1490 if (IS_ERR(bank->dbck))
1491 printk(KERN_ERR "Could not get %s\n", clk_name);
1492 }
1514 } 1493 }
1515 1494
1516 /* Enable system clock for GPIO module. 1495 /* Enable system clock for GPIO module.
@@ -1739,12 +1718,6 @@ static int __init omap_gpio_sysinit(void)
1739 return ret; 1718 return ret;
1740} 1719}
1741 1720
1742EXPORT_SYMBOL(omap_request_gpio);
1743EXPORT_SYMBOL(omap_free_gpio);
1744EXPORT_SYMBOL(omap_set_gpio_direction);
1745EXPORT_SYMBOL(omap_set_gpio_dataout);
1746EXPORT_SYMBOL(omap_get_gpio_datain);
1747
1748arch_initcall(omap_gpio_sysinit); 1721arch_initcall(omap_gpio_sysinit);
1749 1722
1750 1723
@@ -1801,14 +1774,14 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1801 continue; 1774 continue;
1802 1775
1803 irq = bank->virtual_irq_start + j; 1776 irq = bank->virtual_irq_start + j;
1804 value = omap_get_gpio_datain(gpio); 1777 value = gpio_get_value(gpio);
1805 is_in = gpio_is_input(bank, mask); 1778 is_in = gpio_is_input(bank, mask);
1806 1779
1807 if (bank_is_mpuio(bank)) 1780 if (bank_is_mpuio(bank))
1808 seq_printf(s, "MPUIO %2d ", j); 1781 seq_printf(s, "MPUIO %2d ", j);
1809 else 1782 else
1810 seq_printf(s, "GPIO %3d ", gpio); 1783 seq_printf(s, "GPIO %3d ", gpio);
1811 seq_printf(s, "(%10s): %s %s", 1784 seq_printf(s, "(%-20.20s): %s %s",
1812 label, 1785 label,
1813 is_in ? "in " : "out", 1786 is_in ? "in " : "out",
1814 value ? "hi" : "lo"); 1787 value ? "hi" : "lo");
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 0e6d147ab6f8..89a6ab0b7db8 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -79,26 +79,43 @@ static struct platform_device omap_i2c_devices[] = {
79#endif 79#endif
80}; 80};
81 81
82static void __init omap_i2c_mux_pins(int bus_id) 82#if defined(CONFIG_ARCH_OMAP24XX)
83static const int omap24xx_pins[][2] = {
84 { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
85 { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
86};
87#else
88static const int omap24xx_pins[][2] = {};
89#endif
90#if defined(CONFIG_ARCH_OMAP34XX)
91static const int omap34xx_pins[][2] = {
92 { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
93 { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
94 { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
95};
96#else
97static const int omap34xx_pins[][2] = {};
98#endif
99
100static void __init omap_i2c_mux_pins(int bus)
83{ 101{
84 /* TODO: Muxing for OMAP3 */ 102 int scl, sda;
85 switch (bus_id) { 103
86 case 1: 104 if (cpu_class_is_omap1()) {
87 if (cpu_class_is_omap1()) { 105 scl = I2C_SCL;
88 omap_cfg_reg(I2C_SCL); 106 sda = I2C_SDA;
89 omap_cfg_reg(I2C_SDA); 107 } else if (cpu_is_omap24xx()) {
90 } else if (cpu_is_omap24xx()) { 108 scl = omap24xx_pins[bus][0];
91 omap_cfg_reg(M19_24XX_I2C1_SCL); 109 sda = omap24xx_pins[bus][1];
92 omap_cfg_reg(L15_24XX_I2C1_SDA); 110 } else if (cpu_is_omap34xx()) {
93 } 111 scl = omap34xx_pins[bus][0];
94 break; 112 sda = omap34xx_pins[bus][1];
95 case 2: 113 } else {
96 if (cpu_is_omap24xx()) { 114 return;
97 omap_cfg_reg(J15_24XX_I2C2_SCL);
98 omap_cfg_reg(H19_24XX_I2C2_SDA);
99 }
100 break;
101 } 115 }
116
117 omap_cfg_reg(sda);
118 omap_cfg_reg(scl);
102} 119}
103 120
104int __init omap_register_i2c_bus(int bus_id, u32 clkrate, 121int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -142,6 +159,6 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
142 res[1].start = irq; 159 res[1].start = irq;
143 } 160 }
144 161
145 omap_i2c_mux_pins(bus_id); 162 omap_i2c_mux_pins(bus_id - 1);
146 return platform_device_register(pdev); 163 return platform_device_register(pdev);
147} 164}
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index 731c858cf3fe..61bd5e8f09b1 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -29,12 +29,14 @@
29#ifndef __ASM_ARCH_OMAP_APOLLON_H 29#ifndef __ASM_ARCH_OMAP_APOLLON_H
30#define __ASM_ARCH_OMAP_APOLLON_H 30#define __ASM_ARCH_OMAP_APOLLON_H
31 31
32#include <mach/cpu.h>
33
32extern void apollon_mmc_init(void); 34extern void apollon_mmc_init(void);
33 35
34static inline int apollon_plus(void) 36static inline int apollon_plus(void)
35{ 37{
36 /* The apollon plus has IDCODE revision 5 */ 38 /* The apollon plus has IDCODE revision 5 */
37 return system_rev & 0xc0; 39 return omap_rev() & 0xc0;
38} 40}
39 41
40/* Placeholder for APOLLON specific defines */ 42/* Placeholder for APOLLON specific defines */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
index 66e2746c04ca..f23399665212 100644
--- a/arch/arm/plat-omap/include/mach/board-ldp.h
+++ b/arch/arm/plat-omap/include/mach/board-ldp.h
@@ -32,5 +32,8 @@
32extern void twl4030_bci_battery_init(void); 32extern void twl4030_bci_battery_init(void);
33 33
34#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ 34#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
35 35#define LDP_SMC911X_CS 1
36#define LDP_SMC911X_GPIO 152
37#define DEBUG_BASE 0x08000000
38#define OMAP34XX_ETHR_START DEBUG_BASE
36#endif /* __ASM_ARCH_OMAP_LDP_H */ 39#endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index e0464187209d..b2062f1175de 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -28,13 +28,18 @@
28 28
29struct omap_chip_id { 29struct omap_chip_id {
30 u8 oc; 30 u8 oc;
31 u8 type;
31}; 32};
32 33
33#define OMAP_CHIP_INIT(x) { .oc = x } 34#define OMAP_CHIP_INIT(x) { .oc = x }
34 35
35extern unsigned int system_rev; 36/*
36 37 * omap_rev bits:
37#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) 38 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
39 * CPU revision (See _REV_ defined in cpu.h) [15:08]
40 * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
41 */
42unsigned int omap_rev(void);
38 43
39/* 44/*
40 * Test if multicore OMAP support is needed 45 * Test if multicore OMAP support is needed
@@ -108,7 +113,7 @@ extern unsigned int system_rev;
108 * cpu_is_omap243x(): True for OMAP2430 113 * cpu_is_omap243x(): True for OMAP2430
109 * cpu_is_omap343x(): True for OMAP3430 114 * cpu_is_omap343x(): True for OMAP3430
110 */ 115 */
111#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff) 116#define GET_OMAP_CLASS (omap_rev() & 0xff)
112 117
113#define IS_OMAP_CLASS(class, id) \ 118#define IS_OMAP_CLASS(class, id) \
114static inline int is_omap ##class (void) \ 119static inline int is_omap ##class (void) \
@@ -116,7 +121,7 @@ static inline int is_omap ##class (void) \
116 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ 121 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
117} 122}
118 123
119#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff) 124#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
120 125
121#define IS_OMAP_SUBCLASS(subclass, id) \ 126#define IS_OMAP_SUBCLASS(subclass, id) \
122static inline int is_omap ##subclass (void) \ 127static inline int is_omap ##subclass (void) \
@@ -226,7 +231,7 @@ IS_OMAP_SUBCLASS(343x, 0x343)
226 * cpu_is_omap2430(): True for OMAP2430 231 * cpu_is_omap2430(): True for OMAP2430
227 * cpu_is_omap3430(): True for OMAP3430 232 * cpu_is_omap3430(): True for OMAP3430
228 */ 233 */
229#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) 234#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
230 235
231#define IS_OMAP_TYPE(type, id) \ 236#define IS_OMAP_TYPE(type, id) \
232static inline int is_omap ##type (void) \ 237static inline int is_omap ##type (void) \
@@ -320,44 +325,20 @@ IS_OMAP_TYPE(3430, 0x3430)
320#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) 325#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
321 326
322#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 327#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
323/*
324 * Macros to detect silicon revision of OMAP2/3 processors.
325 * is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
326 * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
327 * is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
328 * get_sil_rev: return the silicon rev value.
329 */
330#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
331#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
332 328
333#define is_sil_rev_greater_than(rev) \ 329/* Various silicon revisions for omap2 */
334 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 330#define OMAP242X_CLASS 0x24200024
335 (get_sil_revision(system_rev) > get_sil_revision(rev))) 331#define OMAP2420_REV_ES1_0 0x24200024
332#define OMAP2420_REV_ES2_0 0x24201024
336 333
337#define is_sil_rev_less_than(rev) \ 334#define OMAP243X_CLASS 0x24300024
338 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 335#define OMAP2430_REV_ES1_0 0x24300024
339 (get_sil_revision(system_rev) < get_sil_revision(rev)))
340 336
341#define is_sil_rev_equal_to(rev) \ 337#define OMAP343X_CLASS 0x34300034
342 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 338#define OMAP3430_REV_ES1_0 0x34300034
343 (get_sil_revision(system_rev) == get_sil_revision(rev))) 339#define OMAP3430_REV_ES2_0 0x34301034
344 340#define OMAP3430_REV_ES2_1 0x34302034
345#define get_sil_rev() \ 341#define OMAP3430_REV_ES3_0 0x34303034
346 get_sil_revision(system_rev)
347
348/* Various silicon macros defined here */
349#define OMAP242X_CLASS 0x24200000
350#define OMAP2420_REV_ES1_0 0x24200000
351#define OMAP2420_REV_ES2_0 0x24201000
352
353#define OMAP243X_CLASS 0x24300000
354#define OMAP2430_REV_ES1_0 0x24300000
355
356#define OMAP343X_CLASS 0x34300000
357#define OMAP3430_REV_ES1_0 0x34300000
358#define OMAP3430_REV_ES2_0 0x34301000
359#define OMAP3430_REV_ES2_1 0x34302000
360#define OMAP3430_REV_ES2_2 0x34303000
361 342
362/* 343/*
363 * omap_chip bits 344 * omap_chip bits
@@ -382,23 +363,16 @@ IS_OMAP_TYPE(3430, 0x3430)
382#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 363#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
383 364
384int omap_chip_is(struct omap_chip_id oci); 365int omap_chip_is(struct omap_chip_id oci);
385 366int omap_type(void);
386 367
387/* 368/*
388 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD 369 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
389 */ 370 */
390#define DEVICE_TYPE_TEST 0 371#define OMAP2_DEVICE_TYPE_TEST 0
391#define DEVICE_TYPE_EMU 1 372#define OMAP2_DEVICE_TYPE_EMU 1
392#define DEVICE_TYPE_SEC 2 373#define OMAP2_DEVICE_TYPE_SEC 2
393#define DEVICE_TYPE_GP 3 374#define OMAP2_DEVICE_TYPE_GP 3
394#define DEVICE_TYPE_BAD 4 375#define OMAP2_DEVICE_TYPE_BAD 4
395
396#define get_device_type() ((system_rev & 0x700) >> 8)
397#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
398#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
399#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
400#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
401#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
402 376
403void omap2_check_revision(void); 377void omap2_check_revision(void);
404 378
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 98e9008b7e9d..04e68e88f134 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -71,11 +71,6 @@
71 IH_GPIO_BASE + (nr)) 71 IH_GPIO_BASE + (nr))
72 72
73extern int omap_gpio_init(void); /* Call from board init only */ 73extern int omap_gpio_init(void); /* Call from board init only */
74extern int omap_request_gpio(int gpio);
75extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio);
79extern void omap2_gpio_prepare_for_retention(void); 74extern void omap2_gpio_prepare_for_retention(void);
80extern void omap2_gpio_resume_after_retention(void); 75extern void omap2_gpio_resume_after_retention(void);
81extern void omap_set_gpio_debounce(int gpio, int enable); 76extern void omap_set_gpio_debounce(int gpio, int enable);
@@ -92,6 +87,16 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
92#include <linux/errno.h> 87#include <linux/errno.h>
93#include <asm-generic/gpio.h> 88#include <asm-generic/gpio.h>
94 89
90static inline int omap_request_gpio(int gpio)
91{
92 return gpio_request(gpio, "FIXME");
93}
94
95static inline void omap_free_gpio(int gpio)
96{
97 gpio_free(gpio);
98}
99
95static inline int gpio_get_value(unsigned gpio) 100static inline int gpio_get_value(unsigned gpio)
96{ 101{
97 return __gpio_get_value(gpio); 102 return __gpio_get_value(gpio);
@@ -109,16 +114,24 @@ static inline int gpio_cansleep(unsigned gpio)
109 114
110static inline int gpio_to_irq(unsigned gpio) 115static inline int gpio_to_irq(unsigned gpio)
111{ 116{
112 if (gpio < (OMAP_MAX_GPIO_LINES + 16)) 117 return __gpio_to_irq(gpio);
113 return OMAP_GPIO_IRQ(gpio);
114 return -EINVAL;
115} 118}
116 119
117static inline int irq_to_gpio(unsigned irq) 120static inline int irq_to_gpio(unsigned irq)
118{ 121{
122 int tmp;
123
124 /* omap1 SOC mpuio */
119 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16))) 125 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
120 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES; 126 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
121 return irq - IH_GPIO_BASE; 127
128 /* SOC gpio */
129 tmp = irq - IH_GPIO_BASE;
130 if (tmp < OMAP_MAX_GPIO_LINES)
131 return tmp;
132
133 /* we don't supply reverse mappings for non-SOC gpios */
134 return -EIO;
122} 135}
123 136
124#endif 137#endif
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 6bbf1789bed5..f4362b8682c7 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -632,6 +632,15 @@ enum omap24xx_index {
632 AC7_2430_USB0HS_DATA7, 632 AC7_2430_USB0HS_DATA7,
633 633
634 /* 2430 McBSP */ 634 /* 2430 McBSP */
635 AD6_2430_MCBSP_CLKS,
636
637 AB2_2430_MCBSP1_CLKR,
638 AD5_2430_MCBSP1_FSR,
639 AA1_2430_MCBSP1_DX,
640 AF3_2430_MCBSP1_DR,
641 AB3_2430_MCBSP1_FSX,
642 Y9_2430_MCBSP1_CLKX,
643
635 AC10_2430_MCBSP2_FSX, 644 AC10_2430_MCBSP2_FSX,
636 AD16_2430_MCBSP2_CLX, 645 AD16_2430_MCBSP2_CLX,
637 AE13_2430_MCBSP2_DX, 646 AE13_2430_MCBSP2_DX,
@@ -641,6 +650,30 @@ enum omap24xx_index {
641 AE13_2430_MCBSP2_DX_OFF, 650 AE13_2430_MCBSP2_DX_OFF,
642 AD13_2430_MCBSP2_DR_OFF, 651 AD13_2430_MCBSP2_DR_OFF,
643 652
653 AC9_2430_MCBSP3_CLKX,
654 AE4_2430_MCBSP3_FSX,
655 AE2_2430_MCBSP3_DR,
656 AF4_2430_MCBSP3_DX,
657
658 N3_2430_MCBSP4_CLKX,
659 AD23_2430_MCBSP4_DR,
660 AB25_2430_MCBSP4_DX,
661 AC25_2430_MCBSP4_FSX,
662
663 AE16_2430_MCBSP5_CLKX,
664 AF12_2430_MCBSP5_FSX,
665 K7_2430_MCBSP5_DX,
666 M1_2430_MCBSP5_DR,
667
668 /* 2430 McSPI*/
669 Y18_2430_MCSPI1_CLK,
670 AD15_2430_MCSPI1_SIMO,
671 AE17_2430_MCSPI1_SOMI,
672 U1_2430_MCSPI1_CS0,
673
674 /* Touchscreen GPIO */
675 AF19_2430_GPIO_85,
676
644}; 677};
645 678
646enum omap34xx_index { 679enum omap34xx_index {
@@ -749,6 +782,14 @@ enum omap34xx_index {
749 AD2_3430_USB3FS_PHY_MM3_TXDAT, 782 AD2_3430_USB3FS_PHY_MM3_TXDAT,
750 AC1_3430_USB3FS_PHY_MM3_TXEN_N, 783 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
751 784
785 /* 34xx GPIO
786 * - normally these are bidirectional, no internal pullup/pulldown
787 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
788 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
789 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
790 */
791 AH8_34XX_GPIO29,
792 J25_34XX_GPIO170,
752}; 793};
753 794
754struct omap_mux_cfg { 795struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index ec67fb428607..7b74d1255e0b 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -353,8 +353,8 @@ struct omapfb_device {
353 u32 pseudo_palette[17]; 353 u32 pseudo_palette[17];
354 354
355 struct lcd_panel *panel; /* LCD panel */ 355 struct lcd_panel *panel; /* LCD panel */
356 struct lcd_ctrl *ctrl; /* LCD controller */ 356 const struct lcd_ctrl *ctrl; /* LCD controller */
357 struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ 357 const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
358 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external 358 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
359 interface */ 359 interface */
360 struct device *dev; 360 struct device *dev;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 9f9a921829c0..be7bcaf2b832 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -24,6 +24,7 @@
24 24
25#include <mach/sram.h> 25#include <mach/sram.h>
26#include <mach/board.h> 26#include <mach/board.h>
27#include <mach/cpu.h>
27 28
28#include <mach/control.h> 29#include <mach/control.h>
29 30
@@ -87,7 +88,7 @@ static int is_sram_locked(void)
87 int type = 0; 88 int type = 0;
88 89
89 if (cpu_is_omap242x()) 90 if (cpu_is_omap242x())
90 type = system_rev & OMAP2_DEVICETYPE_MASK; 91 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
91 92
92 if (type == GP_DEVICE) { 93 if (type == GP_DEVICE) {
93 /* RAMFW: R/W access to all initiators for all qualifier sets */ 94 /* RAMFW: R/W access to all initiators for all qualifier sets */
@@ -255,7 +256,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
255 if (!_omap_sram_reprogram_clock) 256 if (!_omap_sram_reprogram_clock)
256 omap_sram_error(); 257 omap_sram_error();
257 258
258 return _omap_sram_reprogram_clock(dpllctl, ckctl); 259 _omap_sram_reprogram_clock(dpllctl, ckctl);
259} 260}
260 261
261int __init omap1_sram_init(void) 262int __init omap1_sram_init(void)
@@ -282,8 +283,8 @@ void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
282 if (!_omap2_sram_ddr_init) 283 if (!_omap2_sram_ddr_init)
283 omap_sram_error(); 284 omap_sram_error();
284 285
285 return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, 286 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
286 base_cs, force_unlock); 287 base_cs, force_unlock);
287} 288}
288 289
289static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, 290static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
@@ -294,7 +295,7 @@ void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
294 if (!_omap2_sram_reprogram_sdrc) 295 if (!_omap2_sram_reprogram_sdrc)
295 omap_sram_error(); 296 omap_sram_error();
296 297
297 return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); 298 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
298} 299}
299 300
300static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 301static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-06 20:23:27 -0400