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-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/include/plat-omap/dma-omap.h377
2 files changed, 1 insertions, 378 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c288b76f8e6c..37a488aaa2ba 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,7 +36,7 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/delay.h> 37#include <linux/delay.h>
38 38
39#include <plat-omap/dma-omap.h> 39#include <linux/omap-dma.h>
40 40
41/* 41/*
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA 42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
diff --git a/arch/arm/plat-omap/include/plat-omap/dma-omap.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
deleted file mode 100644
index 6f506ba9e453..000000000000
--- a/arch/arm/plat-omap/include/plat-omap/dma-omap.h
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * OMAP DMA handling defines and function
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#include <linux/platform_device.h>
25
26#define INT_DMA_LCD 25
27
28#define OMAP1_DMA_TOUT_IRQ (1 << 0)
29#define OMAP_DMA_DROP_IRQ (1 << 1)
30#define OMAP_DMA_HALF_IRQ (1 << 2)
31#define OMAP_DMA_FRAME_IRQ (1 << 3)
32#define OMAP_DMA_LAST_IRQ (1 << 4)
33#define OMAP_DMA_BLOCK_IRQ (1 << 5)
34#define OMAP1_DMA_SYNC_IRQ (1 << 6)
35#define OMAP2_DMA_PKT_IRQ (1 << 7)
36#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
37#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
38#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
39#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
40
41#define OMAP_DMA_CCR_EN (1 << 7)
42#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
43#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
44#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
45#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
46
47#define OMAP_DMA_DATA_TYPE_S8 0x00
48#define OMAP_DMA_DATA_TYPE_S16 0x01
49#define OMAP_DMA_DATA_TYPE_S32 0x02
50
51#define OMAP_DMA_SYNC_ELEMENT 0x00
52#define OMAP_DMA_SYNC_FRAME 0x01
53#define OMAP_DMA_SYNC_BLOCK 0x02
54#define OMAP_DMA_SYNC_PACKET 0x03
55
56#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
57#define OMAP_DMA_SRC_SYNC 0x01
58#define OMAP_DMA_DST_SYNC 0x00
59
60#define OMAP_DMA_PORT_EMIFF 0x00
61#define OMAP_DMA_PORT_EMIFS 0x01
62#define OMAP_DMA_PORT_OCP_T1 0x02
63#define OMAP_DMA_PORT_TIPB 0x03
64#define OMAP_DMA_PORT_OCP_T2 0x04
65#define OMAP_DMA_PORT_MPUI 0x05
66
67#define OMAP_DMA_AMODE_CONSTANT 0x00
68#define OMAP_DMA_AMODE_POST_INC 0x01
69#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
70#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
71
72#define DMA_DEFAULT_FIFO_DEPTH 0x10
73#define DMA_DEFAULT_ARB_RATE 0x01
74/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
75#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
76#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
77#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
78#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
79#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
80#define DMA_THREAD_FIFO_75 (0x01 << 14)
81#define DMA_THREAD_FIFO_25 (0x02 << 14)
82#define DMA_THREAD_FIFO_50 (0x03 << 14)
83
84/* DMA4_OCP_SYSCONFIG bits */
85#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
86#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
87#define DMA_SYSCONFIG_EMUFREE (1 << 5)
88#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
89#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
90#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
91
92#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
93#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
94
95#define DMA_IDLEMODE_SMARTIDLE 0x2
96#define DMA_IDLEMODE_NO_IDLE 0x1
97#define DMA_IDLEMODE_FORCE_IDLE 0x0
98
99/* Chaining modes*/
100#ifndef CONFIG_ARCH_OMAP1
101#define OMAP_DMA_STATIC_CHAIN 0x1
102#define OMAP_DMA_DYNAMIC_CHAIN 0x2
103#define OMAP_DMA_CHAIN_ACTIVE 0x1
104#define OMAP_DMA_CHAIN_INACTIVE 0x0
105#endif
106
107#define DMA_CH_PRIO_HIGH 0x1
108#define DMA_CH_PRIO_LOW 0x0 /* Def */
109
110/* Errata handling */
111#define IS_DMA_ERRATA(id) (errata & (id))
112#define SET_DMA_ERRATA(id) (errata |= (id))
113
114#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
115#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
116#define DMA_ERRATA_i378 BIT(0x2)
117#define DMA_ERRATA_i541 BIT(0x3)
118#define DMA_ERRATA_i88 BIT(0x4)
119#define DMA_ERRATA_3_3 BIT(0x5)
120#define DMA_ROMCODE_BUG BIT(0x6)
121
122/* Attributes for OMAP DMA Contrller */
123#define DMA_LINKED_LCH BIT(0x0)
124#define GLOBAL_PRIORITY BIT(0x1)
125#define RESERVE_CHANNEL BIT(0x2)
126#define IS_CSSA_32 BIT(0x3)
127#define IS_CDSA_32 BIT(0x4)
128#define IS_RW_PRIORITY BIT(0x5)
129#define ENABLE_1510_MODE BIT(0x6)
130#define SRC_PORT BIT(0x7)
131#define DST_PORT BIT(0x8)
132#define SRC_INDEX BIT(0x9)
133#define DST_INDEX BIT(0xa)
134#define IS_BURST_ONLY4 BIT(0xb)
135#define CLEAR_CSR_ON_READ BIT(0xc)
136#define IS_WORD_16 BIT(0xd)
137#define ENABLE_16XX_MODE BIT(0xe)
138#define HS_CHANNELS_RESERVED BIT(0xf)
139
140/* Defines for DMA Capabilities */
141#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
142#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
143#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
144
145enum omap_reg_offsets {
146
147GCR, GSCR, GRST1, HW_ID,
148PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
149PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
150CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
151PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
152IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
153IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
154OCP_SYSCONFIG,
155
156/* omap1+ specific */
157CPC, CCR2, LCH_CTRL,
158
159/* Common registers for all omap's */
160CSDP, CCR, CICR, CSR,
161CEN, CFN, CSFI, CSEI,
162CSAC, CDAC, CDEI,
163CDFI, CLNK_CTRL,
164
165/* Channel specific registers */
166CSSA, CDSA, COLOR,
167CCEN, CCFN,
168
169/* omap3630 and omap4 specific */
170CDP, CNDP, CCDN,
171
172};
173
174enum omap_dma_burst_mode {
175 OMAP_DMA_DATA_BURST_DIS = 0,
176 OMAP_DMA_DATA_BURST_4,
177 OMAP_DMA_DATA_BURST_8,
178 OMAP_DMA_DATA_BURST_16,
179};
180
181enum end_type {
182 OMAP_DMA_LITTLE_ENDIAN = 0,
183 OMAP_DMA_BIG_ENDIAN
184};
185
186enum omap_dma_color_mode {
187 OMAP_DMA_COLOR_DIS = 0,
188 OMAP_DMA_CONSTANT_FILL,
189 OMAP_DMA_TRANSPARENT_COPY
190};
191
192enum omap_dma_write_mode {
193 OMAP_DMA_WRITE_NON_POSTED = 0,
194 OMAP_DMA_WRITE_POSTED,
195 OMAP_DMA_WRITE_LAST_NON_POSTED
196};
197
198enum omap_dma_channel_mode {
199 OMAP_DMA_LCH_2D = 0,
200 OMAP_DMA_LCH_G,
201 OMAP_DMA_LCH_P,
202 OMAP_DMA_LCH_PD
203};
204
205struct omap_dma_channel_params {
206 int data_type; /* data type 8,16,32 */
207 int elem_count; /* number of elements in a frame */
208 int frame_count; /* number of frames in a element */
209
210 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
211 int src_amode; /* constant, post increment, indexed,
212 double indexed */
213 unsigned long src_start; /* source address : physical */
214 int src_ei; /* source element index */
215 int src_fi; /* source frame index */
216
217 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
218 int dst_amode; /* constant, post increment, indexed,
219 double indexed */
220 unsigned long dst_start; /* source address : physical */
221 int dst_ei; /* source element index */
222 int dst_fi; /* source frame index */
223
224 int trigger; /* trigger attached if the channel is
225 synchronized */
226 int sync_mode; /* sycn on element, frame , block or packet */
227 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
228
229 int ie; /* interrupt enabled */
230
231 unsigned char read_prio;/* read priority */
232 unsigned char write_prio;/* write priority */
233
234#ifndef CONFIG_ARCH_OMAP1
235 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
236#endif
237};
238
239struct omap_dma_lch {
240 int next_lch;
241 int dev_id;
242 u16 saved_csr;
243 u16 enabled_irqs;
244 const char *dev_name;
245 void (*callback)(int lch, u16 ch_status, void *data);
246 void *data;
247 long flags;
248 /* required for Dynamic chaining */
249 int prev_linked_ch;
250 int next_linked_ch;
251 int state;
252 int chain_id;
253 int status;
254};
255
256struct omap_dma_dev_attr {
257 u32 dev_caps;
258 u16 lch_count;
259 u16 chan_count;
260 struct omap_dma_lch *chan;
261};
262
263/* System DMA platform data structure */
264struct omap_system_dma_plat_info {
265 struct omap_dma_dev_attr *dma_attr;
266 u32 errata;
267 void (*disable_irq_lch)(int lch);
268 void (*show_dma_caps)(void);
269 void (*clear_lch_regs)(int lch);
270 void (*clear_dma)(int lch);
271 void (*dma_write)(u32 val, int reg, int lch);
272 u32 (*dma_read)(int reg, int lch);
273};
274
275#ifdef CONFIG_ARCH_OMAP2PLUS
276#define dma_omap2plus() 1
277#else
278#define dma_omap2plus() 0
279#endif
280#define dma_omap1() (!dma_omap2plus())
281#define dma_omap15xx() ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
282#define dma_omap16xx() ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
283
284extern void omap_set_dma_priority(int lch, int dst_port, int priority);
285extern int omap_request_dma(int dev_id, const char *dev_name,
286 void (*callback)(int lch, u16 ch_status, void *data),
287 void *data, int *dma_ch);
288extern void omap_enable_dma_irq(int ch, u16 irq_bits);
289extern void omap_disable_dma_irq(int ch, u16 irq_bits);
290extern void omap_free_dma(int ch);
291extern void omap_start_dma(int lch);
292extern void omap_stop_dma(int lch);
293extern void omap_set_dma_transfer_params(int lch, int data_type,
294 int elem_count, int frame_count,
295 int sync_mode,
296 int dma_trigger, int src_or_dst_synch);
297extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
298 u32 color);
299extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
300extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
301
302extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
303 unsigned long src_start,
304 int src_ei, int src_fi);
305extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
306extern void omap_set_dma_src_data_pack(int lch, int enable);
307extern void omap_set_dma_src_burst_mode(int lch,
308 enum omap_dma_burst_mode burst_mode);
309
310extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
311 unsigned long dest_start,
312 int dst_ei, int dst_fi);
313extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
314extern void omap_set_dma_dest_data_pack(int lch, int enable);
315extern void omap_set_dma_dest_burst_mode(int lch,
316 enum omap_dma_burst_mode burst_mode);
317
318extern void omap_set_dma_params(int lch,
319 struct omap_dma_channel_params *params);
320
321extern void omap_dma_link_lch(int lch_head, int lch_queue);
322extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
323
324extern int omap_set_dma_callback(int lch,
325 void (*callback)(int lch, u16 ch_status, void *data),
326 void *data);
327extern dma_addr_t omap_get_dma_src_pos(int lch);
328extern dma_addr_t omap_get_dma_dst_pos(int lch);
329extern void omap_clear_dma(int lch);
330extern int omap_get_dma_active_status(int lch);
331extern int omap_dma_running(void);
332extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
333 int tparams);
334extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
335 unsigned char write_prio);
336extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
337extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
338extern int omap_get_dma_index(int lch, int *ei, int *fi);
339
340void omap_dma_global_context_save(void);
341void omap_dma_global_context_restore(void);
342
343extern void omap_dma_disable_irq(int lch);
344
345/* Chaining APIs */
346#ifndef CONFIG_ARCH_OMAP1
347extern int omap_request_dma_chain(int dev_id, const char *dev_name,
348 void (*callback) (int lch, u16 ch_status,
349 void *data),
350 int *chain_id, int no_of_chans,
351 int chain_mode,
352 struct omap_dma_channel_params params);
353extern int omap_free_dma_chain(int chain_id);
354extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
355 int dest_start, int elem_count,
356 int frame_count, void *callbk_data);
357extern int omap_start_dma_chain_transfers(int chain_id);
358extern int omap_stop_dma_chain_transfers(int chain_id);
359extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
360extern int omap_get_dma_chain_dst_pos(int chain_id);
361extern int omap_get_dma_chain_src_pos(int chain_id);
362
363extern int omap_modify_dma_chain_params(int chain_id,
364 struct omap_dma_channel_params params);
365extern int omap_dma_chain_status(int chain_id);
366#endif
367
368#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
369#include <mach/lcd_dma.h>
370#else
371static inline int omap_lcd_dma_running(void)
372{
373 return 0;
374}
375#endif
376
377#endif /* __ASM_ARCH_DMA_H */
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