diff options
Diffstat (limited to 'arch/arm/plat-omap/include/mach')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/mcbsp.h | 51 |
1 files changed, 49 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h index bb154ea76769..63a3f254af7b 100644 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ b/arch/arm/plat-omap/include/mach/mcbsp.h | |||
| @@ -134,6 +134,11 @@ | |||
| 134 | #define OMAP_MCBSP_REG_XCERG 0x74 | 134 | #define OMAP_MCBSP_REG_XCERG 0x74 |
| 135 | #define OMAP_MCBSP_REG_XCERH 0x78 | 135 | #define OMAP_MCBSP_REG_XCERH 0x78 |
| 136 | #define OMAP_MCBSP_REG_SYSCON 0x8C | 136 | #define OMAP_MCBSP_REG_SYSCON 0x8C |
| 137 | #define OMAP_MCBSP_REG_THRSH2 0x90 | ||
| 138 | #define OMAP_MCBSP_REG_THRSH1 0x94 | ||
| 139 | #define OMAP_MCBSP_REG_IRQST 0xA0 | ||
| 140 | #define OMAP_MCBSP_REG_IRQEN 0xA4 | ||
| 141 | #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 | ||
| 137 | #define OMAP_MCBSP_REG_XCCR 0xAC | 142 | #define OMAP_MCBSP_REG_XCCR 0xAC |
| 138 | #define OMAP_MCBSP_REG_RCCR 0xB0 | 143 | #define OMAP_MCBSP_REG_RCCR 0xB0 |
| 139 | 144 | ||
| @@ -249,8 +254,27 @@ | |||
| 249 | #define RDISABLE 0x0001 | 254 | #define RDISABLE 0x0001 |
| 250 | 255 | ||
| 251 | /********************** McBSP SYSCONFIG bit definitions ********************/ | 256 | /********************** McBSP SYSCONFIG bit definitions ********************/ |
| 257 | #define CLOCKACTIVITY(value) ((value)<<8) | ||
| 258 | #define SIDLEMODE(value) ((value)<<3) | ||
| 259 | #define ENAWAKEUP 0x0004 | ||
| 252 | #define SOFTRST 0x0002 | 260 | #define SOFTRST 0x0002 |
| 253 | 261 | ||
| 262 | /********************** McBSP DMA operating modes **************************/ | ||
| 263 | #define MCBSP_DMA_MODE_ELEMENT 0 | ||
| 264 | #define MCBSP_DMA_MODE_THRESHOLD 1 | ||
| 265 | #define MCBSP_DMA_MODE_FRAME 2 | ||
| 266 | |||
| 267 | /********************** McBSP WAKEUPEN bit definitions *********************/ | ||
| 268 | #define XEMPTYEOFEN 0x4000 | ||
| 269 | #define XRDYEN 0x0400 | ||
| 270 | #define XEOFEN 0x0200 | ||
| 271 | #define XFSXEN 0x0100 | ||
| 272 | #define XSYNCERREN 0x0080 | ||
| 273 | #define RRDYEN 0x0008 | ||
| 274 | #define REOFEN 0x0004 | ||
| 275 | #define RFSREN 0x0002 | ||
| 276 | #define RSYNCERREN 0x0001 | ||
| 277 | |||
| 254 | /* we don't do multichannel for now */ | 278 | /* we don't do multichannel for now */ |
| 255 | struct omap_mcbsp_reg_cfg { | 279 | struct omap_mcbsp_reg_cfg { |
| 256 | u16 spcr2; | 280 | u16 spcr2; |
| @@ -344,6 +368,9 @@ struct omap_mcbsp_platform_data { | |||
| 344 | u8 dma_rx_sync, dma_tx_sync; | 368 | u8 dma_rx_sync, dma_tx_sync; |
| 345 | u16 rx_irq, tx_irq; | 369 | u16 rx_irq, tx_irq; |
| 346 | struct omap_mcbsp_ops *ops; | 370 | struct omap_mcbsp_ops *ops; |
| 371 | #ifdef CONFIG_ARCH_OMAP34XX | ||
| 372 | u16 buffer_size; | ||
| 373 | #endif | ||
| 347 | }; | 374 | }; |
| 348 | 375 | ||
| 349 | struct omap_mcbsp { | 376 | struct omap_mcbsp { |
| @@ -377,6 +404,11 @@ struct omap_mcbsp { | |||
| 377 | struct omap_mcbsp_platform_data *pdata; | 404 | struct omap_mcbsp_platform_data *pdata; |
| 378 | struct clk *iclk; | 405 | struct clk *iclk; |
| 379 | struct clk *fclk; | 406 | struct clk *fclk; |
| 407 | #ifdef CONFIG_ARCH_OMAP34XX | ||
| 408 | int dma_op_mode; | ||
| 409 | u16 max_tx_thres; | ||
| 410 | u16 max_rx_thres; | ||
| 411 | #endif | ||
| 380 | }; | 412 | }; |
| 381 | extern struct omap_mcbsp **mcbsp_ptr; | 413 | extern struct omap_mcbsp **mcbsp_ptr; |
| 382 | extern int omap_mcbsp_count; | 414 | extern int omap_mcbsp_count; |
| @@ -385,10 +417,25 @@ int omap_mcbsp_init(void); | |||
| 385 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | 417 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, |
| 386 | int size); | 418 | int size); |
| 387 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); | 419 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); |
| 420 | #ifdef CONFIG_ARCH_OMAP34XX | ||
| 421 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); | ||
| 422 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); | ||
| 423 | u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); | ||
| 424 | u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); | ||
| 425 | int omap_mcbsp_get_dma_op_mode(unsigned int id); | ||
| 426 | #else | ||
| 427 | static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | ||
| 428 | { } | ||
| 429 | static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | ||
| 430 | { } | ||
| 431 | static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } | ||
| 432 | static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } | ||
| 433 | static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } | ||
| 434 | #endif | ||
| 388 | int omap_mcbsp_request(unsigned int id); | 435 | int omap_mcbsp_request(unsigned int id); |
| 389 | void omap_mcbsp_free(unsigned int id); | 436 | void omap_mcbsp_free(unsigned int id); |
| 390 | void omap_mcbsp_start(unsigned int id); | 437 | void omap_mcbsp_start(unsigned int id, int tx, int rx); |
| 391 | void omap_mcbsp_stop(unsigned int id); | 438 | void omap_mcbsp_stop(unsigned int id, int tx, int rx); |
| 392 | void omap_mcbsp_xmit_word(unsigned int id, u32 word); | 439 | void omap_mcbsp_xmit_word(unsigned int id, u32 word); |
| 393 | u32 omap_mcbsp_recv_word(unsigned int id); | 440 | u32 omap_mcbsp_recv_word(unsigned int id); |
| 394 | 441 | ||
