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-rw-r--r--arch/arm/plat-omap/include/mach/board-2430sdp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-apollon.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-h4.h5
-rw-r--r--arch/arm/plat-omap/include/mach/board-ldp.h36
-rw-r--r--arch/arm/plat-omap/include/mach/board-omap3beagle.h33
-rw-r--r--arch/arm/plat-omap/include/mach/board-overo.h26
-rw-r--r--arch/arm/plat-omap/include/mach/board.h2
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h3
-rw-r--r--arch/arm/plat-omap/include/mach/clockdomain.h106
-rw-r--r--arch/arm/plat-omap/include/mach/common.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h23
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h5
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/fpga.h12
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc.h12
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h12
-rw-r--r--arch/arm/plat-omap/include/mach/io.h59
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h59
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h44
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h2
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h180
-rw-r--r--arch/arm/plat-omap/include/mach/omap1510.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omap16xx.h7
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omapfb.h3
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h7
-rw-r--r--arch/arm/plat-omap/include/mach/powerdomain.h166
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h8
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h18
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h10
-rw-r--r--arch/arm/plat-omap/include/mach/system.h2
33 files changed, 798 insertions, 89 deletions
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
index cf1dc0223949..10d449ea7ed0 100644
--- a/arch/arm/plat-omap/include/mach/board-2430sdp.h
+++ b/arch/arm/plat-omap/include/mach/board-2430sdp.h
@@ -30,10 +30,12 @@
30#define __ASM_ARCH_OMAP_2430SDP_H 30#define __ASM_ARCH_OMAP_2430SDP_H
31 31
32/* Placeholder for 2430SDP specific defines */ 32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300 33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149 34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000 35#define SDP2430_CS0_BASE 0x04000000
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37/* Function prototypes */
38extern void sdp2430_flash_init(void);
39extern void sdp2430_usb_init(void);
38 40
39#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 41#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index d6f2a8e963d5..731c858cf3fe 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -31,6 +31,12 @@
31 31
32extern void apollon_mmc_init(void); 32extern void apollon_mmc_init(void);
33 33
34static inline int apollon_plus(void)
35{
36 /* The apollon plus has IDCODE revision 5 */
37 return system_rev & 0xc0;
38}
39
34/* Placeholder for APOLLON specific defines */ 40/* Placeholder for APOLLON specific defines */
35#define APOLLON_ETHR_GPIO_IRQ 74 41#define APOLLON_ETHR_GPIO_IRQ 74
36 42
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
index 1470cd3e519b..7c3fa0f0a65e 100644
--- a/arch/arm/plat-omap/include/mach/board-h4.h
+++ b/arch/arm/plat-omap/include/mach/board-h4.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/board-h4.h 2 * arch/arm/plat-omap/include/mach/board-h4.h
3 * 3 *
4 * Hardware definitions for TI OMAP1610 H4 board. 4 * Hardware definitions for TI OMAP2420 H4 board.
5 * 5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> 6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 * 7 *
@@ -29,6 +29,9 @@
29#ifndef __ASM_ARCH_OMAP_H4_H 29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H 30#define __ASM_ARCH_OMAP_H4_H
31 31
32/* MMC Prototypes */
33extern void h4_mmc_init(void);
34
32/* Placeholder for H4 specific defines */ 35/* Placeholder for H4 specific defines */
33#define OMAP24XX_ETHR_GPIO_IRQ 92 36#define OMAP24XX_ETHR_GPIO_IRQ 92
34#endif /* __ASM_ARCH_OMAP_H4_H */ 37#endif /* __ASM_ARCH_OMAP_H4_H */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
new file mode 100644
index 000000000000..66e2746c04ca
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-ldp.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-ldp.h
3 *
4 * Hardware definitions for TI OMAP3 LDP.
5 *
6 * Copyright (C) 2008 Texas Instruments Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_LDP_H
30#define __ASM_ARCH_OMAP_LDP_H
31
32extern void twl4030_bci_battery_init(void);
33
34#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
35
36#endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
new file mode 100644
index 000000000000..3080d52d877a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-omap3beagle.h
3 *
4 * Hardware definitions for TI OMAP3 BEAGLE.
5 *
6 * Initial creation by Syed Mohammed Khasim <khasim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
30#define __ASM_ARCH_OMAP3_BEAGLE_H
31
32#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
33
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h
new file mode 100644
index 000000000000..7ecae66966d1
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-overo.h
@@ -0,0 +1,26 @@
1/*
2 * board-overo.h (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 */
15
16#ifndef __ASM_ARCH_OVERO_H
17#define __ASM_ARCH_OVERO_H
18
19#define OVERO_GPIO_BT_XGATE 15
20#define OVERO_GPIO_W2W_NRESET 16
21#define OVERO_GPIO_BT_NRESET 164
22#define OVERO_GPIO_USBH_CPEN 168
23#define OVERO_GPIO_USBH_NRESET 183
24
25#endif /* ____ASM_ARCH_OVERO_H */
26
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 54445642f35d..c23c12ccb353 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -45,6 +45,8 @@ struct omap_mmc_conf {
45 unsigned cover:1; 45 unsigned cover:1;
46 /* 4 wire signaling is optional, and is only used for SD/SDIO */ 46 /* 4 wire signaling is optional, and is only used for SD/SDIO */
47 unsigned wire4:1; 47 unsigned wire4:1;
48 /* use the internal clock */
49 unsigned internal_clock:1;
48 s16 power_pin; 50 s16 power_pin;
49 s16 switch_pin; 51 s16 switch_pin;
50 s16 wp_pin; 52 s16 wp_pin;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 92f7c7238fcd..719298554ed7 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -15,6 +15,7 @@
15 15
16struct module; 16struct module;
17struct clk; 17struct clk;
18struct clockdomain;
18 19
19#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 20#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
20 21
@@ -79,6 +80,8 @@ struct clk {
79 u32 clksel_mask; 80 u32 clksel_mask;
80 const struct clksel *clksel; 81 const struct clksel *clksel;
81 struct dpll_data *dpll_data; 82 struct dpll_data *dpll_data;
83 const char *clkdm_name;
84 struct clockdomain *clkdm;
82#else 85#else
83 __u8 rate_offset; 86 __u8 rate_offset;
84 __u8 src_offset; 87 __u8 src_offset;
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
new file mode 100644
index 000000000000..1f51f0173784
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -0,0 +1,106 @@
1/*
2 * linux/include/asm-arm/arch-omap/clockdomain.h
3 *
4 * OMAP2/3 clockdomain framework functions
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
18
19#include <mach/powerdomain.h>
20#include <mach/clock.h>
21#include <mach/cpu.h>
22
23/* Clockdomain capability flags */
24#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
25#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
26#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
27#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
28
29#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
30#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
31#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
32
33/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
34#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
35#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
36
37/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
38#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
39#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
40#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
41#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
42
43/*
44 * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
45 * and sleepdeps added when a powerdomain should stay active in hwsup mode;
46 * and conversely, removed when the powerdomain should be allowed to go
47 * inactive in hwsup mode.
48 */
49struct clkdm_pwrdm_autodep {
50
51 /* Name of the powerdomain to add a wkdep/sleepdep on */
52 const char *pwrdm_name;
53
54 /* Powerdomain pointer (looked up at clkdm_init() time) */
55 struct powerdomain *pwrdm;
56
57 /* OMAP chip types that this clockdomain dep is valid on */
58 const struct omap_chip_id omap_chip;
59
60};
61
62struct clockdomain {
63
64 /* Clockdomain name */
65 const char *name;
66
67 /* Powerdomain enclosing this clockdomain */
68 const char *pwrdm_name;
69
70 /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
71 const u16 clktrctrl_mask;
72
73 /* Clockdomain capability flags */
74 const u8 flags;
75
76 /* OMAP chip types that this clockdomain is valid on */
77 const struct omap_chip_id omap_chip;
78
79 /* Usecount tracking */
80 atomic_t usecount;
81
82 /* Powerdomain pointer assigned at clkdm_register() */
83 struct powerdomain *pwrdm;
84
85 struct list_head node;
86
87};
88
89void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
90int clkdm_register(struct clockdomain *clkdm);
91int clkdm_unregister(struct clockdomain *clkdm);
92struct clockdomain *clkdm_lookup(const char *name);
93
94int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
95struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
96
97void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
98void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
99
100int omap2_clkdm_wakeup(struct clockdomain *clkdm);
101int omap2_clkdm_sleep(struct clockdomain *clkdm);
102
103int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
104int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
105
106#endif
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 06093112b665..ef70e2b0f054 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -34,6 +34,7 @@ struct sys_timer;
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void); 36extern void omap_serial_init(void);
37extern void omap_serial_enable_clocks(int enable);
37#ifdef CONFIG_I2C_OMAP 38#ifdef CONFIG_I2C_OMAP
38extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 39extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
39 struct i2c_board_info const *info, 40 struct i2c_board_info const *info,
@@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
49 50
50/* IO bases for various OMAP processors */ 51/* IO bases for various OMAP processors */
51struct omap_globals { 52struct omap_globals {
53 u32 class; /* OMAP class to detect */
52 void __iomem *tap; /* Control module ID code */ 54 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */ 55 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */ 56 void __iomem *sms; /* SDRAM Memory Scheduler */
@@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
62void omap2_set_globals_343x(void); 64void omap2_set_globals_343x(void);
63 65
64/* These get called from omap2_set_globals_xxxx(), do not call these */ 66/* These get called from omap2_set_globals_xxxx(), do not call these */
67void omap2_set_globals_tap(struct omap_globals *);
65void omap2_set_globals_memory(struct omap_globals *); 68void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *); 69void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *); 70void omap2_set_globals_prcm(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index e3fd62d9a995..dc9886760577 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,13 +1,10 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/* 1/*
5 * arch/arm/plat-omap/include/mach/control.h 2 * arch/arm/plat-omap/include/mach/control.h
6 * 3 *
7 * OMAP2/3 System Control Module definitions 4 * OMAP2/3 System Control Module definitions
8 * 5 *
9 * Copyright (C) 2007 Texas Instruments, Inc. 6 * Copyright (C) 2007-2008 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation 7 * Copyright (C) 2007-2008 Nokia Corporation
11 * 8 *
12 * Written by Paul Walmsley 9 * Written by Paul Walmsley
13 * 10 *
@@ -16,14 +13,23 @@
16 * the Free Software Foundation. 13 * the Free Software Foundation.
17 */ 14 */
18 15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h> 19#include <mach/io.h>
20 20
21#ifndef __ASSEMBLY__
21#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
30#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */
27 33
28/* 34/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 35 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
@@ -134,6 +140,7 @@
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 140#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 141#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 142#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
143#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
137 144
138/* 145/*
139 * REVISIT: This list of registers is not comprehensive - there are more 146 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 05aee0eda34f..e0464187209d 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
346 get_sil_revision(system_rev) 346 get_sil_revision(system_rev)
347 347
348/* Various silicon macros defined here */ 348/* Various silicon macros defined here */
349#define OMAP242X_CLASS 0x24200000
349#define OMAP2420_REV_ES1_0 0x24200000 350#define OMAP2420_REV_ES1_0 0x24200000
350#define OMAP2420_REV_ES2_0 0x24201000 351#define OMAP2420_REV_ES2_0 0x24201000
352
353#define OMAP243X_CLASS 0x24300000
351#define OMAP2430_REV_ES1_0 0x24300000 354#define OMAP2430_REV_ES1_0 0x24300000
355
356#define OMAP343X_CLASS 0x34300000
352#define OMAP3430_REV_ES1_0 0x34300000 357#define OMAP3430_REV_ES1_0 0x34300000
353#define OMAP3430_REV_ES2_0 0x34301000 358#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000 359#define OMAP3430_REV_ES2_1 0x34302000
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b0039bdeb4e..1b11f5c6a2d9 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -35,6 +35,18 @@
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3 35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3 36 add \rx, \rx, #0x00004000 @ UART 3
37#endif 37#endif
38
39#elif CONFIG_ARCH_OMAP3
40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000
43#ifdef CONFIG_OMAP_LL_DEBUG_UART2
44 add \rx, \rx, #0x00002000 @ UART 2
45#endif
46#ifdef CONFIG_OMAP_LL_DEBUG_UART3
47 add \rx, \rx, #0x00fb0000 @ UART 3
48 add \rx, \rx, #0x00006000
49#endif
38#endif 50#endif
39 .endm 51 .endm
40 52
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index d4e9043bf201..030118ee204a 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -55,9 +55,17 @@
551510: 551510:
56 .endm 56 .endm
57 57
58#elif defined(CONFIG_ARCH_OMAP24XX) 58#endif
59#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
59 60
61#if defined(CONFIG_ARCH_OMAP24XX)
60#include <mach/omap24xx.h> 62#include <mach/omap24xx.h>
63#endif
64#if defined(CONFIG_ARCH_OMAP34XX)
65#include <mach/omap34xx.h>
66#endif
67
68#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
61 69
62 .macro disable_fiq 70 .macro disable_fiq
63 .endm 71 .endm
@@ -79,7 +87,7 @@
79 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ 87 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
80 cmp \irqnr, #0x0 88 cmp \irqnr, #0x0
812222: 892222:
82 ldrne \irqnr, [\base, #IRQ_SIR_IRQ] 90 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
83 91
84 .endm 92 .endm
85 93
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h
index c92e4b42b289..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/mach/fpga.h
@@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
34 * --------------------------------------------------------------------------- 34 * ---------------------------------------------------------------------------
35 */ 35 */
36/* maps in the FPGA registers and the ETHR registers */ 36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 37#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40 40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
85 * OMAP-1510 FPGA 85 * OMAP-1510 FPGA
86 * --------------------------------------------------------------------------- 86 * ---------------------------------------------------------------------------
87 */ 87 */
88#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ 88#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
89#define OMAP1510_FPGA_SIZE SZ_4K 89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* Physical */ 90#define OMAP1510_FPGA_START 0x08000000 /* PA */
91 91
92/* Revision */ 92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 8c71e288860f..98e9008b7e9d 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31 31
32#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000 32#define OMAP_MPUIO_BASE 0xfffb5000
33 33
34#ifdef CONFIG_ARCH_OMAP730 34#ifdef CONFIG_ARCH_OMAP730
35#define OMAP_MPUIO_INPUT_LATCH 0x00 35#define OMAP_MPUIO_INPUT_LATCH 0x00
@@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input); 76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable); 77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio); 78extern int omap_get_gpio_datain(int gpio);
79extern void omap2_gpio_prepare_for_retention(void);
80extern void omap2_gpio_resume_after_retention(void);
79extern void omap_set_gpio_debounce(int gpio, int enable); 81extern void omap_set_gpio_debounce(int gpio, int enable);
80extern void omap_set_gpio_debounce_time(int gpio, int enable); 82extern void omap_set_gpio_debounce_time(int gpio, int enable);
81 83
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 6a8e07ffc2d0..45b678439bb7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -11,6 +11,9 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
14#define GPMC_CS_CONFIG1 0x00 17#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04 18#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08 19#define GPMC_CS_CONFIG3 0x08
@@ -22,6 +25,9 @@
22#define GPMC_CS_NAND_ADDRESS 0x20 25#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24 26#define GPMC_CS_NAND_DATA 0x24
24 27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -78,9 +84,14 @@ struct gpmc_timings {
78 u16 access; /* Start-cycle to first data valid delay */ 84 u16 access; /* Start-cycle to first data valid delay */
79 u16 rd_cycle; /* Total read cycle time */ 85 u16 rd_cycle; /* Total read cycle time */
80 u16 wr_cycle; /* Total write cycle time */ 86 u16 wr_cycle; /* Total write cycle time */
87
88 /* The following are only on OMAP3430 */
89 u16 wr_access; /* WRACCESSTIME */
90 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
81}; 91};
82 92
83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 93extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
94extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 95extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void); 96extern unsigned long gpmc_get_fclk_period(void);
86 97
@@ -92,5 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
92extern void gpmc_cs_free(int cs); 103extern void gpmc_cs_free(int cs);
93extern int gpmc_cs_set_reserved(int cs, int reserved); 104extern int gpmc_cs_set_reserved(int cs, int reserved);
94extern int gpmc_cs_reserved(int cs); 105extern int gpmc_cs_reserved(int cs);
106extern void gpmc_init(void);
95 107
96#endif 108#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 07f5d7f21528..6589ddbb63b2 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -89,7 +89,7 @@
89#define DPLL_CTL (0xfffecf00) 89#define DPLL_CTL (0xfffecf00)
90 90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ 91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE (0xe1008000) 92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
@@ -282,8 +282,8 @@
282 282
283#include "omap730.h" 283#include "omap730.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h"
286#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h"
287#include "omap34xx.h" 287#include "omap34xx.h"
288 288
289#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
@@ -322,6 +322,14 @@
322#include "board-2430sdp.h" 322#include "board-2430sdp.h"
323#endif 323#endif
324 324
325#ifdef CONFIG_MACH_OMAP3_BEAGLE
326#include "board-omap3beagle.h"
327#endif
328
329#ifdef CONFIG_MACH_OMAP_LDP
330#include "board-ldp.h"
331#endif
332
325#ifdef CONFIG_MACH_OMAP_APOLLON 333#ifdef CONFIG_MACH_OMAP_APOLLON
326#include "board-apollon.h" 334#include "board-apollon.h"
327#endif 335#endif
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 2a30b7d88cde..adc83b7b8205 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -55,14 +55,13 @@
55 55
56#if defined(CONFIG_ARCH_OMAP1) 56#if defined(CONFIG_ARCH_OMAP1)
57 57
58#define IO_PHYS 0xFFFB0000 58#define IO_PHYS 0xFFFB0000
59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) 63#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_v2p(va) ((va) + IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66 65
67#elif defined(CONFIG_ARCH_OMAP2) 66#elif defined(CONFIG_ARCH_OMAP2)
68 67
@@ -74,7 +73,6 @@
74#define L4_24XX_VIRT 0xd8000000 73#define L4_24XX_VIRT 0xd8000000
75#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
76 75
77#ifdef CONFIG_ARCH_OMAP2430
78#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 76#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
79#define L4_WK_243X_VIRT 0xd9000000 77#define L4_WK_243X_VIRT 0xd9000000
80#define L4_WK_243X_SIZE SZ_1M 78#define L4_WK_243X_SIZE SZ_1M
@@ -88,13 +86,10 @@
88#define OMAP243X_SMS_VIRT 0xFC000000 86#define OMAP243X_SMS_VIRT 0xFC000000
89#define OMAP243X_SMS_SIZE SZ_1M 87#define OMAP243X_SMS_SIZE SZ_1M
90 88
91#endif 89#define IO_OFFSET 0x90000000
92 90#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
93#define IO_OFFSET 0x90000000 91#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 92#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
98 93
99/* DSP */ 94/* DSP */
100#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ 95#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
@@ -149,9 +144,8 @@
149 144
150 145
151#define IO_OFFSET 0x90000000 146#define IO_OFFSET 0x90000000
152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 147#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 148#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 149#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
156 150
157/* DSP */ 151/* DSP */
@@ -167,7 +161,14 @@
167 161
168#endif 162#endif
169 163
170#ifndef __ASSEMBLER__ 164#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
165#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
166#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
167
168#ifdef __ASSEMBLER__
169#define IOMEM(x) x
170#else
171#define IOMEM(x) ((void __force __iomem *)(x))
171 172
172/* 173/*
173 * Functions to access the OMAP IO region 174 * Functions to access the OMAP IO region
@@ -178,13 +179,13 @@
178 * - DO NOT use hardcoded virtual addresses to allow changing the 179 * - DO NOT use hardcoded virtual addresses to allow changing the
179 * IO address space again if needed 180 * IO address space again if needed
180 */ 181 */
181#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 182#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
182#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 183#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
183#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 184#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
184 185
185#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 186#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 187#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 188#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
188 189
189extern void omap1_map_common_io(void); 190extern void omap1_map_common_io(void);
190extern void omap1_init_common_hw(void); 191extern void omap1_init_common_hw(void);
@@ -192,6 +193,12 @@ extern void omap1_init_common_hw(void);
192extern void omap2_map_common_io(void); 193extern void omap2_map_common_io(void);
193extern void omap2_init_common_hw(void); 194extern void omap2_init_common_hw(void);
194 195
196#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
197#define __arch_iounmap(v) omap_iounmap(v)
198
199void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
200void omap_iounmap(volatile void __iomem *addr);
201
195#endif 202#endif
196 203
197#endif 204#endif
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 62aa7dfb9464..a2929ac8c687 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
125#define INT_UART2 (15 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_SOSSI_MATCH (19 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE) 179#define INT_1610_NAND (63 + IH2_BASE)
180#define INT_1610_SHA1MD5 (91 + IH2_BASE)
179 181
180/* 182/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2 183 * OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,18 @@
263#define INT_24XX_GPTIMER10 46 265#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 266#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 267#define INT_24XX_GPTIMER12 48
268#define INT_24XX_SHA1MD5 51
269#define INT_24XX_MCBSP4_IRQ_TX 54
270#define INT_24XX_MCBSP4_IRQ_RX 55
266#define INT_24XX_I2C1_IRQ 56 271#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57 272#define INT_24XX_I2C2_IRQ 57
273#define INT_24XX_HDQ_IRQ 58
268#define INT_24XX_MCBSP1_IRQ_TX 59 274#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60 275#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62 276#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63 277#define INT_24XX_MCBSP2_IRQ_RX 63
278#define INT_24XX_SPI1_IRQ 65
279#define INT_24XX_SPI2_IRQ 66
272#define INT_24XX_UART1_IRQ 72 280#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73 281#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74 282#define INT_24XX_UART3_IRQ 74
@@ -278,7 +286,58 @@
278#define INT_24XX_USB_IRQ_HGEN 78 286#define INT_24XX_USB_IRQ_HGEN 78
279#define INT_24XX_USB_IRQ_HSOF 79 287#define INT_24XX_USB_IRQ_HSOF 79
280#define INT_24XX_USB_IRQ_OTG 80 288#define INT_24XX_USB_IRQ_OTG 80
289#define INT_24XX_MCBSP5_IRQ_TX 81
290#define INT_24XX_MCBSP5_IRQ_RX 82
281#define INT_24XX_MMC_IRQ 83 291#define INT_24XX_MMC_IRQ 83
292#define INT_24XX_MMC2_IRQ 86
293#define INT_24XX_MCBSP3_IRQ_TX 89
294#define INT_24XX_MCBSP3_IRQ_RX 90
295#define INT_24XX_SPI3_IRQ 91
296
297#define INT_243X_MCBSP2_IRQ 16
298#define INT_243X_MCBSP3_IRQ 17
299#define INT_243X_MCBSP4_IRQ 18
300#define INT_243X_MCBSP5_IRQ 19
301#define INT_243X_MCBSP1_IRQ 64
302#define INT_243X_HS_USB_MC 92
303#define INT_243X_HS_USB_DMA 93
304#define INT_243X_CARKIT_IRQ 94
305
306#define INT_34XX_BENCH_MPU_EMUL 3
307#define INT_34XX_ST_MCBSP2_IRQ 4
308#define INT_34XX_ST_MCBSP3_IRQ 5
309#define INT_34XX_SSM_ABORT_IRQ 6
310#define INT_34XX_SYS_NIRQ 7
311#define INT_34XX_D2D_FW_IRQ 8
312#define INT_34XX_PRCM_MPU_IRQ 11
313#define INT_34XX_MCBSP1_IRQ 16
314#define INT_34XX_MCBSP2_IRQ 17
315#define INT_34XX_MCBSP3_IRQ 22
316#define INT_34XX_MCBSP4_IRQ 23
317#define INT_34XX_CAM_IRQ 24
318#define INT_34XX_MCBSP5_IRQ 27
319#define INT_34XX_GPIO_BANK1 29
320#define INT_34XX_GPIO_BANK2 30
321#define INT_34XX_GPIO_BANK3 31
322#define INT_34XX_GPIO_BANK4 32
323#define INT_34XX_GPIO_BANK5 33
324#define INT_34XX_GPIO_BANK6 34
325#define INT_34XX_USIM_IRQ 35
326#define INT_34XX_WDT3_IRQ 36
327#define INT_34XX_SPI4_IRQ 48
328#define INT_34XX_SHA1MD52_IRQ 49
329#define INT_34XX_FPKA_READY_IRQ 50
330#define INT_34XX_SHA1MD51_IRQ 51
331#define INT_34XX_RNG_IRQ 52
332#define INT_34XX_I2C3_IRQ 61
333#define INT_34XX_FPKA_ERROR_IRQ 64
334#define INT_34XX_PBIAS_IRQ 75
335#define INT_34XX_OHCI_IRQ 76
336#define INT_34XX_EHCI_IRQ 77
337#define INT_34XX_TLL_IRQ 78
338#define INT_34XX_PARTHASH_IRQ 79
339#define INT_34XX_MMC3_IRQ 94
340#define INT_34XX_GPT12_IRQ 95
282 341
283#define INT_34XX_BENCH_MPU_EMUL 3 342#define INT_34XX_BENCH_MPU_EMUL 3
284 343
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 8fdb95e26fcd..6a0d1a0a24a7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -43,9 +43,15 @@
43 43
44#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
46#define OMAP2430_MCBSP3_BASE 0x4808c000
47#define OMAP2430_MCBSP4_BASE 0x4808e000
48#define OMAP2430_MCBSP5_BASE 0x48096000
46 49
47#define OMAP34XX_MCBSP1_BASE 0x48074000 50#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000 51#define OMAP34XX_MCBSP2_BASE 0x49022000
52#define OMAP34XX_MCBSP3_BASE 0x49024000
53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000
49 55
50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
51 57
@@ -81,9 +87,6 @@
81#define OMAP_MCBSP_REG_XCERG 0x3A 87#define OMAP_MCBSP_REG_XCERG 0x3A
82#define OMAP_MCBSP_REG_XCERH 0x3C 88#define OMAP_MCBSP_REG_XCERH 0x3C
83 89
84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
86
87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 90#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 91#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
89 92
@@ -91,12 +94,14 @@
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 94#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 95#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93 96
94#elif defined(CONFIG_ARCH_OMAP24XX) 97#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
95 98
96#define OMAP_MCBSP_REG_DRR2 0x00 99#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04 100#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08 101#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C 102#define OMAP_MCBSP_REG_DXR1 0x0C
103#define OMAP_MCBSP_REG_DRR 0x00
104#define OMAP_MCBSP_REG_DXR 0x08
100#define OMAP_MCBSP_REG_SPCR2 0x10 105#define OMAP_MCBSP_REG_SPCR2 0x10
101#define OMAP_MCBSP_REG_SPCR1 0x14 106#define OMAP_MCBSP_REG_SPCR1 0x14
102#define OMAP_MCBSP_REG_RCR2 0x18 107#define OMAP_MCBSP_REG_RCR2 0x18
@@ -124,9 +129,9 @@
124#define OMAP_MCBSP_REG_RCERH 0x70 129#define OMAP_MCBSP_REG_RCERH 0x70
125#define OMAP_MCBSP_REG_XCERG 0x74 130#define OMAP_MCBSP_REG_XCERG 0x74
126#define OMAP_MCBSP_REG_XCERH 0x78 131#define OMAP_MCBSP_REG_XCERH 0x78
127 132#define OMAP_MCBSP_REG_SYSCON 0x8C
128#define OMAP_MAX_MCBSP_COUNT 2 133#define OMAP_MCBSP_REG_XCCR 0xAC
129#define MAX_MCBSP_CLOCKS 2 134#define OMAP_MCBSP_REG_RCCR 0xB0
130 135
131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 136#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 137#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -137,10 +142,6 @@
137 142
138#endif 143#endif
139 144
140#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
141#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
142
143
144/************************** McBSP SPCR1 bit definitions ***********************/ 145/************************** McBSP SPCR1 bit definitions ***********************/
145#define RRST 0x0001 146#define RRST 0x0001
146#define RRDY 0x0002 147#define RRDY 0x0002
@@ -151,6 +152,7 @@
151#define DXENA 0x0080 152#define DXENA 0x0080
152#define CLKSTP(value) ((value)<<11) /* bits 11:12 */ 153#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
153#define RJUST(value) ((value)<<13) /* bits 13:14 */ 154#define RJUST(value) ((value)<<13) /* bits 13:14 */
155#define ALB 0x8000
154#define DLB 0x8000 156#define DLB 0x8000
155 157
156/************************** McBSP SPCR2 bit definitions ***********************/ 158/************************** McBSP SPCR2 bit definitions ***********************/
@@ -228,6 +230,17 @@
228#define XPABLK(value) ((value)<<5) /* Bits 5:6 */ 230#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
229#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ 231#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
230 232
233/*********************** McBSP XCCR bit definitions *************************/
234#define DILB 0x0020
235#define XDMAEN 0x0008
236#define XDISABLE 0x0001
237
238/********************** McBSP RCCR bit definitions *************************/
239#define RDMAEN 0x0008
240#define RDISABLE 0x0001
241
242/********************** McBSP SYSCONFIG bit definitions ********************/
243#define SOFTRST 0x0002
231 244
232/* we don't do multichannel for now */ 245/* we don't do multichannel for now */
233struct omap_mcbsp_reg_cfg { 246struct omap_mcbsp_reg_cfg {
@@ -260,6 +273,8 @@ typedef enum {
260 OMAP_MCBSP1 = 0, 273 OMAP_MCBSP1 = 0,
261 OMAP_MCBSP2, 274 OMAP_MCBSP2,
262 OMAP_MCBSP3, 275 OMAP_MCBSP3,
276 OMAP_MCBSP4,
277 OMAP_MCBSP5
263} omap_mcbsp_id; 278} omap_mcbsp_id;
264 279
265typedef int __bitwise omap_mcbsp_io_type_t; 280typedef int __bitwise omap_mcbsp_io_type_t;
@@ -311,12 +326,10 @@ struct omap_mcbsp_spi_cfg {
311struct omap_mcbsp_ops { 326struct omap_mcbsp_ops {
312 void (*request)(unsigned int); 327 void (*request)(unsigned int);
313 void (*free)(unsigned int); 328 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315}; 329};
316 330
317struct omap_mcbsp_platform_data { 331struct omap_mcbsp_platform_data {
318 unsigned long phys_base; 332 unsigned long phys_base;
319 u32 virt_base;
320 u8 dma_rx_sync, dma_tx_sync; 333 u8 dma_rx_sync, dma_tx_sync;
321 u16 rx_irq, tx_irq; 334 u16 rx_irq, tx_irq;
322 struct omap_mcbsp_ops *ops; 335 struct omap_mcbsp_ops *ops;
@@ -326,7 +339,7 @@ struct omap_mcbsp_platform_data {
326struct omap_mcbsp { 339struct omap_mcbsp {
327 struct device *dev; 340 struct device *dev;
328 unsigned long phys_base; 341 unsigned long phys_base;
329 u32 io_base; 342 void __iomem *io_base;
330 u8 id; 343 u8 id;
331 u8 free; 344 u8 free;
332 omap_mcbsp_word_length rx_word_length; 345 omap_mcbsp_word_length rx_word_length;
@@ -354,6 +367,8 @@ struct omap_mcbsp {
354 struct omap_mcbsp_platform_data *pdata; 367 struct omap_mcbsp_platform_data *pdata;
355 struct clk *clk; 368 struct clk *clk;
356}; 369};
370extern struct omap_mcbsp **mcbsp_ptr;
371extern int omap_mcbsp_count;
357 372
358int omap_mcbsp_init(void); 373int omap_mcbsp_init(void);
359void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 374void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
@@ -378,5 +393,6 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
378/* Polled read/write functions */ 393/* Polled read/write functions */
379int omap_mcbsp_pollread(unsigned int id, u16 * buf); 394int omap_mcbsp_pollread(unsigned int id, u16 * buf);
380int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 395int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
396int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
381 397
382#endif 398#endif
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index a325caf80d04..d40cac60b959 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,7 @@
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) 41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
42#define PHYS_OFFSET UL(0x80000000) 42#define PHYS_OFFSET UL(0x80000000)
43#endif 43#endif
44 44
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 614b2c1327c7..6bbf1789bed5 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -125,20 +125,64 @@
125 .pu_pd_val = pull_mode, \ 125 .pu_pd_val = pull_mode, \
126}, 126},
127 127
128 128/* 24xx/34xx mux bit defines */
129#define PULL_DISABLED 0 129#define OMAP2_PULL_ENA (1 << 3)
130#define PULL_ENABLED 1 130#define OMAP2_PULL_UP (1 << 4)
131 131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132#define PULL_DOWN 0 132
133#define PULL_UP 1 133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
134 175
135struct pin_config { 176struct pin_config {
136 char *name; 177 char *name;
137 unsigned char busy; 178 const unsigned int mux_reg;
138 unsigned char debug; 179 unsigned char debug;
139 180
140 const char *mux_reg_name; 181#if defined(CONFIG_ARCH_OMAP34XX)
141 const unsigned int mux_reg; 182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
142 const unsigned char mask_offset; 186 const unsigned char mask_offset;
143 const unsigned char mask; 187 const unsigned char mask;
144 188
@@ -150,6 +194,12 @@ struct pin_config {
150 const char *pu_pd_name; 194 const char *pu_pd_name;
151 const unsigned int pu_pd_reg; 195 const unsigned int pu_pd_reg;
152 const unsigned char pu_pd_val; 196 const unsigned char pu_pd_val;
197#endif
198
199#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
201#endif
202
153}; 203};
154 204
155enum omap730_index { 205enum omap730_index {
@@ -593,6 +643,114 @@ enum omap24xx_index {
593 643
594}; 644};
595 645
646enum omap34xx_index {
647 /* 34xx I2C */
648 K21_34XX_I2C1_SCL,
649 J21_34XX_I2C1_SDA,
650 AF15_34XX_I2C2_SCL,
651 AE15_34XX_I2C2_SDA,
652 AF14_34XX_I2C3_SCL,
653 AG14_34XX_I2C3_SDA,
654 AD26_34XX_I2C4_SCL,
655 AE26_34XX_I2C4_SDA,
656
657 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
658 Y8_3430_USB1HS_PHY_CLK,
659 Y9_3430_USB1HS_PHY_STP,
660 AA14_3430_USB1HS_PHY_DIR,
661 AA11_3430_USB1HS_PHY_NXT,
662 W13_3430_USB1HS_PHY_DATA0,
663 W12_3430_USB1HS_PHY_DATA1,
664 W11_3430_USB1HS_PHY_DATA2,
665 Y11_3430_USB1HS_PHY_DATA3,
666 W9_3430_USB1HS_PHY_DATA4,
667 Y12_3430_USB1HS_PHY_DATA5,
668 W8_3430_USB1HS_PHY_DATA6,
669 Y13_3430_USB1HS_PHY_DATA7,
670
671 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
672 AA8_3430_USB2HS_PHY_CLK,
673 AA10_3430_USB2HS_PHY_STP,
674 AA9_3430_USB2HS_PHY_DIR,
675 AB11_3430_USB2HS_PHY_NXT,
676 AB10_3430_USB2HS_PHY_DATA0,
677 AB9_3430_USB2HS_PHY_DATA1,
678 W3_3430_USB2HS_PHY_DATA2,
679 T4_3430_USB2HS_PHY_DATA3,
680 T3_3430_USB2HS_PHY_DATA4,
681 R3_3430_USB2HS_PHY_DATA5,
682 R4_3430_USB2HS_PHY_DATA6,
683 T2_3430_USB2HS_PHY_DATA7,
684
685
686 /* TLL - HSUSB: 12-pin TLL Port 1*/
687 Y8_3430_USB1HS_TLL_CLK,
688 Y9_3430_USB1HS_TLL_STP,
689 AA14_3430_USB1HS_TLL_DIR,
690 AA11_3430_USB1HS_TLL_NXT,
691 W13_3430_USB1HS_TLL_DATA0,
692 W12_3430_USB1HS_TLL_DATA1,
693 W11_3430_USB1HS_TLL_DATA2,
694 Y11_3430_USB1HS_TLL_DATA3,
695 W9_3430_USB1HS_TLL_DATA4,
696 Y12_3430_USB1HS_TLL_DATA5,
697 W8_3430_USB1HS_TLL_DATA6,
698 Y13_3430_USB1HS_TLL_DATA7,
699
700 /* TLL - HSUSB: 12-pin TLL Port 2*/
701 AA8_3430_USB2HS_TLL_CLK,
702 AA10_3430_USB2HS_TLL_STP,
703 AA9_3430_USB2HS_TLL_DIR,
704 AB11_3430_USB2HS_TLL_NXT,
705 AB10_3430_USB2HS_TLL_DATA0,
706 AB9_3430_USB2HS_TLL_DATA1,
707 W3_3430_USB2HS_TLL_DATA2,
708 T4_3430_USB2HS_TLL_DATA3,
709 T3_3430_USB2HS_TLL_DATA4,
710 R3_3430_USB2HS_TLL_DATA5,
711 R4_3430_USB2HS_TLL_DATA6,
712 T2_3430_USB2HS_TLL_DATA7,
713
714 /* TLL - HSUSB: 12-pin TLL Port 3*/
715 AA6_3430_USB3HS_TLL_CLK,
716 AB3_3430_USB3HS_TLL_STP,
717 AA3_3430_USB3HS_TLL_DIR,
718 Y3_3430_USB3HS_TLL_NXT,
719 AA5_3430_USB3HS_TLL_DATA0,
720 Y4_3430_USB3HS_TLL_DATA1,
721 Y5_3430_USB3HS_TLL_DATA2,
722 W5_3430_USB3HS_TLL_DATA3,
723 AB12_3430_USB3HS_TLL_DATA4,
724 AB13_3430_USB3HS_TLL_DATA5,
725 AA13_3430_USB3HS_TLL_DATA6,
726 AA12_3430_USB3HS_TLL_DATA7,
727
728 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
729 AF10_3430_USB1FS_PHY_MM1_RXDP,
730 AG9_3430_USB1FS_PHY_MM1_RXDM,
731 W13_3430_USB1FS_PHY_MM1_RXRCV,
732 W12_3430_USB1FS_PHY_MM1_TXSE0,
733 W11_3430_USB1FS_PHY_MM1_TXDAT,
734 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
735
736 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
737 AF7_3430_USB2FS_PHY_MM2_RXDP,
738 AH7_3430_USB2FS_PHY_MM2_RXDM,
739 AB10_3430_USB2FS_PHY_MM2_RXRCV,
740 AB9_3430_USB2FS_PHY_MM2_TXSE0,
741 W3_3430_USB2FS_PHY_MM2_TXDAT,
742 T4_3430_USB2FS_PHY_MM2_TXEN_N,
743
744 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
745 AH3_3430_USB3FS_PHY_MM3_RXDP,
746 AE3_3430_USB3FS_PHY_MM3_RXDM,
747 AD1_3430_USB3FS_PHY_MM3_RXRCV,
748 AE1_3430_USB3FS_PHY_MM3_TXSE0,
749 AD2_3430_USB3FS_PHY_MM3_TXDAT,
750 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
751
752};
753
596struct omap_mux_cfg { 754struct omap_mux_cfg {
597 struct pin_config *pins; 755 struct pin_config *pins;
598 unsigned long size; 756 unsigned long size;
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h
index 505a38af8b22..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/mach/omap1510.h
@@ -44,5 +44,7 @@
44#define OMAP1510_DSPREG_SIZE SZ_128K 44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000 45#define OMAP1510_DSPREG_START 0xE1000000
46 46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
47#endif /* __ASM_ARCH_OMAP15XX_H */ 49#endif /* __ASM_ARCH_OMAP15XX_H */
48 50
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h
index c6c93afb2788..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/mach/omap16xx.h
@@ -44,6 +44,11 @@
44#define OMAP16XX_DSPREG_SIZE SZ_128K 44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000 45#define OMAP16XX_DSPREG_START 0xE1000000
46 46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
47/* 52/*
48 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
49 * Interrupts 54 * Interrupts
@@ -190,7 +195,7 @@
190#define WSPR_DISABLE_0 (0x0000aaaa) 195#define WSPR_DISABLE_0 (0x0000aaaa)
191#define WSPR_DISABLE_1 (0x00005555) 196#define WSPR_DISABLE_1 (0x00005555)
192 197
193/* Mailbox */ 198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
194#define OMAP16XX_MAILBOX_BASE (0xfffcf000) 199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
195 200
196#endif /* __ASM_ARCH_OMAP16XX_H */ 201#endif /* __ASM_ARCH_OMAP16XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index bb8319d66e9f..24335d4932f5 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -39,7 +39,6 @@
39/* interrupt controller */ 39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42#define IRQ_SIR_IRQ 0x0040
43 42
44#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP2420_CTRL_BASE L4_24XX_BASE
45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
@@ -48,6 +47,7 @@
48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE 47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) 48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000 49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51 51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index cae037d13079..ec67fb428607 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -62,6 +62,7 @@
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
65#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 66#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
66 67
67/* Values from DSP must map to lower 16-bits */ 68/* Values from DSP must map to lower 16-bits */
@@ -305,6 +306,7 @@ struct lcd_ctrl {
305 int screen_width, 306 int screen_width,
306 int pos_x, int pos_y, int width, 307 int pos_x, int pos_y, int width,
307 int height, int color_mode); 308 int height, int color_mode);
309 int (*set_rotate) (int angle);
308 int (*setup_mem) (int plane, size_t size, 310 int (*setup_mem) (int plane, size_t size,
309 int mem_type, unsigned long *paddr); 311 int mem_type, unsigned long *paddr);
310 int (*mmap) (struct fb_info *info, 312 int (*mmap) (struct fb_info *info,
@@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
374extern struct lcd_ctrl omap2_disp_ctrl; 376extern struct lcd_ctrl omap2_disp_ctrl;
375#endif 377#endif
376 378
379extern void omapfb_reserve_sdram(void);
377extern void omapfb_register_panel(struct lcd_panel *panel); 380extern void omapfb_register_panel(struct lcd_panel *panel);
378extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); 381extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
379extern void omapfb_notify_clients(struct omapfb_device *fbdev, 382extern void omapfb_notify_clients(struct omapfb_device *fbdev,
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index bfa09325a5ff..768eb6e7abcf 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -39,11 +39,11 @@
39 * Register and offset definitions to be used in PM assembler code 39 * Register and offset definitions to be used in PM assembler code
40 * ---------------------------------------------------------------------------- 40 * ----------------------------------------------------------------------------
41 */ 41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00) 42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04 43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08 44#define ARM_IDLECT2_ASM_OFFSET 0x08
45 45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00) 46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c 47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49 49
@@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short); 135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short); 136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short); 137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); 138extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
139 void __iomem *sdrc_power);
139extern void omap730_idle_loop_suspend(void); 140extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void); 141extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void); 142extern void omap1610_idle_loop_suspend(void);
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
new file mode 100644
index 000000000000..2806a9c8e4d7
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -0,0 +1,166 @@
1/*
2 * OMAP2/3 powerdomain control
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
22#include <mach/cpu.h>
23
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
31/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON))
34
35#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_RET))
37
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
39
40
41/* Powerdomain flags */
42#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
43
44
45/*
46 * Number of memory banks that are power-controllable. On OMAP3430, the
47 * maximum is 4.
48 */
49#define PWRDM_MAX_MEM_BANKS 4
50
51/*
52 * Maximum number of clockdomains that can be associated with a powerdomain.
53 * CORE powerdomain is probably the worst case.
54 */
55#define PWRDM_MAX_CLKDMS 3
56
57/* XXX A completely arbitrary number. What is reasonable here? */
58#define PWRDM_TRANSITION_BAILOUT 100000
59
60struct clockdomain;
61struct powerdomain;
62
63/* Encodes dependencies between powerdomains - statically defined */
64struct pwrdm_dep {
65
66 /* Powerdomain name */
67 const char *pwrdm_name;
68
69 /* Powerdomain pointer - resolved by the powerdomain code */
70 struct powerdomain *pwrdm;
71
72 /* Flags to mark OMAP chip restrictions, etc. */
73 const struct omap_chip_id omap_chip;
74
75};
76
77struct powerdomain {
78
79 /* Powerdomain name */
80 const char *name;
81
82 /* the address offset from CM_BASE/PRM_BASE */
83 const s16 prcm_offs;
84
85 /* Used to represent the OMAP chip types containing this pwrdm */
86 const struct omap_chip_id omap_chip;
87
88 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
89 const u8 dep_bit;
90
91 /* Powerdomains that can be told to wake this powerdomain up */
92 struct pwrdm_dep *wkdep_srcs;
93
94 /* Powerdomains that can be told to keep this pwrdm from inactivity */
95 struct pwrdm_dep *sleepdep_srcs;
96
97 /* Possible powerdomain power states */
98 const u8 pwrsts;
99
100 /* Possible logic power states when pwrdm in RETENTION */
101 const u8 pwrsts_logic_ret;
102
103 /* Powerdomain flags */
104 const u8 flags;
105
106 /* Number of software-controllable memory banks in this powerdomain */
107 const u8 banks;
108
109 /* Possible memory bank pwrstates when pwrdm in RETENTION */
110 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
111
112 /* Possible memory bank pwrstates when pwrdm is ON */
113 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
114
115 /* Clockdomains in this powerdomain */
116 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
117
118 struct list_head node;
119
120};
121
122
123void pwrdm_init(struct powerdomain **pwrdm_list);
124
125int pwrdm_register(struct powerdomain *pwrdm);
126int pwrdm_unregister(struct powerdomain *pwrdm);
127struct powerdomain *pwrdm_lookup(const char *name);
128
129int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
130
131int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
132int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
133int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
134 int (*fn)(struct powerdomain *pwrdm,
135 struct clockdomain *clkdm));
136
137int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
138int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
139int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
140int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
141int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
142int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
143
144int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
145
146int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
147int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
148int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
149int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
150
151int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
152int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
153int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
154
155int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
156int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
157int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
158int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
159
160int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
161int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
162bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
163
164int pwrdm_wait_transition(struct powerdomain *pwrdm);
165
166#endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 787b7acec546..a98c6c3beb2c 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -25,6 +25,8 @@
25#define SDRC_DLLB_STATUS 0x06C 25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070 26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084 27#define SDRC_MR_0 0x084
28#define SDRC_ACTIM_CTRL_A_0 0x09c
29#define SDRC_ACTIM_CTRL_B_0 0x0a0
28#define SDRC_RFR_CTRL_0 0x0a4 30#define SDRC_RFR_CTRL_0 0x0a4
29 31
30/* 32/*
@@ -63,9 +65,9 @@
63 */ 65 */
64 66
65 67
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 68#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 69#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 70#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69 71
70/* SMS register offsets - read/write with sms_{read,write}_reg() */ 72/* SMS register offsets - read/write with sms_{read,write}_reg() */
71 73
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index cc6bfa51ccb5..8a676a04be48 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -20,18 +20,24 @@
20#define OMAP_UART1_BASE 0x4806a000 20#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000 21#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000 22#define OMAP_UART3_BASE 0x4806e000
23#elif defined(CONFIG_ARCH_OMAP3)
24/* OMAP3 serial ports */
25#define OMAP_UART1_BASE 0x4806a000
26#define OMAP_UART2_BASE 0x4806c000
27#define OMAP_UART3_BASE 0x49020000
23#endif 28#endif
24 29
25#define OMAP_MAX_NR_PORTS 3 30#define OMAP_MAX_NR_PORTS 3
26#define OMAP1510_BASE_BAUD (12000000/16) 31#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16) 32#define OMAP16XX_BASE_BAUD (48000000/16)
33#define OMAP24XX_BASE_BAUD (48000000/16)
28 34
29#define is_omap_port(p) ({int __ret = 0; \ 35#define is_omap_port(pt) ({int __ret = 0; \
30 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \ 36 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
31 p == IO_ADDRESS(OMAP_UART2_BASE) || \ 37 (pt)->port.mapbase == OMAP_UART2_BASE || \
32 p == IO_ADDRESS(OMAP_UART3_BASE)) \ 38 (pt)->port.mapbase == OMAP_UART3_BASE) \
33 __ret = 1; \ 39 __ret = 1; \
34 __ret; \ 40 __ret; \
35 }) 41 })
36 42
37#endif 43#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index e09323449981..ab35d622dcf5 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type); 21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2);
27
24/* Do not use these */ 28/* Do not use these */
25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 29extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long omap1_sram_reprogram_clock_sz; 30extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type); 57 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz; 58extern unsigned long omap243x_sram_reprogram_sdrc_sz;
55 59
60
61extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
62 u32 sdrc_actim_ctrla,
63 u32 sdrc_actim_ctrlb, u32 m2);
64extern unsigned long omap3_sram_configure_core_dpll_sz;
65
56#endif 66#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 06a28c7b98de..06923f261545 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
40 40
41static inline void arch_reset(char mode) 41static inline void arch_reset(char mode)
42{ 42{
43 if (!cpu_is_omap24xx()) 43 if (!cpu_class_is_omap2())
44 omap1_arch_reset(mode); 44 omap1_arch_reset(mode);
45 else 45 else
46 omap_prcm_arch_reset(mode); 46 omap_prcm_arch_reset(mode);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 07:13:51 -0500