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-rw-r--r--arch/arm/plat-omap/clock.c1315
1 files changed, 140 insertions, 1175 deletions
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index a020fe16428f..7ce39b986e23 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,15 +1,20 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/clock.c 2 * linux/arch/arm/plat-omap/clock.c
3 * 3 *
4 * Copyright (C) 2004 Nokia corporation 4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
8 *
7 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
10 */ 12 */
11#include <linux/module.h> 13#include <linux/version.h>
14#include <linux/config.h>
12#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
13#include <linux/list.h> 18#include <linux/list.h>
14#include <linux/errno.h> 19#include <linux/errno.h>
15#include <linux/err.h> 20#include <linux/err.h>
@@ -18,562 +23,20 @@
18#include <asm/io.h> 23#include <asm/io.h>
19#include <asm/semaphore.h> 24#include <asm/semaphore.h>
20#include <asm/hardware/clock.h> 25#include <asm/hardware/clock.h>
21#include <asm/arch/board.h>
22#include <asm/arch/usb.h>
23 26
24#include "clock.h" 27#include <asm/arch/clock.h>
25#include "sram.h"
26 28
27static LIST_HEAD(clocks); 29LIST_HEAD(clocks);
28static DECLARE_MUTEX(clocks_sem); 30static DECLARE_MUTEX(clocks_sem);
29static DEFINE_SPINLOCK(clockfw_lock); 31DEFINE_SPINLOCK(clockfw_lock);
30static void propagate_rate(struct clk * clk);
31/* UART clock function */
32static int set_uart_rate(struct clk * clk, unsigned long rate);
33/* External clock (MCLK & BCLK) functions */
34static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
35static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
36static void init_ext_clk(struct clk * clk);
37/* MPU virtual clock functions */
38static int select_table_rate(struct clk * clk, unsigned long rate);
39static long round_to_table_rate(struct clk * clk, unsigned long rate);
40void clk_setdpll(__u16, __u16);
41
42static struct mpu_rate rate_table[] = {
43 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
44 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
45 */
46#if defined(CONFIG_OMAP_ARM_216MHZ)
47 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
48#endif
49#if defined(CONFIG_OMAP_ARM_195MHZ)
50 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
51#endif
52#if defined(CONFIG_OMAP_ARM_192MHZ)
53 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
54 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
55 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
56 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
57 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
58#endif
59#if defined(CONFIG_OMAP_ARM_182MHZ)
60 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
61#endif
62#if defined(CONFIG_OMAP_ARM_168MHZ)
63 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
64#endif
65#if defined(CONFIG_OMAP_ARM_150MHZ)
66 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
67#endif
68#if defined(CONFIG_OMAP_ARM_120MHZ)
69 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
70#endif
71#if defined(CONFIG_OMAP_ARM_96MHZ)
72 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
73#endif
74#if defined(CONFIG_OMAP_ARM_60MHZ)
75 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
76#endif
77#if defined(CONFIG_OMAP_ARM_30MHZ)
78 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
79#endif
80 { 0, 0, 0, 0, 0 },
81};
82
83
84static void ckctl_recalc(struct clk * clk);
85int __clk_enable(struct clk *clk);
86void __clk_disable(struct clk *clk);
87void __clk_unuse(struct clk *clk);
88int __clk_use(struct clk *clk);
89
90
91static void followparent_recalc(struct clk * clk)
92{
93 clk->rate = clk->parent->rate;
94}
95
96
97static void watchdog_recalc(struct clk * clk)
98{
99 clk->rate = clk->parent->rate / 14;
100}
101
102static void uart_recalc(struct clk * clk)
103{
104 unsigned int val = omap_readl(clk->enable_reg);
105 if (val & clk->enable_bit)
106 clk->rate = 48000000;
107 else
108 clk->rate = 12000000;
109}
110
111static struct clk ck_ref = {
112 .name = "ck_ref",
113 .rate = 12000000,
114 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
115 ALWAYS_ENABLED,
116};
117
118static struct clk ck_dpll1 = {
119 .name = "ck_dpll1",
120 .parent = &ck_ref,
121 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
122 RATE_PROPAGATES | ALWAYS_ENABLED,
123};
124
125static struct clk ck_dpll1out = {
126 .name = "ck_dpll1out",
127 .parent = &ck_dpll1,
128 .flags = CLOCK_IN_OMAP16XX,
129 .enable_reg = ARM_IDLECT2,
130 .enable_bit = EN_CKOUT_ARM,
131 .recalc = &followparent_recalc,
132};
133
134static struct clk arm_ck = {
135 .name = "arm_ck",
136 .parent = &ck_dpll1,
137 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
138 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
139 .rate_offset = CKCTL_ARMDIV_OFFSET,
140 .recalc = &ckctl_recalc,
141};
142
143static struct clk armper_ck = {
144 .name = "armper_ck",
145 .parent = &ck_dpll1,
146 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
147 RATE_CKCTL,
148 .enable_reg = ARM_IDLECT2,
149 .enable_bit = EN_PERCK,
150 .rate_offset = CKCTL_PERDIV_OFFSET,
151 .recalc = &ckctl_recalc,
152};
153
154static struct clk arm_gpio_ck = {
155 .name = "arm_gpio_ck",
156 .parent = &ck_dpll1,
157 .flags = CLOCK_IN_OMAP1510,
158 .enable_reg = ARM_IDLECT2,
159 .enable_bit = EN_GPIOCK,
160 .recalc = &followparent_recalc,
161};
162
163static struct clk armxor_ck = {
164 .name = "armxor_ck",
165 .parent = &ck_ref,
166 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
167 .enable_reg = ARM_IDLECT2,
168 .enable_bit = EN_XORPCK,
169 .recalc = &followparent_recalc,
170};
171
172static struct clk armtim_ck = {
173 .name = "armtim_ck",
174 .parent = &ck_ref,
175 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
176 .enable_reg = ARM_IDLECT2,
177 .enable_bit = EN_TIMCK,
178 .recalc = &followparent_recalc,
179};
180
181static struct clk armwdt_ck = {
182 .name = "armwdt_ck",
183 .parent = &ck_ref,
184 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
185 .enable_reg = ARM_IDLECT2,
186 .enable_bit = EN_WDTCK,
187 .recalc = &watchdog_recalc,
188};
189
190static struct clk arminth_ck16xx = {
191 .name = "arminth_ck",
192 .parent = &arm_ck,
193 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
194 .recalc = &followparent_recalc,
195 /* Note: On 16xx the frequency can be divided by 2 by programming
196 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
197 *
198 * 1510 version is in TC clocks.
199 */
200};
201
202static struct clk dsp_ck = {
203 .name = "dsp_ck",
204 .parent = &ck_dpll1,
205 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
206 RATE_CKCTL,
207 .enable_reg = ARM_CKCTL,
208 .enable_bit = EN_DSPCK,
209 .rate_offset = CKCTL_DSPDIV_OFFSET,
210 .recalc = &ckctl_recalc,
211};
212
213static struct clk dspmmu_ck = {
214 .name = "dspmmu_ck",
215 .parent = &ck_dpll1,
216 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
217 RATE_CKCTL | ALWAYS_ENABLED,
218 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
219 .recalc = &ckctl_recalc,
220};
221
222static struct clk dspper_ck = {
223 .name = "dspper_ck",
224 .parent = &ck_dpll1,
225 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
226 RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
227 .enable_reg = DSP_IDLECT2,
228 .enable_bit = EN_PERCK,
229 .rate_offset = CKCTL_PERDIV_OFFSET,
230 .recalc = &followparent_recalc,
231 //.recalc = &ckctl_recalc,
232};
233
234static struct clk dspxor_ck = {
235 .name = "dspxor_ck",
236 .parent = &ck_ref,
237 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
238 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
239 .enable_reg = DSP_IDLECT2,
240 .enable_bit = EN_XORPCK,
241 .recalc = &followparent_recalc,
242};
243
244static struct clk dsptim_ck = {
245 .name = "dsptim_ck",
246 .parent = &ck_ref,
247 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
248 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_DSPTIMCK,
251 .recalc = &followparent_recalc,
252};
253
254static struct clk tc_ck = {
255 .name = "tc_ck",
256 .parent = &ck_dpll1,
257 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
258 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .rate_offset = CKCTL_TCDIV_OFFSET,
260 .recalc = &ckctl_recalc,
261};
262
263static struct clk arminth_ck1510 = {
264 .name = "arminth_ck",
265 .parent = &tc_ck,
266 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
267 .recalc = &followparent_recalc,
268 /* Note: On 1510 the frequency follows TC_CK
269 *
270 * 16xx version is in MPU clocks.
271 */
272};
273
274static struct clk tipb_ck = {
275 .name = "tibp_ck",
276 .parent = &tc_ck,
277 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
278 .recalc = &followparent_recalc,
279};
280
281static struct clk l3_ocpi_ck = {
282 .name = "l3_ocpi_ck",
283 .parent = &tc_ck,
284 .flags = CLOCK_IN_OMAP16XX,
285 .enable_reg = ARM_IDLECT3,
286 .enable_bit = EN_OCPI_CK,
287 .recalc = &followparent_recalc,
288};
289 32
290static struct clk tc1_ck = { 33static struct clk_functions *arch_clock;
291 .name = "tc1_ck",
292 .parent = &tc_ck,
293 .flags = CLOCK_IN_OMAP16XX,
294 .enable_reg = ARM_IDLECT3,
295 .enable_bit = EN_TC1_CK,
296 .recalc = &followparent_recalc,
297};
298 34
299static struct clk tc2_ck = { 35/*-------------------------------------------------------------------------
300 .name = "tc2_ck", 36 * Standard clock functions defined in asm/hardware/clock.h
301 .parent = &tc_ck, 37 *-------------------------------------------------------------------------*/
302 .flags = CLOCK_IN_OMAP16XX,
303 .enable_reg = ARM_IDLECT3,
304 .enable_bit = EN_TC2_CK,
305 .recalc = &followparent_recalc,
306};
307 38
308static struct clk dma_ck = { 39struct clk * clk_get(struct device *dev, const char *id)
309 .name = "dma_ck",
310 .parent = &tc_ck,
311 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
312 ALWAYS_ENABLED,
313 .recalc = &followparent_recalc,
314};
315
316static struct clk dma_lcdfree_ck = {
317 .name = "dma_lcdfree_ck",
318 .parent = &tc_ck,
319 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
320 .recalc = &followparent_recalc,
321};
322
323static struct clk api_ck = {
324 .name = "api_ck",
325 .parent = &tc_ck,
326 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
327 .enable_reg = ARM_IDLECT2,
328 .enable_bit = EN_APICK,
329 .recalc = &followparent_recalc,
330};
331
332static struct clk lb_ck = {
333 .name = "lb_ck",
334 .parent = &tc_ck,
335 .flags = CLOCK_IN_OMAP1510,
336 .enable_reg = ARM_IDLECT2,
337 .enable_bit = EN_LBCK,
338 .recalc = &followparent_recalc,
339};
340
341static struct clk rhea1_ck = {
342 .name = "rhea1_ck",
343 .parent = &tc_ck,
344 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
345 .recalc = &followparent_recalc,
346};
347
348static struct clk rhea2_ck = {
349 .name = "rhea2_ck",
350 .parent = &tc_ck,
351 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
352 .recalc = &followparent_recalc,
353};
354
355static struct clk lcd_ck = {
356 .name = "lcd_ck",
357 .parent = &ck_dpll1,
358 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
359 RATE_CKCTL,
360 .enable_reg = ARM_IDLECT2,
361 .enable_bit = EN_LCDCK,
362 .rate_offset = CKCTL_LCDDIV_OFFSET,
363 .recalc = &ckctl_recalc,
364};
365
366static struct clk uart1_1510 = {
367 .name = "uart1_ck",
368 /* Direct from ULPD, no parent */
369 .rate = 12000000,
370 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
371 .enable_reg = MOD_CONF_CTRL_0,
372 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
373 .set_rate = &set_uart_rate,
374 .recalc = &uart_recalc,
375};
376
377static struct clk uart1_16xx = {
378 .name = "uart1_ck",
379 /* Direct from ULPD, no parent */
380 .rate = 48000000,
381 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
382 .enable_reg = MOD_CONF_CTRL_0,
383 .enable_bit = 29,
384};
385
386static struct clk uart2_ck = {
387 .name = "uart2_ck",
388 /* Direct from ULPD, no parent */
389 .rate = 12000000,
390 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
391 ALWAYS_ENABLED,
392 .enable_reg = MOD_CONF_CTRL_0,
393 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
394 .set_rate = &set_uart_rate,
395 .recalc = &uart_recalc,
396};
397
398static struct clk uart3_1510 = {
399 .name = "uart3_ck",
400 /* Direct from ULPD, no parent */
401 .rate = 12000000,
402 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
403 .enable_reg = MOD_CONF_CTRL_0,
404 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
405 .set_rate = &set_uart_rate,
406 .recalc = &uart_recalc,
407};
408
409static struct clk uart3_16xx = {
410 .name = "uart3_ck",
411 /* Direct from ULPD, no parent */
412 .rate = 48000000,
413 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
414 .enable_reg = MOD_CONF_CTRL_0,
415 .enable_bit = 31,
416};
417
418static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
419 .name = "usb_clko",
420 /* Direct from ULPD, no parent */
421 .rate = 6000000,
422 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
423 RATE_FIXED | ENABLE_REG_32BIT,
424 .enable_reg = ULPD_CLOCK_CTRL,
425 .enable_bit = USB_MCLK_EN_BIT,
426};
427
428static struct clk usb_hhc_ck1510 = {
429 .name = "usb_hhc_ck",
430 /* Direct from ULPD, no parent */
431 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
432 .flags = CLOCK_IN_OMAP1510 |
433 RATE_FIXED | ENABLE_REG_32BIT,
434 .enable_reg = MOD_CONF_CTRL_0,
435 .enable_bit = USB_HOST_HHC_UHOST_EN,
436};
437
438static struct clk usb_hhc_ck16xx = {
439 .name = "usb_hhc_ck",
440 /* Direct from ULPD, no parent */
441 .rate = 48000000,
442 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
443 .flags = CLOCK_IN_OMAP16XX |
444 RATE_FIXED | ENABLE_REG_32BIT,
445 .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
446 .enable_bit = 8 /* UHOST_EN */,
447};
448
449static struct clk usb_dc_ck = {
450 .name = "usb_dc_ck",
451 /* Direct from ULPD, no parent */
452 .rate = 48000000,
453 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
454 .enable_reg = SOFT_REQ_REG,
455 .enable_bit = 4,
456};
457
458static struct clk mclk_1510 = {
459 .name = "mclk",
460 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
461 .rate = 12000000,
462 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
463};
464
465static struct clk mclk_16xx = {
466 .name = "mclk",
467 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
468 .flags = CLOCK_IN_OMAP16XX,
469 .enable_reg = COM_CLK_DIV_CTRL_SEL,
470 .enable_bit = COM_ULPD_PLL_CLK_REQ,
471 .set_rate = &set_ext_clk_rate,
472 .round_rate = &round_ext_clk_rate,
473 .init = &init_ext_clk,
474};
475
476static struct clk bclk_1510 = {
477 .name = "bclk",
478 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
479 .rate = 12000000,
480 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
481};
482
483static struct clk bclk_16xx = {
484 .name = "bclk",
485 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
486 .flags = CLOCK_IN_OMAP16XX,
487 .enable_reg = SWD_CLK_DIV_CTRL_SEL,
488 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
489 .set_rate = &set_ext_clk_rate,
490 .round_rate = &round_ext_clk_rate,
491 .init = &init_ext_clk,
492};
493
494static struct clk mmc1_ck = {
495 .name = "mmc1_ck",
496 /* Functional clock is direct from ULPD, interface clock is ARMPER */
497 .parent = &armper_ck,
498 .rate = 48000000,
499 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
500 RATE_FIXED | ENABLE_REG_32BIT,
501 .enable_reg = MOD_CONF_CTRL_0,
502 .enable_bit = 23,
503};
504
505static struct clk mmc2_ck = {
506 .name = "mmc2_ck",
507 /* Functional clock is direct from ULPD, interface clock is ARMPER */
508 .parent = &armper_ck,
509 .rate = 48000000,
510 .flags = CLOCK_IN_OMAP16XX |
511 RATE_FIXED | ENABLE_REG_32BIT,
512 .enable_reg = MOD_CONF_CTRL_0,
513 .enable_bit = 20,
514};
515
516static struct clk virtual_ck_mpu = {
517 .name = "mpu",
518 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
519 VIRTUAL_CLOCK | ALWAYS_ENABLED,
520 .parent = &arm_ck, /* Is smarter alias for */
521 .recalc = &followparent_recalc,
522 .set_rate = &select_table_rate,
523 .round_rate = &round_to_table_rate,
524};
525
526
527static struct clk * onchip_clks[] = {
528 /* non-ULPD clocks */
529 &ck_ref,
530 &ck_dpll1,
531 /* CK_GEN1 clocks */
532 &ck_dpll1out,
533 &arm_ck,
534 &armper_ck,
535 &arm_gpio_ck,
536 &armxor_ck,
537 &armtim_ck,
538 &armwdt_ck,
539 &arminth_ck1510, &arminth_ck16xx,
540 /* CK_GEN2 clocks */
541 &dsp_ck,
542 &dspmmu_ck,
543 &dspper_ck,
544 &dspxor_ck,
545 &dsptim_ck,
546 /* CK_GEN3 clocks */
547 &tc_ck,
548 &tipb_ck,
549 &l3_ocpi_ck,
550 &tc1_ck,
551 &tc2_ck,
552 &dma_ck,
553 &dma_lcdfree_ck,
554 &api_ck,
555 &lb_ck,
556 &rhea1_ck,
557 &rhea2_ck,
558 &lcd_ck,
559 /* ULPD clocks */
560 &uart1_1510,
561 &uart1_16xx,
562 &uart2_ck,
563 &uart3_1510,
564 &uart3_16xx,
565 &usb_clko,
566 &usb_hhc_ck1510, &usb_hhc_ck16xx,
567 &usb_dc_ck,
568 &mclk_1510, &mclk_16xx,
569 &bclk_1510, &bclk_16xx,
570 &mmc1_ck,
571 &mmc2_ck,
572 /* Virtual clocks */
573 &virtual_ck_mpu,
574};
575
576struct clk *clk_get(struct device *dev, const char *id)
577{ 40{
578 struct clk *p, *clk = ERR_PTR(-ENOENT); 41 struct clk *p, *clk = ERR_PTR(-ENOENT);
579 42
@@ -590,534 +53,200 @@ struct clk *clk_get(struct device *dev, const char *id)
590} 53}
591EXPORT_SYMBOL(clk_get); 54EXPORT_SYMBOL(clk_get);
592 55
593
594void clk_put(struct clk *clk)
595{
596 if (clk && !IS_ERR(clk))
597 module_put(clk->owner);
598}
599EXPORT_SYMBOL(clk_put);
600
601
602int __clk_enable(struct clk *clk)
603{
604 __u16 regval16;
605 __u32 regval32;
606
607 if (clk->flags & ALWAYS_ENABLED)
608 return 0;
609
610 if (unlikely(clk->enable_reg == 0)) {
611 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
612 clk->name);
613 return 0;
614 }
615
616 if (clk->flags & DSP_DOMAIN_CLOCK) {
617 __clk_use(&api_ck);
618 }
619
620 if (clk->flags & ENABLE_REG_32BIT) {
621 if (clk->flags & VIRTUAL_IO_ADDRESS) {
622 regval32 = __raw_readl(clk->enable_reg);
623 regval32 |= (1 << clk->enable_bit);
624 __raw_writel(regval32, clk->enable_reg);
625 } else {
626 regval32 = omap_readl(clk->enable_reg);
627 regval32 |= (1 << clk->enable_bit);
628 omap_writel(regval32, clk->enable_reg);
629 }
630 } else {
631 if (clk->flags & VIRTUAL_IO_ADDRESS) {
632 regval16 = __raw_readw(clk->enable_reg);
633 regval16 |= (1 << clk->enable_bit);
634 __raw_writew(regval16, clk->enable_reg);
635 } else {
636 regval16 = omap_readw(clk->enable_reg);
637 regval16 |= (1 << clk->enable_bit);
638 omap_writew(regval16, clk->enable_reg);
639 }
640 }
641
642 if (clk->flags & DSP_DOMAIN_CLOCK) {
643 __clk_unuse(&api_ck);
644 }
645
646 return 0;
647}
648
649
650void __clk_disable(struct clk *clk)
651{
652 __u16 regval16;
653 __u32 regval32;
654
655 if (clk->enable_reg == 0)
656 return;
657
658 if (clk->flags & DSP_DOMAIN_CLOCK) {
659 __clk_use(&api_ck);
660 }
661
662 if (clk->flags & ENABLE_REG_32BIT) {
663 if (clk->flags & VIRTUAL_IO_ADDRESS) {
664 regval32 = __raw_readl(clk->enable_reg);
665 regval32 &= ~(1 << clk->enable_bit);
666 __raw_writel(regval32, clk->enable_reg);
667 } else {
668 regval32 = omap_readl(clk->enable_reg);
669 regval32 &= ~(1 << clk->enable_bit);
670 omap_writel(regval32, clk->enable_reg);
671 }
672 } else {
673 if (clk->flags & VIRTUAL_IO_ADDRESS) {
674 regval16 = __raw_readw(clk->enable_reg);
675 regval16 &= ~(1 << clk->enable_bit);
676 __raw_writew(regval16, clk->enable_reg);
677 } else {
678 regval16 = omap_readw(clk->enable_reg);
679 regval16 &= ~(1 << clk->enable_bit);
680 omap_writew(regval16, clk->enable_reg);
681 }
682 }
683
684 if (clk->flags & DSP_DOMAIN_CLOCK) {
685 __clk_unuse(&api_ck);
686 }
687}
688
689
690void __clk_unuse(struct clk *clk)
691{
692 if (clk->usecount > 0 && !(--clk->usecount)) {
693 __clk_disable(clk);
694 if (likely(clk->parent))
695 __clk_unuse(clk->parent);
696 }
697}
698
699
700int __clk_use(struct clk *clk)
701{
702 int ret = 0;
703 if (clk->usecount++ == 0) {
704 if (likely(clk->parent))
705 ret = __clk_use(clk->parent);
706
707 if (unlikely(ret != 0)) {
708 clk->usecount--;
709 return ret;
710 }
711
712 ret = __clk_enable(clk);
713
714 if (unlikely(ret != 0) && clk->parent) {
715 __clk_unuse(clk->parent);
716 clk->usecount--;
717 }
718 }
719
720 return ret;
721}
722
723
724int clk_enable(struct clk *clk) 56int clk_enable(struct clk *clk)
725{ 57{
726 unsigned long flags; 58 unsigned long flags;
727 int ret; 59 int ret = 0;
728 60
729 spin_lock_irqsave(&clockfw_lock, flags); 61 spin_lock_irqsave(&clockfw_lock, flags);
730 ret = __clk_enable(clk); 62 if (clk->enable)
63 ret = clk->enable(clk);
64 else if (arch_clock->clk_enable)
65 ret = arch_clock->clk_enable(clk);
66 else
67 printk(KERN_ERR "Could not enable clock %s\n", clk->name);
731 spin_unlock_irqrestore(&clockfw_lock, flags); 68 spin_unlock_irqrestore(&clockfw_lock, flags);
69
732 return ret; 70 return ret;
733} 71}
734EXPORT_SYMBOL(clk_enable); 72EXPORT_SYMBOL(clk_enable);
735 73
736
737void clk_disable(struct clk *clk) 74void clk_disable(struct clk *clk)
738{ 75{
739 unsigned long flags; 76 unsigned long flags;
740 77
741 spin_lock_irqsave(&clockfw_lock, flags); 78 spin_lock_irqsave(&clockfw_lock, flags);
742 __clk_disable(clk); 79 if (clk->disable)
80 clk->disable(clk);
81 else if (arch_clock->clk_disable)
82 arch_clock->clk_disable(clk);
83 else
84 printk(KERN_ERR "Could not disable clock %s\n", clk->name);
743 spin_unlock_irqrestore(&clockfw_lock, flags); 85 spin_unlock_irqrestore(&clockfw_lock, flags);
744} 86}
745EXPORT_SYMBOL(clk_disable); 87EXPORT_SYMBOL(clk_disable);
746 88
747
748int clk_use(struct clk *clk) 89int clk_use(struct clk *clk)
749{ 90{
750 unsigned long flags; 91 unsigned long flags;
751 int ret = 0; 92 int ret = 0;
752 93
753 spin_lock_irqsave(&clockfw_lock, flags); 94 spin_lock_irqsave(&clockfw_lock, flags);
754 ret = __clk_use(clk); 95 if (arch_clock->clk_use)
96 ret = arch_clock->clk_use(clk);
755 spin_unlock_irqrestore(&clockfw_lock, flags); 97 spin_unlock_irqrestore(&clockfw_lock, flags);
98
756 return ret; 99 return ret;
757} 100}
758EXPORT_SYMBOL(clk_use); 101EXPORT_SYMBOL(clk_use);
759 102
760
761void clk_unuse(struct clk *clk) 103void clk_unuse(struct clk *clk)
762{ 104{
763 unsigned long flags; 105 unsigned long flags;
764 106
765 spin_lock_irqsave(&clockfw_lock, flags); 107 spin_lock_irqsave(&clockfw_lock, flags);
766 __clk_unuse(clk); 108 if (arch_clock->clk_unuse)
109 arch_clock->clk_unuse(clk);
767 spin_unlock_irqrestore(&clockfw_lock, flags); 110 spin_unlock_irqrestore(&clockfw_lock, flags);
768} 111}
769EXPORT_SYMBOL(clk_unuse); 112EXPORT_SYMBOL(clk_unuse);
770 113
771
772int clk_get_usecount(struct clk *clk) 114int clk_get_usecount(struct clk *clk)
773{ 115{
774 return clk->usecount; 116 unsigned long flags;
775} 117 int ret = 0;
776EXPORT_SYMBOL(clk_get_usecount);
777
778
779unsigned long clk_get_rate(struct clk *clk)
780{
781 return clk->rate;
782}
783EXPORT_SYMBOL(clk_get_rate);
784
785
786static __u16 verify_ckctl_value(__u16 newval)
787{
788 /* This function checks for following limitations set
789 * by the hardware (all conditions must be true):
790 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
791 * ARM_CK >= TC_CK
792 * DSP_CK >= TC_CK
793 * DSPMMU_CK >= TC_CK
794 *
795 * In addition following rules are enforced:
796 * LCD_CK <= TC_CK
797 * ARMPER_CK <= TC_CK
798 *
799 * However, maximum frequencies are not checked for!
800 */
801 __u8 per_exp;
802 __u8 lcd_exp;
803 __u8 arm_exp;
804 __u8 dsp_exp;
805 __u8 tc_exp;
806 __u8 dspmmu_exp;
807
808 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
809 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
810 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
811 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
812 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
813 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
814
815 if (dspmmu_exp < dsp_exp)
816 dspmmu_exp = dsp_exp;
817 if (dspmmu_exp > dsp_exp+1)
818 dspmmu_exp = dsp_exp+1;
819 if (tc_exp < arm_exp)
820 tc_exp = arm_exp;
821 if (tc_exp < dspmmu_exp)
822 tc_exp = dspmmu_exp;
823 if (tc_exp > lcd_exp)
824 lcd_exp = tc_exp;
825 if (tc_exp > per_exp)
826 per_exp = tc_exp;
827 118
828 newval &= 0xf000; 119 spin_lock_irqsave(&clockfw_lock, flags);
829 newval |= per_exp << CKCTL_PERDIV_OFFSET; 120 ret = clk->usecount;
830 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 121 spin_unlock_irqrestore(&clockfw_lock, flags);
831 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
832 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
833 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
834 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
835 122
836 return newval; 123 return ret;
837} 124}
125EXPORT_SYMBOL(clk_get_usecount);
838 126
839 127unsigned long clk_get_rate(struct clk *clk)
840static int calc_dsor_exp(struct clk *clk, unsigned long rate)
841{ 128{
842 /* Note: If target frequency is too low, this function will return 4, 129 unsigned long flags;
843 * which is invalid value. Caller must check for this value and act 130 unsigned long ret = 0;
844 * accordingly.
845 *
846 * Note: This function does not check for following limitations set
847 * by the hardware (all conditions must be true):
848 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
849 * ARM_CK >= TC_CK
850 * DSP_CK >= TC_CK
851 * DSPMMU_CK >= TC_CK
852 */
853 unsigned long realrate;
854 struct clk * parent;
855 unsigned dsor_exp;
856
857 if (unlikely(!(clk->flags & RATE_CKCTL)))
858 return -EINVAL;
859
860 parent = clk->parent;
861 if (unlikely(parent == 0))
862 return -EIO;
863
864 realrate = parent->rate;
865 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
866 if (realrate <= rate)
867 break;
868 131
869 realrate /= 2; 132 spin_lock_irqsave(&clockfw_lock, flags);
870 } 133 ret = clk->rate;
134 spin_unlock_irqrestore(&clockfw_lock, flags);
871 135
872 return dsor_exp; 136 return ret;
873} 137}
138EXPORT_SYMBOL(clk_get_rate);
874 139
875 140void clk_put(struct clk *clk)
876static void ckctl_recalc(struct clk * clk)
877{ 141{
878 int dsor; 142 if (clk && !IS_ERR(clk))
879 143 module_put(clk->owner);
880 /* Calculate divisor encoded as 2-bit exponent */
881 if (clk->flags & DSP_DOMAIN_CLOCK) {
882 /* The clock control bits are in DSP domain,
883 * so api_ck is needed for access.
884 * Note that DSP_CKCTL virt addr = phys addr, so
885 * we must use __raw_readw() instead of omap_readw().
886 */
887 __clk_use(&api_ck);
888 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
889 __clk_unuse(&api_ck);
890 } else {
891 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
892 }
893 if (unlikely(clk->rate == clk->parent->rate / dsor))
894 return; /* No change, quick exit */
895 clk->rate = clk->parent->rate / dsor;
896
897 if (unlikely(clk->flags & RATE_PROPAGATES))
898 propagate_rate(clk);
899} 144}
145EXPORT_SYMBOL(clk_put);
900 146
147/*-------------------------------------------------------------------------
148 * Optional clock functions defined in asm/hardware/clock.h
149 *-------------------------------------------------------------------------*/
901 150
902long clk_round_rate(struct clk *clk, unsigned long rate) 151long clk_round_rate(struct clk *clk, unsigned long rate)
903{ 152{
904 int dsor_exp; 153 unsigned long flags;
905 154 long ret = 0;
906 if (clk->flags & RATE_FIXED)
907 return clk->rate;
908
909 if (clk->flags & RATE_CKCTL) {
910 dsor_exp = calc_dsor_exp(clk, rate);
911 if (dsor_exp < 0)
912 return dsor_exp;
913 if (dsor_exp > 3)
914 dsor_exp = 3;
915 return clk->parent->rate / (1 << dsor_exp);
916 }
917 155
918 if(clk->round_rate != 0) 156 spin_lock_irqsave(&clockfw_lock, flags);
919 return clk->round_rate(clk, rate); 157 if (arch_clock->clk_round_rate)
158 ret = arch_clock->clk_round_rate(clk, rate);
159 spin_unlock_irqrestore(&clockfw_lock, flags);
920 160
921 return clk->rate; 161 return ret;
922} 162}
923EXPORT_SYMBOL(clk_round_rate); 163EXPORT_SYMBOL(clk_round_rate);
924 164
925 165int clk_set_rate(struct clk *clk, unsigned long rate)
926static void propagate_rate(struct clk * clk)
927{
928 struct clk ** clkp;
929
930 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
931 if (likely((*clkp)->parent != clk)) continue;
932 if (likely((*clkp)->recalc))
933 (*clkp)->recalc(*clkp);
934 }
935}
936
937
938static int select_table_rate(struct clk * clk, unsigned long rate)
939{ 166{
940 /* Find the highest supported frequency <= rate and switch to it */ 167 unsigned long flags;
941 struct mpu_rate * ptr; 168 int ret = 0;
942
943 if (clk != &virtual_ck_mpu)
944 return -EINVAL;
945
946 for (ptr = rate_table; ptr->rate; ptr++) {
947 if (ptr->xtal != ck_ref.rate)
948 continue;
949
950 /* DPLL1 cannot be reprogrammed without risking system crash */
951 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
952 continue;
953
954 /* Can check only after xtal frequency check */
955 if (ptr->rate <= rate)
956 break;
957 }
958
959 if (!ptr->rate)
960 return -EINVAL;
961 169
962 /* 170 spin_lock_irqsave(&clockfw_lock, flags);
963 * In most cases we should not need to reprogram DPLL. 171 if (arch_clock->clk_set_rate)
964 * Reprogramming the DPLL is tricky, it must be done from SRAM. 172 ret = arch_clock->clk_set_rate(clk, rate);
965 */ 173 spin_unlock_irqrestore(&clockfw_lock, flags);
966 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
967 174
968 ck_dpll1.rate = ptr->pll_rate; 175 return ret;
969 propagate_rate(&ck_dpll1);
970 return 0;
971} 176}
177EXPORT_SYMBOL(clk_set_rate);
972 178
973 179int clk_set_parent(struct clk *clk, struct clk *parent)
974static long round_to_table_rate(struct clk * clk, unsigned long rate)
975{ 180{
976 /* Find the highest supported frequency <= rate */ 181 unsigned long flags;
977 struct mpu_rate * ptr; 182 int ret = 0;
978 long highest_rate;
979
980 if (clk != &virtual_ck_mpu)
981 return -EINVAL;
982
983 highest_rate = -EINVAL;
984
985 for (ptr = rate_table; ptr->rate; ptr++) {
986 if (ptr->xtal != ck_ref.rate)
987 continue;
988
989 highest_rate = ptr->rate;
990 183
991 /* Can check only after xtal frequency check */ 184 spin_lock_irqsave(&clockfw_lock, flags);
992 if (ptr->rate <= rate) 185 if (arch_clock->clk_set_parent)
993 break; 186 ret = arch_clock->clk_set_parent(clk, parent);
994 } 187 spin_unlock_irqrestore(&clockfw_lock, flags);
995 188
996 return highest_rate; 189 return ret;
997} 190}
191EXPORT_SYMBOL(clk_set_parent);
998 192
999 193struct clk *clk_get_parent(struct clk *clk)
1000int clk_set_rate(struct clk *clk, unsigned long rate)
1001{ 194{
1002 int ret = -EINVAL; 195 unsigned long flags;
1003 int dsor_exp; 196 struct clk * ret = NULL;
1004 __u16 regval;
1005 unsigned long flags;
1006
1007 if (clk->flags & RATE_CKCTL) {
1008 dsor_exp = calc_dsor_exp(clk, rate);
1009 if (dsor_exp > 3)
1010 dsor_exp = -EINVAL;
1011 if (dsor_exp < 0)
1012 return dsor_exp;
1013
1014 spin_lock_irqsave(&clockfw_lock, flags);
1015 regval = omap_readw(ARM_CKCTL);
1016 regval &= ~(3 << clk->rate_offset);
1017 regval |= dsor_exp << clk->rate_offset;
1018 regval = verify_ckctl_value(regval);
1019 omap_writew(regval, ARM_CKCTL);
1020 clk->rate = clk->parent->rate / (1 << dsor_exp);
1021 spin_unlock_irqrestore(&clockfw_lock, flags);
1022 ret = 0;
1023 } else if(clk->set_rate != 0) {
1024 spin_lock_irqsave(&clockfw_lock, flags);
1025 ret = clk->set_rate(clk, rate);
1026 spin_unlock_irqrestore(&clockfw_lock, flags);
1027 }
1028 197
1029 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 198 spin_lock_irqsave(&clockfw_lock, flags);
1030 propagate_rate(clk); 199 if (arch_clock->clk_get_parent)
200 ret = arch_clock->clk_get_parent(clk);
201 spin_unlock_irqrestore(&clockfw_lock, flags);
1031 202
1032 return ret; 203 return ret;
1033} 204}
1034EXPORT_SYMBOL(clk_set_rate); 205EXPORT_SYMBOL(clk_get_parent);
1035 206
207/*-------------------------------------------------------------------------
208 * OMAP specific clock functions shared between omap1 and omap2
209 *-------------------------------------------------------------------------*/
1036 210
1037static unsigned calc_ext_dsor(unsigned long rate) 211unsigned int __initdata mpurate;
1038{
1039 unsigned dsor;
1040 212
1041 /* MCLK and BCLK divisor selection is not linear: 213/*
1042 * freq = 96MHz / dsor 214 * By default we use the rate set by the bootloader.
1043 * 215 * You can override this with mpurate= cmdline option.
1044 * RATIO_SEL range: dsor <-> RATIO_SEL 216 */
1045 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 217static int __init omap_clk_setup(char *str)
1046 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
1047 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
1048 * can not be used.
1049 */
1050 for (dsor = 2; dsor < 96; ++dsor) {
1051 if ((dsor & 1) && dsor > 8)
1052 continue;
1053 if (rate >= 96000000 / dsor)
1054 break;
1055 }
1056 return dsor;
1057}
1058
1059/* Only needed on 1510 */
1060static int set_uart_rate(struct clk * clk, unsigned long rate)
1061{
1062 unsigned int val;
1063
1064 val = omap_readl(clk->enable_reg);
1065 if (rate == 12000000)
1066 val &= ~(1 << clk->enable_bit);
1067 else if (rate == 48000000)
1068 val |= (1 << clk->enable_bit);
1069 else
1070 return -EINVAL;
1071 omap_writel(val, clk->enable_reg);
1072 clk->rate = rate;
1073
1074 return 0;
1075}
1076
1077static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
1078{ 218{
1079 unsigned dsor; 219 get_option(&str, &mpurate);
1080 __u16 ratio_bits;
1081 220
1082 dsor = calc_ext_dsor(rate); 221 if (!mpurate)
1083 clk->rate = 96000000 / dsor; 222 return 1;
1084 if (dsor > 8)
1085 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
1086 else
1087 ratio_bits = (dsor - 2) << 2;
1088 223
1089 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; 224 if (mpurate < 1000)
1090 omap_writew(ratio_bits, clk->enable_reg); 225 mpurate *= 1000000;
1091 226
1092 return 0; 227 return 1;
1093} 228}
229__setup("mpurate=", omap_clk_setup);
1094 230
1095 231/* Used for clocks that always have same value as the parent clock */
1096static long round_ext_clk_rate(struct clk * clk, unsigned long rate) 232void followparent_recalc(struct clk *clk)
1097{ 233{
1098 return 96000000 / calc_ext_dsor(rate); 234 clk->rate = clk->parent->rate;
1099} 235}
1100 236
1101 237/* Propagate rate to children */
1102static void init_ext_clk(struct clk * clk) 238void propagate_rate(struct clk * tclk)
1103{ 239{
1104 unsigned dsor; 240 struct clk *clkp;
1105 __u16 ratio_bits;
1106 241
1107 /* Determine current rate and ensure clock is based on 96MHz APLL */ 242 list_for_each_entry(clkp, &clocks, node) {
1108 ratio_bits = omap_readw(clk->enable_reg) & ~1; 243 if (likely(clkp->parent != tclk))
1109 omap_writew(ratio_bits, clk->enable_reg); 244 continue;
1110 245 if (likely((u32)clkp->recalc))
1111 ratio_bits = (ratio_bits & 0xfc) >> 2; 246 clkp->recalc(clkp);
1112 if (ratio_bits > 6) 247 }
1113 dsor = (ratio_bits - 6) * 2 + 8;
1114 else
1115 dsor = ratio_bits + 2;
1116
1117 clk-> rate = 96000000 / dsor;
1118} 248}
1119 249
1120
1121int clk_register(struct clk *clk) 250int clk_register(struct clk *clk)
1122{ 251{
1123 down(&clocks_sem); 252 down(&clocks_sem);
@@ -1125,6 +254,7 @@ int clk_register(struct clk *clk)
1125 if (clk->init) 254 if (clk->init)
1126 clk->init(clk); 255 clk->init(clk);
1127 up(&clocks_sem); 256 up(&clocks_sem);
257
1128 return 0; 258 return 0;
1129} 259}
1130EXPORT_SYMBOL(clk_register); 260EXPORT_SYMBOL(clk_register);
@@ -1137,203 +267,38 @@ void clk_unregister(struct clk *clk)
1137} 267}
1138EXPORT_SYMBOL(clk_unregister); 268EXPORT_SYMBOL(clk_unregister);
1139 269
1140#ifdef CONFIG_OMAP_RESET_CLOCKS 270void clk_deny_idle(struct clk *clk)
1141/*
1142 * Resets some clocks that may be left on from bootloader,
1143 * but leaves serial clocks on. See also omap_late_clk_reset().
1144 */
1145static inline void omap_early_clk_reset(void)
1146{ 271{
1147 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 272 unsigned long flags;
273
274 spin_lock_irqsave(&clockfw_lock, flags);
275 if (arch_clock->clk_deny_idle)
276 arch_clock->clk_deny_idle(clk);
277 spin_unlock_irqrestore(&clockfw_lock, flags);
1148} 278}
1149#else 279EXPORT_SYMBOL(clk_deny_idle);
1150#define omap_early_clk_reset() {}
1151#endif
1152 280
1153int __init clk_init(void) 281void clk_allow_idle(struct clk *clk)
1154{ 282{
1155 struct clk ** clkp; 283 unsigned long flags;
1156 const struct omap_clock_config *info;
1157 int crystal_type = 0; /* Default 12 MHz */
1158
1159 omap_early_clk_reset();
1160
1161 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
1162 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1163 clk_register(*clkp);
1164 continue;
1165 }
1166
1167 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1168 clk_register(*clkp);
1169 continue;
1170 }
1171
1172 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1173 clk_register(*clkp);
1174 continue;
1175 }
1176 }
1177
1178 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1179 if (info != NULL) {
1180 if (!cpu_is_omap1510())
1181 crystal_type = info->system_clock_type;
1182 }
1183
1184#if defined(CONFIG_ARCH_OMAP730)
1185 ck_ref.rate = 13000000;
1186#elif defined(CONFIG_ARCH_OMAP16XX)
1187 if (crystal_type == 2)
1188 ck_ref.rate = 19200000;
1189#endif
1190
1191 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1192 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1193 omap_readw(ARM_CKCTL));
1194
1195 /* We want to be in syncronous scalable mode */
1196 omap_writew(0x1000, ARM_SYSST);
1197
1198#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1199 /* Use values set by bootloader. Determine PLL rate and recalculate
1200 * dependent clocks as if kernel had changed PLL or divisors.
1201 */
1202 {
1203 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1204
1205 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1206 if (pll_ctl_val & 0x10) {
1207 /* PLL enabled, apply multiplier and divisor */
1208 if (pll_ctl_val & 0xf80)
1209 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1210 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1211 } else {
1212 /* PLL disabled, apply bypass divisor */
1213 switch (pll_ctl_val & 0xc) {
1214 case 0:
1215 break;
1216 case 0x4:
1217 ck_dpll1.rate /= 2;
1218 break;
1219 default:
1220 ck_dpll1.rate /= 4;
1221 break;
1222 }
1223 }
1224 }
1225 propagate_rate(&ck_dpll1);
1226#else
1227 /* Find the highest supported frequency and enable it */
1228 if (select_table_rate(&virtual_ck_mpu, ~0)) {
1229 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1230 /* Guess sane values (60MHz) */
1231 omap_writew(0x2290, DPLL_CTL);
1232 omap_writew(0x1005, ARM_CKCTL);
1233 ck_dpll1.rate = 60000000;
1234 propagate_rate(&ck_dpll1);
1235 }
1236#endif
1237 /* Cache rates for clocks connected to ck_ref (not dpll1) */
1238 propagate_rate(&ck_ref);
1239 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
1240 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
1241 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1242 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
1243 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
1244
1245#ifdef CONFIG_MACH_OMAP_PERSEUS2
1246 /* Select slicer output as OMAP input clock */
1247 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1248#endif
1249
1250 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1251 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1252
1253 /* Put DSP/MPUI into reset until needed */
1254 omap_writew(0, ARM_RSTCT1);
1255 omap_writew(1, ARM_RSTCT2);
1256 omap_writew(0x400, ARM_IDLECT1);
1257
1258 /*
1259 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1260 * of the ARM_IDLECT2 register must be set to zero. The power-on
1261 * default value of this bit is one.
1262 */
1263 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
1264
1265 /*
1266 * Only enable those clocks we will need, let the drivers
1267 * enable other clocks as necessary
1268 */
1269 clk_use(&armper_ck);
1270 clk_use(&armxor_ck);
1271 clk_use(&armtim_ck);
1272
1273 if (cpu_is_omap1510())
1274 clk_enable(&arm_gpio_ck);
1275 284
1276 return 0; 285 spin_lock_irqsave(&clockfw_lock, flags);
286 if (arch_clock->clk_allow_idle)
287 arch_clock->clk_allow_idle(clk);
288 spin_unlock_irqrestore(&clockfw_lock, flags);
1277} 289}
290EXPORT_SYMBOL(clk_allow_idle);
1278 291
292/*-------------------------------------------------------------------------*/
1279 293
1280#ifdef CONFIG_OMAP_RESET_CLOCKS 294int __init clk_init(struct clk_functions * custom_clocks)
1281
1282static int __init omap_late_clk_reset(void)
1283{ 295{
1284 /* Turn off all unused clocks */ 296 if (!custom_clocks) {
1285 struct clk *p; 297 printk(KERN_ERR "No custom clock functions registered\n");
1286 __u32 regval32; 298 BUG();
1287
1288 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
1289 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
1290 omap_writew(regval32, SOFT_REQ_REG);
1291 omap_writew(0, SOFT_REQ_REG2);
1292
1293 list_for_each_entry(p, &clocks, node) {
1294 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1295 p->enable_reg == 0)
1296 continue;
1297
1298 /* Assume no DSP clocks have been activated by bootloader */
1299 if (p->flags & DSP_DOMAIN_CLOCK)
1300 continue;
1301
1302 /* Is the clock already disabled? */
1303 if (p->flags & ENABLE_REG_32BIT) {
1304 if (p->flags & VIRTUAL_IO_ADDRESS)
1305 regval32 = __raw_readl(p->enable_reg);
1306 else
1307 regval32 = omap_readl(p->enable_reg);
1308 } else {
1309 if (p->flags & VIRTUAL_IO_ADDRESS)
1310 regval32 = __raw_readw(p->enable_reg);
1311 else
1312 regval32 = omap_readw(p->enable_reg);
1313 }
1314
1315 if ((regval32 & (1 << p->enable_bit)) == 0)
1316 continue;
1317
1318 /* FIXME: This clock seems to be necessary but no-one
1319 * has asked for its activation. */
1320 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
1321 || p == &ck_dpll1out // FIX: SoSSI, SSR
1322 || p == &arm_gpio_ck // FIX: GPIO code for 1510
1323 ) {
1324 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1325 p->name);
1326 continue;
1327 }
1328
1329 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1330 __clk_disable(p);
1331 printk(" done\n");
1332 } 299 }
1333 300
301 arch_clock = custom_clocks;
302
1334 return 0; 303 return 0;
1335} 304}
1336
1337late_initcall(omap_late_clk_reset);
1338
1339#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:28:50 -0500