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-rw-r--r--arch/arm/plat-mxc/Kconfig15
-rw-r--r--arch/arm/plat-mxc/Makefile5
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c4
-rw-r--r--arch/arm/plat-mxc/avic.c (renamed from arch/arm/plat-mxc/irq.c)32
-rw-r--r--arch/arm/plat-mxc/cpufreq.c1
-rw-r--r--arch/arm/plat-mxc/devices.c23
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig54
-rw-r--r--arch/arm/plat-mxc/devices/Makefile16
-rw-r--r--arch/arm/plat-mxc/devices/platform-esdhc.c71
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c8
-rw-r--r--arch/arm/plat-mxc/devices/platform-flexcan.c48
-rw-r--r--arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c56
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c127
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-fb.c52
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c16
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-keypad.c62
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-ssi.c17
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c38
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx2-wdt.c68
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx21-hcd.c41
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx_udc.c75
-rw-r--r--arch/arm/plat-mxc/devices/platform-imxdi_rtc.c41
-rw-r--r--arch/arm/plat-mxc/devices/platform-mx1-camera.c42
-rw-r--r--arch/arm/plat-mxc/devices/platform-mx2-camera.c64
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc-ehci.c69
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc-mmc.c72
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_nand.c10
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_pwm.c60
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_rnga.c56
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_w1.c50
-rw-r--r--arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c74
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c16
-rw-r--r--arch/arm/plat-mxc/ehci.c77
-rw-r--r--arch/arm/plat-mxc/gpio.c114
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S23
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h174
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S14
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h94
-rw-r--r--arch/arm/plat-mxc/include/mach/imxfb.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx50.h977
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h1898
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h323
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h64
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h155
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h105
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h149
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h87
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h51
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h198
-rw-r--r--arch/arm/plat-mxc/include/mach/mx50.h285
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h73
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h353
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h42
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/sdma.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h8
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c31
-rw-r--r--arch/arm/plat-mxc/irq-common.c60
-rw-r--r--arch/arm/plat-mxc/irq-common.h29
-rw-r--r--arch/arm/plat-mxc/system.c10
-rw-r--r--arch/arm/plat-mxc/tzic.c46
68 files changed, 5552 insertions, 1470 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 64e3a64520e0..389f21795015 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -21,10 +21,6 @@ config ARCH_MX2
21 21
22config ARCH_MX25 22config ARCH_MX25
23 bool "MX25-based" 23 bool "MX25-based"
24 select CPU_ARM926T
25 select ARCH_MXC_IOMUX_V3
26 select HAVE_FB_IMX
27 select ARCH_MXC_AUDMUX_V2
28 help 24 help
29 This enables support for systems based on the Freescale i.MX25 family 25 This enables support for systems based on the Freescale i.MX25 family
30 26
@@ -51,7 +47,6 @@ endchoice
51 47
52source "arch/arm/mach-imx/Kconfig" 48source "arch/arm/mach-imx/Kconfig"
53source "arch/arm/mach-mx3/Kconfig" 49source "arch/arm/mach-mx3/Kconfig"
54source "arch/arm/mach-mx25/Kconfig"
55source "arch/arm/mach-mxc91231/Kconfig" 50source "arch/arm/mach-mxc91231/Kconfig"
56source "arch/arm/mach-mx5/Kconfig" 51source "arch/arm/mach-mx5/Kconfig"
57 52
@@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR
68 Say N here, unless you have a specialized requirement. 63 Say N here, unless you have a specialized requirement.
69 64
70config MXC_TZIC 65config MXC_TZIC
71 bool "Enable TrustZone Interrupt Controller" 66 bool
72 depends on ARCH_MX51 67
73 help 68config MXC_AVIC
74 This will be automatically selected for all processors 69 bool
75 containing this interrupt controller.
76 Say N here only if you are really sure.
77 70
78config MXC_PWM 71config MXC_PWM
79 tristate "Enable PWM driver" 72 tristate "Enable PWM driver"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 372670952789..5fd20e96876c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,10 +3,11 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o 6obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o
7 7
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10obj-$(CONFIG_MXC_AVIC) += avic.o
10 11
11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 12obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0be1ac7f421b..175e3647bb27 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void)
209 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); 209 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
210 } 210 }
211#endif 211#endif
212#if defined(CONFIG_ARCH_MX25) 212#if defined(CONFIG_SOC_IMX25)
213 if (cpu_is_mx25()) { 213 if (cpu_is_mx25()) {
214 audmux_clk = clk_get(NULL, "audmux"); 214 audmux_clk = clk_get(NULL, "audmux");
215 if (IS_ERR(audmux_clk)) { 215 if (IS_ERR(audmux_clk)) {
@@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void)
220 } 220 }
221 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); 221 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
222 } 222 }
223#endif 223#endif /* if defined(CONFIG_SOC_IMX25) */
224 audmux_debugfs_init(); 224 audmux_debugfs_init();
225 225
226 return 0; 226 return 0;
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c
index 7331f2ace5fe..9a4e8a22dd0a 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -24,6 +24,8 @@
24#include <asm/mach/irq.h> 24#include <asm/mach/irq.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include "irq-common.h"
28
27#define AVIC_INTCNTL 0x00 /* int control reg */ 29#define AVIC_INTCNTL 0x00 /* int control reg */
28#define AVIC_NIMASK 0x04 /* int mask reg */ 30#define AVIC_NIMASK 0x04 /* int mask reg */
29#define AVIC_INTENNUM 0x08 /* int enable number reg */ 31#define AVIC_INTENNUM 0x08 /* int enable number reg */
@@ -46,9 +48,9 @@
46 48
47void __iomem *avic_base; 49void __iomem *avic_base;
48 50
49int imx_irq_set_priority(unsigned char irq, unsigned char prio)
50{
51#ifdef CONFIG_MXC_IRQ_PRIOR 51#ifdef CONFIG_MXC_IRQ_PRIOR
52static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
53{
52 unsigned int temp; 54 unsigned int temp;
53 unsigned int mask = 0x0F << irq % 8 * 4; 55 unsigned int mask = 0x0F << irq % 8 * 4;
54 56
@@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
62 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); 64 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
63 65
64 return 0; 66 return 0;
65#else
66 return -ENOSYS;
67#endif
68} 67}
69EXPORT_SYMBOL(imx_irq_set_priority); 68#endif
70 69
71#ifdef CONFIG_FIQ 70#ifdef CONFIG_FIQ
72int mxc_set_irq_fiq(unsigned int irq, unsigned int type) 71static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
73{ 72{
74 unsigned int irqt; 73 unsigned int irqt;
75 74
@@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
87 86
88 return 0; 87 return 0;
89} 88}
90EXPORT_SYMBOL(mxc_set_irq_fiq);
91#endif /* CONFIG_FIQ */ 89#endif /* CONFIG_FIQ */
92 90
93/* Disable interrupt number "irq" in the AVIC */ 91/* Disable interrupt number "irq" in the AVIC */
@@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq)
102 __raw_writel(irq, avic_base + AVIC_INTENNUM); 100 __raw_writel(irq, avic_base + AVIC_INTENNUM);
103} 101}
104 102
105static struct irq_chip mxc_avic_chip = { 103static struct mxc_irq_chip mxc_avic_chip = {
106 .ack = mxc_mask_irq, 104 .base = {
107 .mask = mxc_mask_irq, 105 .ack = mxc_mask_irq,
108 .unmask = mxc_unmask_irq, 106 .mask = mxc_mask_irq,
107 .unmask = mxc_unmask_irq,
108 },
109#ifdef CONFIG_MXC_IRQ_PRIOR
110 .set_priority = avic_irq_set_priority,
111#endif
112#ifdef CONFIG_FIQ
113 .set_irq_fiq = avic_set_irq_fiq,
114#endif
109}; 115};
110 116
111/* 117/*
@@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
133 __raw_writel(0, avic_base + AVIC_INTTYPEH); 139 __raw_writel(0, avic_base + AVIC_INTTYPEH);
134 __raw_writel(0, avic_base + AVIC_INTTYPEL); 140 __raw_writel(0, avic_base + AVIC_INTTYPEL);
135 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
136 set_irq_chip(i, &mxc_avic_chip); 142 set_irq_chip(i, &mxc_avic_chip.base);
137 set_irq_handler(i, handle_level_irq); 143 set_irq_handler(i, handle_level_irq);
138 set_irq_flags(i, IRQF_VALID); 144 set_irq_flags(i, IRQF_VALID);
139 } 145 }
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 039538e68793..ce81481becf1 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
144 imx_freq_table[i].frequency = CPUFREQ_TABLE_END; 144 imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
145 145
146 policy->cur = clk_get_rate(cpu_clk) / 1000; 146 policy->cur = clk_get_rate(cpu_clk) / 1000;
147 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
148 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; 147 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
149 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; 148 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
150 149
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 735776d84956..e9bcefe79a43 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -17,6 +17,7 @@
17 */ 17 */
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/slab.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/err.h> 22#include <linux/err.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
@@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
36 return ret; 37 return ret;
37} 38}
38 39
39struct platform_device *__init imx_add_platform_device(const char *name, int id, 40struct platform_device *__init imx_add_platform_device_dmamask(
41 const char *name, int id,
40 const struct resource *res, unsigned int num_resources, 42 const struct resource *res, unsigned int num_resources,
41 const void *data, size_t size_data) 43 const void *data, size_t size_data, u64 dmamask)
42{ 44{
43 int ret = -ENOMEM; 45 int ret = -ENOMEM;
44 struct platform_device *pdev; 46 struct platform_device *pdev;
@@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id,
47 if (!pdev) 49 if (!pdev)
48 goto err; 50 goto err;
49 51
52 if (dmamask) {
53 /*
54 * This memory isn't freed when the device is put,
55 * I don't have a nice idea for that though. Conceptually
56 * dma_mask in struct device should not be a pointer.
57 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
58 */
59 pdev->dev.dma_mask =
60 kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
61 if (!pdev->dev.dma_mask)
62 /* ret is still -ENOMEM; */
63 goto err;
64
65 *pdev->dev.dma_mask = dmamask;
66 pdev->dev.coherent_dma_mask = dmamask;
67 }
68
50 if (res) { 69 if (res) {
51 ret = platform_device_add_resources(pdev, res, num_resources); 70 ret = platform_device_add_resources(pdev, res, num_resources);
52 if (ret) 71 if (ret)
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9aa6f3ea9012..2537166468ac 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,29 +1,73 @@
1config IMX_HAVE_PLATFORM_ESDHC
2 bool
3
4config IMX_HAVE_PLATFORM_FEC 1config IMX_HAVE_PLATFORM_FEC
5 bool 2 bool
6 default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 3 default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51
7 4
8config IMX_HAVE_PLATFORM_FLEXCAN 5config IMX_HAVE_PLATFORM_FLEXCAN
9 select HAVE_CAN_FLEXCAN if CAN 6 select HAVE_CAN_FLEXCAN if CAN
10 bool 7 bool
11 8
9config IMX_HAVE_PLATFORM_FSL_USB2_UDC
10 bool
11
12config IMX_HAVE_PLATFORM_GPIO_KEYS 12config IMX_HAVE_PLATFORM_GPIO_KEYS
13 bool 13 bool
14 default y if ARCH_MX51 14 default y if SOC_IMX51
15
16config IMX_HAVE_PLATFORM_IMX21_HCD
17 bool
15 18
19config IMX_HAVE_PLATFORM_IMX2_WDT
20 bool
21
22config IMX_HAVE_PLATFORM_IMXDI_RTC
23 bool
24
25config IMX_HAVE_PLATFORM_IMX_FB
26 bool
27 select HAVE_FB_IMX
28
16config IMX_HAVE_PLATFORM_IMX_I2C 29config IMX_HAVE_PLATFORM_IMX_I2C
17 bool 30 bool
18 31
32config IMX_HAVE_PLATFORM_IMX_KEYPAD
33 bool
34
19config IMX_HAVE_PLATFORM_IMX_SSI 35config IMX_HAVE_PLATFORM_IMX_SSI
20 bool 36 bool
21 37
22config IMX_HAVE_PLATFORM_IMX_UART 38config IMX_HAVE_PLATFORM_IMX_UART
23 bool 39 bool
24 40
41config IMX_HAVE_PLATFORM_IMX_UDC
42 bool
43
44config IMX_HAVE_PLATFORM_MX1_CAMERA
45 bool
46
47config IMX_HAVE_PLATFORM_MX2_CAMERA
48 bool
49
50config IMX_HAVE_PLATFORM_MXC_EHCI
51 bool
52
53config IMX_HAVE_PLATFORM_MXC_MMC
54 bool
55
25config IMX_HAVE_PLATFORM_MXC_NAND 56config IMX_HAVE_PLATFORM_MXC_NAND
26 bool 57 bool
27 58
59config IMX_HAVE_PLATFORM_MXC_PWM
60 bool
61
62config IMX_HAVE_PLATFORM_MXC_RNGA
63 bool
64 select ARCH_HAS_RNGA
65
66config IMX_HAVE_PLATFORM_MXC_W1
67 bool
68
69config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
70 bool
71
28config IMX_HAVE_PLATFORM_SPI_IMX 72config IMX_HAVE_PLATFORM_SPI_IMX
29 bool 73 bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 45aefeb283ba..75cd2ece9053 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,10 +1,24 @@
1obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
2obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o 1obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o 2obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o 4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
5obj-y += platform-imx-dma.o 8obj-y += platform-imx-dma.o
9obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o 10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
11obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o 12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
8obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o 13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
15obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
16obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
17obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
18obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
9obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o 19obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
23obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
10obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 24obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
deleted file mode 100644
index 2605bfa0dfb0..000000000000
--- a/arch/arm/plat-mxc/devices/platform-esdhc.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11#include <mach/esdhc.h>
12
13#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_ARCH_MX25
24const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
25#define imx25_esdhc_data_entry(_id, _hwid) \
26 imx_esdhc_imx_data_entry(MX25, _id, _hwid)
27 imx25_esdhc_data_entry(0, 1),
28 imx25_esdhc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_ARCH_MX25 */
31
32#ifdef CONFIG_ARCH_MX35
33const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
34#define imx35_esdhc_data_entry(_id, _hwid) \
35 imx_esdhc_imx_data_entry(MX35, _id, _hwid)
36 imx35_esdhc_data_entry(0, 1),
37 imx35_esdhc_data_entry(1, 2),
38 imx35_esdhc_data_entry(2, 3),
39};
40#endif /* ifdef CONFIG_ARCH_MX35 */
41
42#ifdef CONFIG_ARCH_MX51
43const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
44#define imx51_esdhc_data_entry(_id, _hwid) \
45 imx_esdhc_imx_data_entry(MX51, _id, _hwid)
46 imx51_esdhc_data_entry(0, 1),
47 imx51_esdhc_data_entry(1, 2),
48 imx51_esdhc_data_entry(2, 3),
49 imx51_esdhc_data_entry(3, 4),
50};
51#endif /* ifdef CONFIG_ARCH_MX51 */
52
53struct platform_device *__init imx_add_esdhc(
54 const struct imx_esdhc_imx_data *data,
55 const struct esdhc_platform_data *pdata)
56{
57 struct resource res[] = {
58 {
59 .start = data->iobase,
60 .end = data->iobase + SZ_16K - 1,
61 .flags = IORESOURCE_MEM,
62 }, {
63 .start = data->irq,
64 .end = data->irq,
65 .flags = IORESOURCE_IRQ,
66 },
67 };
68
69 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
70 ARRAY_SIZE(res), pdata, sizeof(*pdata));
71}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 11d087f4e219..269ec78aba77 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -16,22 +16,22 @@
16 .irq = soc ## _INT_FEC, \ 16 .irq = soc ## _INT_FEC, \
17 } 17 }
18 18
19#ifdef CONFIG_ARCH_MX25 19#ifdef CONFIG_SOC_IMX25
20const struct imx_fec_data imx25_fec_data __initconst = 20const struct imx_fec_data imx25_fec_data __initconst =
21 imx_fec_data_entry_single(MX25); 21 imx_fec_data_entry_single(MX25);
22#endif /* ifdef CONFIG_ARCH_MX25 */ 22#endif /* ifdef CONFIG_SOC_IMX25 */
23 23
24#ifdef CONFIG_SOC_IMX27 24#ifdef CONFIG_SOC_IMX27
25const struct imx_fec_data imx27_fec_data __initconst = 25const struct imx_fec_data imx27_fec_data __initconst =
26 imx_fec_data_entry_single(MX27); 26 imx_fec_data_entry_single(MX27);
27#endif /* ifdef CONFIG_SOC_IMX27 */ 27#endif /* ifdef CONFIG_SOC_IMX27 */
28 28
29#ifdef CONFIG_ARCH_MX35 29#ifdef CONFIG_SOC_IMX35
30const struct imx_fec_data imx35_fec_data __initconst = 30const struct imx_fec_data imx35_fec_data __initconst =
31 imx_fec_data_entry_single(MX35); 31 imx_fec_data_entry_single(MX35);
32#endif 32#endif
33 33
34#ifdef CONFIG_ARCH_MX51 34#ifdef CONFIG_SOC_IMX51
35const struct imx_fec_data imx51_fec_data __initconst = 35const struct imx_fec_data imx51_fec_data __initconst =
36 imx_fec_data_entry_single(MX51); 36 imx_fec_data_entry_single(MX51);
37#endif 37#endif
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
index 5e97a01f14f3..4e8497af2eb1 100644
--- a/arch/arm/plat-mxc/devices/platform-flexcan.c
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -5,26 +5,54 @@
5 * the terms of the GNU General Public License version 2 as published by the 5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation. 6 * Free Software Foundation.
7 */ 7 */
8 8#include <mach/hardware.h>
9#include <mach/devices-common.h> 9#include <mach/devices-common.h>
10 10
11struct platform_device *__init imx_add_flexcan(int id, 11#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \
12 resource_size_t iobase, resource_size_t iosize, 12 { \
13 resource_size_t irq, 13 .id = _id, \
14 .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_CAN ## _hwid, \
17 }
18
19#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX25
23const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
24#define imx25_flexcan_data_entry(_id, _hwid) \
25 imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
26 imx25_flexcan_data_entry(0, 1),
27 imx25_flexcan_data_entry(1, 2),
28};
29#endif /* ifdef CONFIG_SOC_IMX25 */
30
31#ifdef CONFIG_SOC_IMX35
32const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
33#define imx35_flexcan_data_entry(_id, _hwid) \
34 imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
35 imx35_flexcan_data_entry(0, 1),
36 imx35_flexcan_data_entry(1, 2),
37};
38#endif /* ifdef CONFIG_SOC_IMX35 */
39
40struct platform_device *__init imx_add_flexcan(
41 const struct imx_flexcan_data *data,
14 const struct flexcan_platform_data *pdata) 42 const struct flexcan_platform_data *pdata)
15{ 43{
16 struct resource res[] = { 44 struct resource res[] = {
17 { 45 {
18 .start = iobase, 46 .start = data->iobase,
19 .end = iobase + iosize - 1, 47 .end = data->iobase + data->iosize - 1,
20 .flags = IORESOURCE_MEM, 48 .flags = IORESOURCE_MEM,
21 }, { 49 }, {
22 .start = irq, 50 .start = data->irq,
23 .end = irq, 51 .end = data->irq,
24 .flags = IORESOURCE_IRQ, 52 .flags = IORESOURCE_IRQ,
25 }, 53 },
26 }; 54 };
27 55
28 return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), 56 return imx_add_platform_device("flexcan", data->id,
29 pdata, sizeof(*pdata)); 57 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
30} 58}
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
new file mode 100644
index 000000000000..59c33f6e401c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_fsl_usb2_udc_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _USB_OTG_BASE_ADDR, \
15 .irq = soc ## _INT_USB_OTG, \
16 }
17
18#ifdef CONFIG_SOC_IMX25
19const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
20 imx_fsl_usb2_udc_data_entry_single(MX25);
21#endif /* ifdef CONFIG_SOC_IMX25 */
22
23#ifdef CONFIG_SOC_IMX27
24const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
25 imx_fsl_usb2_udc_data_entry_single(MX27);
26#endif /* ifdef CONFIG_SOC_IMX27 */
27
28#ifdef CONFIG_SOC_IMX31
29const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
30 imx_fsl_usb2_udc_data_entry_single(MX31);
31#endif /* ifdef CONFIG_SOC_IMX31 */
32
33#ifdef CONFIG_SOC_IMX35
34const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
35 imx_fsl_usb2_udc_data_entry_single(MX35);
36#endif /* ifdef CONFIG_SOC_IMX35 */
37
38struct platform_device *__init imx_add_fsl_usb2_udc(
39 const struct imx_fsl_usb2_udc_data *data,
40 const struct fsl_usb2_platform_data *pdata)
41{
42 struct resource res[] = {
43 {
44 .start = data->iobase,
45 .end = data->iobase + SZ_512 - 1,
46 .flags = IORESOURCE_MEM,
47 }, {
48 .start = data->irq,
49 .end = data->irq,
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53 return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
54 res, ARRAY_SIZE(res),
55 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
56}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 3a705c7877dd..33530d2d5ed1 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -31,25 +31,25 @@ struct imx_imx_sdma_data {
31 }, \ 31 }, \
32 } 32 }
33 33
34#ifdef CONFIG_ARCH_MX25 34#ifdef CONFIG_SOC_IMX25
35const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = 35struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
36 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); 36 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
37#endif /* ifdef CONFIG_ARCH_MX25 */ 37#endif /* ifdef CONFIG_SOC_IMX25 */
38 38
39#ifdef CONFIG_ARCH_MX31 39#ifdef CONFIG_SOC_IMX31
40struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = 40struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
41 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); 41 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
42#endif /* ifdef CONFIG_ARCH_MX31 */ 42#endif /* ifdef CONFIG_SOC_IMX31 */
43 43
44#ifdef CONFIG_ARCH_MX35 44#ifdef CONFIG_SOC_IMX35
45struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = 45struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
46 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); 46 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
47#endif /* ifdef CONFIG_ARCH_MX35 */ 47#endif /* ifdef CONFIG_SOC_IMX35 */
48 48
49#ifdef CONFIG_ARCH_MX51 49#ifdef CONFIG_SOC_IMX51
50const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = 50struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
51 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); 51 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
52#endif /* ifdef CONFIG_ARCH_MX51 */ 52#endif /* ifdef CONFIG_SOC_IMX51 */
53 53
54static struct platform_device __init __maybe_unused *imx_add_imx_sdma( 54static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
55 const struct imx_imx_sdma_data *data) 55 const struct imx_imx_sdma_data *data)
@@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
76 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); 76 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
77} 77}
78 78
79#ifdef CONFIG_ARCH_MX25
80static struct sdma_script_start_addrs addr_imx25_to1 = {
81 .ap_2_ap_addr = 729,
82 .uart_2_mcu_addr = 904,
83 .per_2_app_addr = 1255,
84 .mcu_2_app_addr = 834,
85 .uartsh_2_mcu_addr = 1120,
86 .per_2_shp_addr = 1329,
87 .mcu_2_shp_addr = 1048,
88 .ata_2_mcu_addr = 1560,
89 .mcu_2_ata_addr = 1479,
90 .app_2_per_addr = 1189,
91 .app_2_mcu_addr = 770,
92 .shp_2_per_addr = 1407,
93 .shp_2_mcu_addr = 979,
94};
95#endif
96
97#ifdef CONFIG_ARCH_MX31
98static struct sdma_script_start_addrs addr_imx31_to1 = {
99 .per_2_per_addr = 1677,
100};
101
102static struct sdma_script_start_addrs addr_imx31_to2 = {
103 .ap_2_ap_addr = 423,
104 .ap_2_bp_addr = 829,
105 .bp_2_ap_addr = 1029,
106};
107#endif
108
109#ifdef CONFIG_ARCH_MX35
110static struct sdma_script_start_addrs addr_imx35_to1 = {
111 .ap_2_ap_addr = 642,
112 .uart_2_mcu_addr = 817,
113 .mcu_2_app_addr = 747,
114 .uartsh_2_mcu_addr = 1183,
115 .per_2_shp_addr = 1033,
116 .mcu_2_shp_addr = 961,
117 .ata_2_mcu_addr = 1333,
118 .mcu_2_ata_addr = 1252,
119 .app_2_mcu_addr = 683,
120 .shp_2_per_addr = 1111,
121 .shp_2_mcu_addr = 892,
122};
123
124static struct sdma_script_start_addrs addr_imx35_to2 = {
125 .ap_2_ap_addr = 729,
126 .uart_2_mcu_addr = 904,
127 .per_2_app_addr = 1597,
128 .mcu_2_app_addr = 834,
129 .uartsh_2_mcu_addr = 1270,
130 .per_2_shp_addr = 1120,
131 .mcu_2_shp_addr = 1048,
132 .ata_2_mcu_addr = 1429,
133 .mcu_2_ata_addr = 1339,
134 .app_2_per_addr = 1531,
135 .app_2_mcu_addr = 770,
136 .shp_2_per_addr = 1198,
137 .shp_2_mcu_addr = 979,
138};
139#endif
140
141#ifdef CONFIG_SOC_IMX51
142static struct sdma_script_start_addrs addr_imx51_to1 = {
143 .ap_2_ap_addr = 642,
144 .uart_2_mcu_addr = 817,
145 .mcu_2_app_addr = 747,
146 .mcu_2_shp_addr = 961,
147 .ata_2_mcu_addr = 1473,
148 .mcu_2_ata_addr = 1392,
149 .app_2_per_addr = 1033,
150 .app_2_mcu_addr = 683,
151 .shp_2_per_addr = 1251,
152 .shp_2_mcu_addr = 892,
153};
154#endif
155
79static int __init imxXX_add_imx_dma(void) 156static int __init imxXX_add_imx_dma(void)
80{ 157{
81 struct platform_device *ret; 158 struct platform_device *ret;
@@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void)
86 else 163 else
87#endif 164#endif
88 165
89#if defined(CONFIG_ARCH_MX25) 166#if defined(CONFIG_SOC_IMX25)
90 if (cpu_is_mx25()) 167 if (cpu_is_mx25()) {
168 imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1;
91 ret = imx_add_imx_sdma(&imx25_imx_sdma_data); 169 ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
92 else 170 } else
93#endif 171#endif
94 172
95#if defined(CONFIG_ARCH_MX31) 173#if defined(CONFIG_SOC_IMX31)
96 if (cpu_is_mx31()) { 174 if (cpu_is_mx31()) {
97 imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; 175 int to_version = mx31_revision() >> 4;
176 imx31_imx_sdma_data.pdata.to_version = to_version;
177 if (to_version == 1)
178 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
179 else
180 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
98 ret = imx_add_imx_sdma(&imx31_imx_sdma_data); 181 ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
99 } else 182 } else
100#endif 183#endif
101 184
102#if defined(CONFIG_ARCH_MX35) 185#if defined(CONFIG_SOC_IMX35)
103 if (cpu_is_mx35()) { 186 if (cpu_is_mx35()) {
104 imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; 187 int to_version = mx35_revision() >> 4;
188 imx35_imx_sdma_data.pdata.to_version = to_version;
189 if (to_version == 1)
190 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
191 else
192 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
105 ret = imx_add_imx_sdma(&imx35_imx_sdma_data); 193 ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
106 } else 194 } else
107#endif 195#endif
108 196
109#if defined(CONFIG_ARCH_MX51) 197#if defined(CONFIG_ARCH_MX51)
110 if (cpu_is_mx51()) 198 if (cpu_is_mx51()) {
199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
111 ret = imx_add_imx_sdma(&imx51_imx_sdma_data); 200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
112 else 201 } else
113#endif 202#endif
114 ret = ERR_PTR(-ENODEV); 203 ret = ERR_PTR(-ENODEV);
115 204
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
new file mode 100644
index 000000000000..6100a7d824dd
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -0,0 +1,52 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_fb_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _LCDC_BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_LCDC, \
17 }
18
19#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX21, SZ_4K);
22#endif /* ifdef CONFIG_SOC_IMX21 */
23
24#ifdef CONFIG_SOC_IMX25
25const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
26 imx_imx_fb_data_entry_single(MX25, SZ_16K);
27#endif /* ifdef CONFIG_SOC_IMX25 */
28
29#ifdef CONFIG_SOC_IMX27
30const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
31 imx_imx_fb_data_entry_single(MX27, SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX27 */
33
34struct platform_device *__init imx_add_imx_fb(
35 const struct imx_imx_fb_data *data,
36 const struct imx_fb_platform_data *pdata)
37{
38 struct resource res[] = {
39 {
40 .start = data->iobase,
41 .end = data->iobase + data->iosize - 1,
42 .flags = IORESOURCE_MEM,
43 }, {
44 .start = data->irq,
45 .end = data->irq,
46 .flags = IORESOURCE_IRQ,
47 },
48 };
49 return imx_add_platform_device_dmamask("imx-fb", 0,
50 res, ARRAY_SIZE(res),
51 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
52}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 679588453aad..72ba880c75af 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
30 imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); 30 imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
31#endif /* ifdef CONFIG_SOC_IMX21 */ 31#endif /* ifdef CONFIG_SOC_IMX21 */
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { 34const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
35#define imx25_imx_i2c_data_entry(_id, _hwid) \ 35#define imx25_imx_i2c_data_entry(_id, _hwid) \
36 imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) 36 imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
38 imx25_imx_i2c_data_entry(1, 2), 38 imx25_imx_i2c_data_entry(1, 2),
39 imx25_imx_i2c_data_entry(2, 3), 39 imx25_imx_i2c_data_entry(2, 3),
40}; 40};
41#endif /* ifdef CONFIG_ARCH_MX25 */ 41#endif /* ifdef CONFIG_SOC_IMX25 */
42 42
43#ifdef CONFIG_SOC_IMX27 43#ifdef CONFIG_SOC_IMX27
44const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { 44const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
@@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
49}; 49};
50#endif /* ifdef CONFIG_SOC_IMX27 */ 50#endif /* ifdef CONFIG_SOC_IMX27 */
51 51
52#ifdef CONFIG_ARCH_MX31 52#ifdef CONFIG_SOC_IMX31
53const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { 53const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
54#define imx31_imx_i2c_data_entry(_id, _hwid) \ 54#define imx31_imx_i2c_data_entry(_id, _hwid) \
55 imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) 55 imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
57 imx31_imx_i2c_data_entry(1, 2), 57 imx31_imx_i2c_data_entry(1, 2),
58 imx31_imx_i2c_data_entry(2, 3), 58 imx31_imx_i2c_data_entry(2, 3),
59}; 59};
60#endif /* ifdef CONFIG_ARCH_MX31 */ 60#endif /* ifdef CONFIG_SOC_IMX31 */
61 61
62#ifdef CONFIG_ARCH_MX35 62#ifdef CONFIG_SOC_IMX35
63const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { 63const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
64#define imx35_imx_i2c_data_entry(_id, _hwid) \ 64#define imx35_imx_i2c_data_entry(_id, _hwid) \
65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) 65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
@@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
67 imx35_imx_i2c_data_entry(1, 2), 67 imx35_imx_i2c_data_entry(1, 2),
68 imx35_imx_i2c_data_entry(2, 3), 68 imx35_imx_i2c_data_entry(2, 3),
69}; 69};
70#endif /* ifdef CONFIG_ARCH_MX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_ARCH_MX51 72#ifdef CONFIG_SOC_IMX51
73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { 73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
74#define imx51_imx_i2c_data_entry(_id, _hwid) \ 74#define imx51_imx_i2c_data_entry(_id, _hwid) \
75 imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) 75 imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
76 imx51_imx_i2c_data_entry(0, 1), 76 imx51_imx_i2c_data_entry(0, 1),
77 imx51_imx_i2c_data_entry(1, 2), 77 imx51_imx_i2c_data_entry(1, 2),
78}; 78};
79#endif /* ifdef CONFIG_ARCH_MX51 */ 79#endif /* ifdef CONFIG_SOC_IMX51 */
80 80
81struct platform_device *__init imx_add_imx_i2c( 81struct platform_device *__init imx_add_imx_i2c(
82 const struct imx_imx_i2c_data *data, 82 const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
new file mode 100644
index 000000000000..40238f0b8643
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_keypad_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _KPP_BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_KPP, \
17 }
18
19#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
21 imx_imx_keypad_data_entry_single(MX21, SZ_16);
22#endif /* ifdef CONFIG_SOC_IMX21 */
23
24#ifdef CONFIG_SOC_IMX25
25const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
26 imx_imx_keypad_data_entry_single(MX25, SZ_16K);
27#endif /* ifdef CONFIG_SOC_IMX25 */
28
29#ifdef CONFIG_SOC_IMX27
30const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
31 imx_imx_keypad_data_entry_single(MX27, SZ_16);
32#endif /* ifdef CONFIG_SOC_IMX27 */
33
34#ifdef CONFIG_SOC_IMX31
35const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
36 imx_imx_keypad_data_entry_single(MX31, SZ_16);
37#endif /* ifdef CONFIG_SOC_IMX31 */
38
39#ifdef CONFIG_SOC_IMX35
40const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
41 imx_imx_keypad_data_entry_single(MX35, SZ_16);
42#endif /* ifdef CONFIG_SOC_IMX35 */
43
44struct platform_device *__init imx_add_imx_keypad(
45 const struct imx_imx_keypad_data *data,
46 const struct matrix_keymap_data *pdata)
47{
48 struct resource res[] = {
49 {
50 .start = data->iobase,
51 .end = data->iobase + data->iosize - 1,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = data->irq,
55 .end = data->irq,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 return imx_add_platform_device("imx-keypad", -1,
61 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
62}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 38a7a0b8f2f1..2569c8d8a2ef 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
30}; 30};
31#endif /* ifdef CONFIG_SOC_IMX21 */ 31#endif /* ifdef CONFIG_SOC_IMX21 */
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { 34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
35#define imx25_imx_ssi_data_entry(_id, _hwid) \ 35#define imx25_imx_ssi_data_entry(_id, _hwid) \
36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) 36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
37 imx25_imx_ssi_data_entry(0, 1), 37 imx25_imx_ssi_data_entry(0, 1),
38 imx25_imx_ssi_data_entry(1, 2), 38 imx25_imx_ssi_data_entry(1, 2),
39}; 39};
40#endif /* ifdef CONFIG_ARCH_MX25 */ 40#endif /* ifdef CONFIG_SOC_IMX25 */
41 41
42#ifdef CONFIG_SOC_IMX27 42#ifdef CONFIG_SOC_IMX27
43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { 43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
@@ -48,32 +48,33 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
48}; 48};
49#endif /* ifdef CONFIG_SOC_IMX27 */ 49#endif /* ifdef CONFIG_SOC_IMX27 */
50 50
51#ifdef CONFIG_ARCH_MX31 51#ifdef CONFIG_SOC_IMX31
52const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { 52const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
53#define imx31_imx_ssi_data_entry(_id, _hwid) \ 53#define imx31_imx_ssi_data_entry(_id, _hwid) \
54 imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) 54 imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
55 imx31_imx_ssi_data_entry(0, 1), 55 imx31_imx_ssi_data_entry(0, 1),
56 imx31_imx_ssi_data_entry(1, 2), 56 imx31_imx_ssi_data_entry(1, 2),
57}; 57};
58#endif /* ifdef CONFIG_ARCH_MX31 */ 58#endif /* ifdef CONFIG_SOC_IMX31 */
59 59
60#ifdef CONFIG_ARCH_MX35 60#ifdef CONFIG_SOC_IMX35
61const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { 61const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
62#define imx35_imx_ssi_data_entry(_id, _hwid) \ 62#define imx35_imx_ssi_data_entry(_id, _hwid) \
63 imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) 63 imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
64 imx35_imx_ssi_data_entry(0, 1), 64 imx35_imx_ssi_data_entry(0, 1),
65 imx35_imx_ssi_data_entry(1, 2), 65 imx35_imx_ssi_data_entry(1, 2),
66}; 66};
67#endif /* ifdef CONFIG_ARCH_MX35 */ 67#endif /* ifdef CONFIG_SOC_IMX35 */
68 68
69#ifdef CONFIG_ARCH_MX51 69#ifdef CONFIG_SOC_IMX51
70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { 70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
71#define imx51_imx_ssi_data_entry(_id, _hwid) \ 71#define imx51_imx_ssi_data_entry(_id, _hwid) \
72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) 72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
73 imx51_imx_ssi_data_entry(0, 1), 73 imx51_imx_ssi_data_entry(0, 1),
74 imx51_imx_ssi_data_entry(1, 2), 74 imx51_imx_ssi_data_entry(1, 2),
75 imx51_imx_ssi_data_entry(2, 3),
75}; 76};
76#endif /* ifdef CONFIG_ARCH_MX51 */ 77#endif /* ifdef CONFIG_SOC_IMX51 */
77 78
78struct platform_device *__init imx_add_imx_ssi( 79struct platform_device *__init imx_add_imx_ssi(
79 const struct imx_imx_ssi_data *data, 80 const struct imx_imx_ssi_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2039640adf27..3c854c2cc6dd 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
47}; 47};
48#endif 48#endif
49 49
50#ifdef CONFIG_ARCH_MX25 50#ifdef CONFIG_SOC_IMX25
51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { 51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
52#define imx25_imx_uart_data_entry(_id, _hwid) \ 52#define imx25_imx_uart_data_entry(_id, _hwid) \
53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) 53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
57 imx25_imx_uart_data_entry(3, 4), 57 imx25_imx_uart_data_entry(3, 4),
58 imx25_imx_uart_data_entry(4, 5), 58 imx25_imx_uart_data_entry(4, 5),
59}; 59};
60#endif /* ifdef CONFIG_ARCH_MX25 */ 60#endif /* ifdef CONFIG_SOC_IMX25 */
61 61
62#ifdef CONFIG_SOC_IMX27 62#ifdef CONFIG_SOC_IMX27
63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { 63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
@@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
72}; 72};
73#endif /* ifdef CONFIG_SOC_IMX27 */ 73#endif /* ifdef CONFIG_SOC_IMX27 */
74 74
75#ifdef CONFIG_ARCH_MX31 75#ifdef CONFIG_SOC_IMX31
76const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { 76const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
77#define imx31_imx_uart_data_entry(_id, _hwid) \ 77#define imx31_imx_uart_data_entry(_id, _hwid) \
78 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) 78 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
82 imx31_imx_uart_data_entry(3, 4), 82 imx31_imx_uart_data_entry(3, 4),
83 imx31_imx_uart_data_entry(4, 5), 83 imx31_imx_uart_data_entry(4, 5),
84}; 84};
85#endif /* ifdef CONFIG_ARCH_MX31 */ 85#endif /* ifdef CONFIG_SOC_IMX31 */
86 86
87#ifdef CONFIG_ARCH_MX35 87#ifdef CONFIG_SOC_IMX35
88const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { 88const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
89#define imx35_imx_uart_data_entry(_id, _hwid) \ 89#define imx35_imx_uart_data_entry(_id, _hwid) \
90 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) 90 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
@@ -92,9 +92,21 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
92 imx35_imx_uart_data_entry(1, 2), 92 imx35_imx_uart_data_entry(1, 2),
93 imx35_imx_uart_data_entry(2, 3), 93 imx35_imx_uart_data_entry(2, 3),
94}; 94};
95#endif /* ifdef CONFIG_ARCH_MX35 */ 95#endif /* ifdef CONFIG_SOC_IMX35 */
96 96
97#ifdef CONFIG_ARCH_MX51 97#ifdef CONFIG_SOC_IMX50
98const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
99#define imx50_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
101 imx50_imx_uart_data_entry(0, 1),
102 imx50_imx_uart_data_entry(1, 2),
103 imx50_imx_uart_data_entry(2, 3),
104 imx50_imx_uart_data_entry(3, 4),
105 imx50_imx_uart_data_entry(4, 5),
106};
107#endif /* ifdef CONFIG_SOC_IMX50 */
108
109#ifdef CONFIG_SOC_IMX51
98const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { 110const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
99#define imx51_imx_uart_data_entry(_id, _hwid) \ 111#define imx51_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) 112 imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
@@ -102,7 +114,17 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
102 imx51_imx_uart_data_entry(1, 2), 114 imx51_imx_uart_data_entry(1, 2),
103 imx51_imx_uart_data_entry(2, 3), 115 imx51_imx_uart_data_entry(2, 3),
104}; 116};
105#endif /* ifdef CONFIG_ARCH_MX51 */ 117#endif /* ifdef CONFIG_SOC_IMX51 */
118
119#ifdef CONFIG_SOC_IMX53
120const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
121#define imx53_imx_uart_data_entry(_id, _hwid) \
122 imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
123 imx53_imx_uart_data_entry(0, 1),
124 imx53_imx_uart_data_entry(1, 2),
125 imx53_imx_uart_data_entry(2, 3),
126};
127#endif /* ifdef CONFIG_SOC_IMX53 */
106 128
107struct platform_device *__init imx_add_imx_uart_3irq( 129struct platform_device *__init imx_add_imx_uart_3irq(
108 const struct imx_imx_uart_3irq_data *data, 130 const struct imx_imx_uart_3irq_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
new file mode 100644
index 000000000000..e0aec61177f4
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -0,0 +1,68 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/hardware.h>
11#include <mach/devices-common.h>
12
13#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 }
19#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX21
23const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
24 imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX21 */
26
27#ifdef CONFIG_SOC_IMX25
28const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
29 imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
30#endif /* ifdef CONFIG_SOC_IMX25 */
31
32#ifdef CONFIG_SOC_IMX27
33const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
34 imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
35#endif /* ifdef CONFIG_SOC_IMX27 */
36
37#ifdef CONFIG_SOC_IMX31
38const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
39 imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K);
40#endif /* ifdef CONFIG_SOC_IMX31 */
41
42#ifdef CONFIG_SOC_IMX35
43const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
44 imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
45#endif /* ifdef CONFIG_SOC_IMX35 */
46
47#ifdef CONFIG_SOC_IMX51
48const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
49#define imx51_imx2_wdt_data_entry(_id, _hwid) \
50 imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
51 imx51_imx2_wdt_data_entry(0, 1),
52 imx51_imx2_wdt_data_entry(1, 2),
53};
54#endif /* ifdef CONFIG_SOC_IMX51 */
55
56struct platform_device *__init imx_add_imx2_wdt(
57 const struct imx_imx2_wdt_data *data)
58{
59 struct resource res[] = {
60 {
61 .start = data->iobase,
62 .end = data->iobase + data->iosize - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 };
66 return imx_add_platform_device("imx2-wdt", data->id,
67 res, ARRAY_SIZE(res), NULL, 0);
68}
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
new file mode 100644
index 000000000000..5770a42f33bf
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx21_hcd_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _USBOTG_BASE_ADDR, \
15 .irq = soc ## _INT_USBHOST, \
16 }
17
18#ifdef CONFIG_SOC_IMX21
19const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
20 imx_imx21_hcd_data_entry_single(MX21);
21#endif /* ifdef CONFIG_SOC_IMX21 */
22
23struct platform_device *__init imx_add_imx21_hcd(
24 const struct imx_imx21_hcd_data *data,
25 const struct mx21_usbh_platform_data *pdata)
26{
27 struct resource res[] = {
28 {
29 .start = data->iobase,
30 .end = data->iobase + SZ_8K - 1,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = data->irq,
34 .end = data->irq,
35 .flags = IORESOURCE_IRQ,
36 },
37 };
38 return imx_add_platform_device_dmamask("imx21-hcd", 0,
39 res, ARRAY_SIZE(res),
40 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
41}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c
new file mode 100644
index 000000000000..6fd675dfce14
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_udc_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _USBD_BASE_ADDR, \
15 .iosize = _size, \
16 .irq0 = soc ## _INT_USBD0, \
17 .irq1 = soc ## _INT_USBD1, \
18 .irq2 = soc ## _INT_USBD2, \
19 .irq3 = soc ## _INT_USBD3, \
20 .irq4 = soc ## _INT_USBD4, \
21 .irq5 = soc ## _INT_USBD5, \
22 .irq6 = soc ## _INT_USBD6, \
23 }
24
25#define imx_imx_udc_data_entry(soc, _size) \
26 [_id] = imx_imx_udc_data_entry_single(soc, _size)
27
28#ifdef CONFIG_SOC_IMX1
29const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
30 imx_imx_udc_data_entry_single(MX1, SZ_4K);
31#endif /* ifdef CONFIG_SOC_IMX1 */
32
33struct platform_device *__init imx_add_imx_udc(
34 const struct imx_imx_udc_data *data,
35 const struct imxusb_platform_data *pdata)
36{
37 struct resource res[] = {
38 {
39 .start = data->iobase,
40 .end = data->iobase + data->iosize - 1,
41 .flags = IORESOURCE_MEM,
42 }, {
43 .start = data->irq0,
44 .end = data->irq0,
45 .flags = IORESOURCE_IRQ,
46 }, {
47 .start = data->irq1,
48 .end = data->irq1,
49 .flags = IORESOURCE_IRQ,
50 }, {
51 .start = data->irq2,
52 .end = data->irq2,
53 .flags = IORESOURCE_IRQ,
54 }, {
55 .start = data->irq3,
56 .end = data->irq3,
57 .flags = IORESOURCE_IRQ,
58 }, {
59 .start = data->irq4,
60 .end = data->irq4,
61 .flags = IORESOURCE_IRQ,
62 }, {
63 .start = data->irq5,
64 .end = data->irq5,
65 .flags = IORESOURCE_IRQ,
66 }, {
67 .start = data->irq6,
68 .end = data->irq6,
69 .flags = IORESOURCE_IRQ,
70 },
71 };
72
73 return imx_add_platform_device("imx_udc", 0,
74 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
75}
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
new file mode 100644
index 000000000000..10653cc8d1fa
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/hardware.h>
11#include <mach/devices-common.h>
12
13#define imx_imxdi_rtc_data_entry_single(soc) \
14 { \
15 .iobase = soc ## _DRYICE_BASE_ADDR, \
16 .irq = soc ## _INT_DRYICE, \
17 }
18
19#ifdef CONFIG_SOC_IMX25
20const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
21 imx_imxdi_rtc_data_entry_single(MX25);
22#endif /* ifdef CONFIG_SOC_IMX25 */
23
24struct platform_device *__init imx_add_imxdi_rtc(
25 const struct imx_imxdi_rtc_data *data)
26{
27 struct resource res[] = {
28 {
29 .start = data->iobase,
30 .end = data->iobase + SZ_16K,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = data->irq,
34 .end = data->irq,
35 .flags = IORESOURCE_IRQ,
36 },
37 };
38
39 return imx_add_platform_device("imxdi_rtc", 0,
40 res, ARRAY_SIZE(res), NULL, 0);
41}
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
new file mode 100644
index 000000000000..edcc581a30a9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mx1_camera_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _CSI ## _BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_CSI, \
17 }
18
19#ifdef CONFIG_SOC_IMX1
20const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
21 imx_mx1_camera_data_entry_single(MX1, 10);
22#endif /* ifdef CONFIG_SOC_IMX1 */
23
24struct platform_device *__init imx_add_mx1_camera(
25 const struct imx_mx1_camera_data *data,
26 const struct mx1_camera_pdata *pdata)
27{
28 struct resource res[] = {
29 {
30 .start = data->iobase,
31 .end = data->iobase + data->iosize - 1,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = data->irq,
35 .end = data->irq,
36 .flags = IORESOURCE_IRQ,
37 },
38 };
39 return imx_add_platform_device_dmamask("mx1-camera", 0,
40 res, ARRAY_SIZE(res),
41 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
42}
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
new file mode 100644
index 000000000000..b3f4828dc447
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mx2_camera_data_entry_single(soc) \
13 { \
14 .iobasecsi = soc ## _CSI_BASE_ADDR, \
15 .iosizecsi = SZ_4K, \
16 .irqcsi = soc ## _INT_CSI, \
17 }
18#define imx_mx2_camera_data_entry_single_emma(soc) \
19 { \
20 .iobasecsi = soc ## _CSI_BASE_ADDR, \
21 .iosizecsi = SZ_32, \
22 .irqcsi = soc ## _INT_CSI, \
23 .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \
24 .iosizeemmaprp = SZ_32, \
25 .irqemmaprp = soc ## _INT_EMMAPRP, \
26 }
27
28#ifdef CONFIG_SOC_IMX25
29const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
30 imx_mx2_camera_data_entry_single(MX25);
31#endif /* ifdef CONFIG_SOC_IMX25 */
32
33#ifdef CONFIG_SOC_IMX27
34const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
35 imx_mx2_camera_data_entry_single_emma(MX27);
36#endif /* ifdef CONFIG_SOC_IMX27 */
37
38struct platform_device *__init imx_add_mx2_camera(
39 const struct imx_mx2_camera_data *data,
40 const struct mx2_camera_platform_data *pdata)
41{
42 struct resource res[] = {
43 {
44 .start = data->iobasecsi,
45 .end = data->iobasecsi + data->iosizecsi - 1,
46 .flags = IORESOURCE_MEM,
47 }, {
48 .start = data->irqcsi,
49 .end = data->irqcsi,
50 .flags = IORESOURCE_IRQ,
51 }, {
52 .start = data->iobaseemmaprp,
53 .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = data->irqemmaprp,
57 .end = data->irqemmaprp,
58 .flags = IORESOURCE_IRQ,
59 },
60 };
61 return imx_add_platform_device_dmamask("mx2-camera", 0,
62 res, data->iobaseemmaprp ? 4 : 2,
63 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
64}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
new file mode 100644
index 000000000000..cc488f4b6204
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \
16 .irq = soc ## _INT_USB_ ## hs, \
17 }
18
19#ifdef CONFIG_SOC_IMX25
20const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
21 imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
22const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
23 imx_mxc_ehci_data_entry_single(MX25, 1, HS);
24#endif /* ifdef CONFIG_SOC_IMX25 */
25
26#ifdef CONFIG_SOC_IMX27
27const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
28 imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
29const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
30 imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
31 imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
32};
33#endif /* ifdef CONFIG_SOC_IMX27 */
34
35#ifdef CONFIG_SOC_IMX31
36const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
37 imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
38const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
39 imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
40 imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
41};
42#endif /* ifdef CONFIG_SOC_IMX31 */
43
44#ifdef CONFIG_SOC_IMX35
45const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
46 imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
47const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
48 imx_mxc_ehci_data_entry_single(MX35, 1, HS);
49#endif /* ifdef CONFIG_SOC_IMX35 */
50
51struct platform_device *__init imx_add_mxc_ehci(
52 const struct imx_mxc_ehci_data *data,
53 const struct mxc_usbh_platform_data *pdata)
54{
55 struct resource res[] = {
56 {
57 .start = data->iobase,
58 .end = data->iobase + SZ_512 - 1,
59 .flags = IORESOURCE_MEM,
60 }, {
61 .start = data->irq,
62 .end = data->irq,
63 .flags = IORESOURCE_IRQ,
64 },
65 };
66 return imx_add_platform_device_dmamask("mxc-ehci", data->id,
67 res, ARRAY_SIZE(res),
68 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
69}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
new file mode 100644
index 000000000000..90d762f6f93b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_SDHC ## _hwid, \
18 .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \
19 }
20#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \
21 [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)
22
23#ifdef CONFIG_SOC_IMX21
24const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
25#define imx21_mxc_mmc_data_entry(_id, _hwid) \
26 imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K)
27 imx21_mxc_mmc_data_entry(0, 1),
28 imx21_mxc_mmc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_SOC_IMX21 */
31
32#ifdef CONFIG_SOC_IMX27
33const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
34#define imx27_mxc_mmc_data_entry(_id, _hwid) \
35 imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K)
36 imx27_mxc_mmc_data_entry(0, 1),
37 imx27_mxc_mmc_data_entry(1, 2),
38};
39#endif /* ifdef CONFIG_SOC_IMX27 */
40
41#ifdef CONFIG_SOC_IMX31
42const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
43#define imx31_mxc_mmc_data_entry(_id, _hwid) \
44 imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K)
45 imx31_mxc_mmc_data_entry(0, 1),
46 imx31_mxc_mmc_data_entry(1, 2),
47};
48#endif /* ifdef CONFIG_SOC_IMX31 */
49
50struct platform_device *__init imx_add_mxc_mmc(
51 const struct imx_mxc_mmc_data *data,
52 const struct imxmmc_platform_data *pdata)
53{
54 struct resource res[] = {
55 {
56 .start = data->iobase,
57 .end = data->iobase + SZ_4K - 1,
58 .flags = IORESOURCE_MEM,
59 }, {
60 .start = data->irq,
61 .end = data->irq,
62 .flags = IORESOURCE_IRQ,
63 }, {
64 .start = data->dmareq,
65 .end = data->dmareq,
66 .flags = IORESOURCE_DMA,
67 },
68 };
69 return imx_add_platform_device_dmamask("mxc-mmc", data->id,
70 res, ARRAY_SIZE(res),
71 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
72}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 3fdcc32e3d67..1568f39fba8b 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
31 imx_mxc_nand_data_entry_single(MX21, SZ_4K); 31 imx_mxc_nand_data_entry_single(MX21, SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX21 */ 32#endif /* ifdef CONFIG_SOC_IMX21 */
33 33
34#ifdef CONFIG_ARCH_MX25 34#ifdef CONFIG_SOC_IMX25
35const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = 35const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
36 imx_mxc_nand_data_entry_single(MX25, SZ_8K); 36 imx_mxc_nand_data_entry_single(MX25, SZ_8K);
37#endif /* ifdef CONFIG_ARCH_MX25 */ 37#endif /* ifdef CONFIG_SOC_IMX25 */
38 38
39#ifdef CONFIG_SOC_IMX27 39#ifdef CONFIG_SOC_IMX27
40const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = 40const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
41 imx_mxc_nand_data_entry_single(MX27, SZ_4K); 41 imx_mxc_nand_data_entry_single(MX27, SZ_4K);
42#endif /* ifdef CONFIG_SOC_IMX27 */ 42#endif /* ifdef CONFIG_SOC_IMX27 */
43 43
44#ifdef CONFIG_ARCH_MX31 44#ifdef CONFIG_SOC_IMX31
45const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = 45const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
46 imx_mxc_nand_data_entry_single(MX31, SZ_4K); 46 imx_mxc_nand_data_entry_single(MX31, SZ_4K);
47#endif 47#endif
48 48
49#ifdef CONFIG_ARCH_MX35 49#ifdef CONFIG_SOC_IMX35
50const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = 50const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
51 imx_mxc_nand_data_entry_single(MX35, SZ_8K); 51 imx_mxc_nand_data_entry_single(MX35, SZ_8K);
52#endif 52#endif
53 53
54#ifdef CONFIG_ARCH_MX51 54#ifdef CONFIG_SOC_IMX51
55const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = 55const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
56 imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); 56 imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
57#endif 57#endif
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
new file mode 100644
index 000000000000..3d8ebdba38ee
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_PWM ## _hwid, \
18 }
19#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX21
23const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
24 imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX21 */
26
27#ifdef CONFIG_SOC_IMX25
28const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
29#define imx25_mxc_pwm_data_entry(_id, _hwid) \
30 imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
31 imx25_mxc_pwm_data_entry(0, 1),
32 imx25_mxc_pwm_data_entry(1, 2),
33 imx25_mxc_pwm_data_entry(2, 3),
34 imx25_mxc_pwm_data_entry(3, 4),
35};
36#endif /* ifdef CONFIG_SOC_IMX25 */
37
38#ifdef CONFIG_SOC_IMX27
39const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
40 imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
41#endif /* ifdef CONFIG_SOC_IMX27 */
42
43struct platform_device *__init imx_add_mxc_pwm(
44 const struct imx_mxc_pwm_data *data)
45{
46 struct resource res[] = {
47 {
48 .start = data->iobase,
49 .end = data->iobase + data->iosize - 1,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = data->irq,
53 .end = data->irq,
54 .flags = IORESOURCE_IRQ,
55 },
56 };
57
58 return imx_add_platform_device("mxc_pwm", data->id,
59 res, ARRAY_SIZE(res), NULL, 0);
60}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
new file mode 100644
index 000000000000..b4b7612b6e17
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12struct imx_mxc_rnga_data {
13 resource_size_t iobase;
14};
15
16#define imx_mxc_rnga_data_entry_single(soc) \
17 { \
18 .iobase = soc ## _RNGA_BASE_ADDR, \
19 }
20
21#ifdef CONFIG_SOC_IMX31
22static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
23 imx_mxc_rnga_data_entry_single(MX31);
24#endif /* ifdef CONFIG_SOC_IMX31 */
25
26static struct platform_device *__init imx_add_mxc_rnga(
27 const struct imx_mxc_rnga_data *data)
28{
29 struct resource res[] = {
30 {
31 .start = data->iobase,
32 .end = data->iobase + SZ_16K - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 };
36 return imx_add_platform_device("mxc_rnga", -1,
37 res, ARRAY_SIZE(res), NULL, 0);
38}
39
40static int __init imxXX_add_mxc_rnga(void)
41{
42 struct platform_device *ret;
43
44#if defined(CONFIG_SOC_IMX31)
45 if (cpu_is_mx31())
46 ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
47 else
48#endif /* if defined(CONFIG_SOC_IMX31) */
49 ret = ERR_PTR(-ENODEV);
50
51 if (IS_ERR(ret))
52 return PTR_ERR(ret);
53
54 return 0;
55}
56arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
new file mode 100644
index 000000000000..96fa5ea91fe8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_w1_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _OWIRE_BASE_ADDR, \
15 }
16
17#ifdef CONFIG_SOC_IMX21
18const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
19 imx_mxc_w1_data_entry_single(MX21);
20#endif /* ifdef CONFIG_SOC_IMX21 */
21
22#ifdef CONFIG_SOC_IMX27
23const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
24 imx_mxc_w1_data_entry_single(MX27);
25#endif /* ifdef CONFIG_SOC_IMX27 */
26
27#ifdef CONFIG_SOC_IMX31
28const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
29 imx_mxc_w1_data_entry_single(MX31);
30#endif /* ifdef CONFIG_SOC_IMX31 */
31
32#ifdef CONFIG_SOC_IMX35
33const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
34 imx_mxc_w1_data_entry_single(MX35);
35#endif /* ifdef CONFIG_SOC_IMX35 */
36
37struct platform_device *__init imx_add_mxc_w1(
38 const struct imx_mxc_w1_data *data)
39{
40 struct resource res[] = {
41 {
42 .start = data->iobase,
43 .end = data->iobase + SZ_4K - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 };
47
48 return imx_add_platform_device("mxc_w1", 0,
49 res, ARRAY_SIZE(res), NULL, 0);
50}
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
new file mode 100644
index 000000000000..b3525648a01d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11#include <mach/esdhc.h>
12
13#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_SOC_IMX25
24const struct imx_sdhci_esdhc_imx_data
25imx25_sdhci_esdhc_imx_data[] __initconst = {
26#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \
27 imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid)
28 imx25_sdhci_esdhc_imx_data_entry(0, 1),
29 imx25_sdhci_esdhc_imx_data_entry(1, 2),
30};
31#endif /* ifdef CONFIG_SOC_IMX25 */
32
33#ifdef CONFIG_SOC_IMX35
34const struct imx_sdhci_esdhc_imx_data
35imx35_sdhci_esdhc_imx_data[] __initconst = {
36#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \
37 imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid)
38 imx35_sdhci_esdhc_imx_data_entry(0, 1),
39 imx35_sdhci_esdhc_imx_data_entry(1, 2),
40 imx35_sdhci_esdhc_imx_data_entry(2, 3),
41};
42#endif /* ifdef CONFIG_SOC_IMX35 */
43
44#ifdef CONFIG_SOC_IMX51
45const struct imx_sdhci_esdhc_imx_data
46imx51_sdhci_esdhc_imx_data[] __initconst = {
47#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \
48 imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid)
49 imx51_sdhci_esdhc_imx_data_entry(0, 1),
50 imx51_sdhci_esdhc_imx_data_entry(1, 2),
51 imx51_sdhci_esdhc_imx_data_entry(2, 3),
52 imx51_sdhci_esdhc_imx_data_entry(3, 4),
53};
54#endif /* ifdef CONFIG_SOC_IMX51 */
55
56struct platform_device *__init imx_add_sdhci_esdhc_imx(
57 const struct imx_sdhci_esdhc_imx_data *data,
58 const struct esdhc_platform_data *pdata)
59{
60 struct resource res[] = {
61 {
62 .start = data->iobase,
63 .end = data->iobase + SZ_16K - 1,
64 .flags = IORESOURCE_MEM,
65 }, {
66 .start = data->irq,
67 .end = data->irq,
68 .flags = IORESOURCE_IRQ,
69 },
70 };
71
72 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
73 ARRAY_SIZE(res), pdata, sizeof(*pdata));
74}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 17f724c9452d..8ea49adcdfc1 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
30}; 30};
31#endif 31#endif
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { 34const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
35#define imx25_cspi_data_entry(_id, _hwid) \ 35#define imx25_cspi_data_entry(_id, _hwid) \
36 imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) 36 imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
38 imx25_cspi_data_entry(1, 2), 38 imx25_cspi_data_entry(1, 2),
39 imx25_cspi_data_entry(2, 3), 39 imx25_cspi_data_entry(2, 3),
40}; 40};
41#endif /* ifdef CONFIG_ARCH_MX25 */ 41#endif /* ifdef CONFIG_SOC_IMX25 */
42 42
43#ifdef CONFIG_SOC_IMX27 43#ifdef CONFIG_SOC_IMX27
44const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { 44const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
@@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
50}; 50};
51#endif /* ifdef CONFIG_SOC_IMX27 */ 51#endif /* ifdef CONFIG_SOC_IMX27 */
52 52
53#ifdef CONFIG_ARCH_MX31 53#ifdef CONFIG_SOC_IMX31
54const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { 54const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
55#define imx31_cspi_data_entry(_id, _hwid) \ 55#define imx31_cspi_data_entry(_id, _hwid) \
56 imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) 56 imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
@@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
58 imx31_cspi_data_entry(1, 2), 58 imx31_cspi_data_entry(1, 2),
59 imx31_cspi_data_entry(2, 3), 59 imx31_cspi_data_entry(2, 3),
60}; 60};
61#endif /* ifdef CONFIG_ARCH_MX31 */ 61#endif /* ifdef CONFIG_SOC_IMX31 */
62 62
63#ifdef CONFIG_ARCH_MX35 63#ifdef CONFIG_SOC_IMX35
64const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { 64const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
65#define imx35_cspi_data_entry(_id, _hwid) \ 65#define imx35_cspi_data_entry(_id, _hwid) \
66 imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) 66 imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
67 imx35_cspi_data_entry(0, 1), 67 imx35_cspi_data_entry(0, 1),
68 imx35_cspi_data_entry(1, 2), 68 imx35_cspi_data_entry(1, 2),
69}; 69};
70#endif /* ifdef CONFIG_ARCH_MX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_ARCH_MX51 72#ifdef CONFIG_SOC_IMX51
73const struct imx_spi_imx_data imx51_cspi_data __initconst = 73const struct imx_spi_imx_data imx51_cspi_data __initconst =
74 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); 74 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
75 75
@@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
79 imx51_ecspi_data_entry(0, 1), 79 imx51_ecspi_data_entry(0, 1),
80 imx51_ecspi_data_entry(1, 2), 80 imx51_ecspi_data_entry(1, 2),
81}; 81};
82#endif /* ifdef CONFIG_ARCH_MX51 */ 82#endif /* ifdef CONFIG_SOC_IMX51 */
83 83
84struct platform_device *__init imx_add_spi_imx( 84struct platform_device *__init imx_add_spi_imx(
85 const struct imx_spi_imx_data *data, 85 const struct imx_spi_imx_data *data,
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 9915607683de..8772ce346a58 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
49 49
50#define MXC_OTG_OFFSET 0 50#define MXC_OTG_OFFSET 0
51#define MXC_H1_OFFSET 0x200 51#define MXC_H1_OFFSET 0x200
52#define MXC_H2_OFFSET 0x400
52 53
53/* USB_CTRL */ 54/* USB_CTRL */
54#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ 55#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
61#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ 62#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
62#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ 63#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
63 64
65/* USBH2CTRL */
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69
64#define MXC_USBCMD_OFFSET 0x140 70#define MXC_USBCMD_OFFSET 0x140
65 71
66/* USBCMD */ 72/* USBCMD */
@@ -69,9 +75,9 @@
69int mxc_initialize_usb_hw(int port, unsigned int flags) 75int mxc_initialize_usb_hw(int port, unsigned int flags)
70{ 76{
71 unsigned int v; 77 unsigned int v;
72#if defined(CONFIG_ARCH_MX25) 78#if defined(CONFIG_SOC_IMX25)
73 if (cpu_is_mx25()) { 79 if (cpu_is_mx25()) {
74 v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + 80 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
75 USBCTRL_OTGBASE_OFFSET)); 81 USBCTRL_OTGBASE_OFFSET));
76 82
77 switch (port) { 83 switch (port) {
@@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
108 return -EINVAL; 114 return -EINVAL;
109 } 115 }
110 116
111 writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + 117 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
112 USBCTRL_OTGBASE_OFFSET)); 118 USBCTRL_OTGBASE_OFFSET));
113 return 0; 119 return 0;
114 } 120 }
115#endif /* CONFIG_ARCH_MX25 */ 121#endif /* if defined(CONFIG_SOC_IMX25) */
116#if defined(CONFIG_ARCH_MX3) 122#if defined(CONFIG_ARCH_MX3)
117 if (cpu_is_mx31()) { 123 if (cpu_is_mx31()) {
118 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 124 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
119 USBCTRL_OTGBASE_OFFSET)); 125 USBCTRL_OTGBASE_OFFSET));
120 126
121 switch (port) { 127 switch (port) {
@@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
153 return -EINVAL; 159 return -EINVAL;
154 } 160 }
155 161
156 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 162 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
157 USBCTRL_OTGBASE_OFFSET)); 163 USBCTRL_OTGBASE_OFFSET));
158 return 0; 164 return 0;
159 } 165 }
160 166
161 if (cpu_is_mx35()) { 167 if (cpu_is_mx35()) {
162 v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + 168 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
163 USBCTRL_OTGBASE_OFFSET)); 169 USBCTRL_OTGBASE_OFFSET));
164 170
165 switch (port) { 171 switch (port) {
@@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
196 return -EINVAL; 202 return -EINVAL;
197 } 203 }
198 204
199 writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + 205 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
200 USBCTRL_OTGBASE_OFFSET)); 206 USBCTRL_OTGBASE_OFFSET));
201 return 0; 207 return 0;
202 } 208 }
@@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
206 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they 212 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
207 * are identical 213 * are identical
208 */ 214 */
209 v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + 215 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
210 USBCTRL_OTGBASE_OFFSET)); 216 USBCTRL_OTGBASE_OFFSET));
211 switch (port) { 217 switch (port) {
212 case 0: /* OTG port */ 218 case 0: /* OTG port */
@@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
241 default: 247 default:
242 return -EINVAL; 248 return -EINVAL;
243 } 249 }
244 writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + 250 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
245 USBCTRL_OTGBASE_OFFSET)); 251 USBCTRL_OTGBASE_OFFSET));
246 return 0; 252 return 0;
247 } 253 }
248#endif /* CONFIG_MACH_MX27 */ 254#endif /* CONFIG_MACH_MX27 */
249#ifdef CONFIG_ARCH_MX51 255#ifdef CONFIG_SOC_IMX51
250 if (cpu_is_mx51()) { 256 if (cpu_is_mx51()) {
251 void __iomem *usb_base; 257 void __iomem *usb_base;
252 void __iomem *usbotg_base; 258 void __iomem *usbotg_base;
@@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
254 int ret = 0; 260 int ret = 0;
255 261
256 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 262 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
263 if (!usb_base) {
264 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
265 return -ENOMEM;
266 }
257 267
258 switch (port) { 268 switch (port) {
259 case 0: /* OTG port */ 269 case 0: /* OTG port */
@@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
262 case 1: /* Host 1 port */ 272 case 1: /* Host 1 port */
263 usbotg_base = usb_base + MXC_H1_OFFSET; 273 usbotg_base = usb_base + MXC_H1_OFFSET;
264 break; 274 break;
275 case 2: /* Host 2 port */
276 usbotg_base = usb_base + MXC_H2_OFFSET;
277 break;
265 default: 278 default:
266 printk(KERN_ERR"%s no such port %d\n", __func__, port); 279 printk(KERN_ERR"%s no such port %d\n", __func__, port);
267 ret = -ENOENT; 280 ret = -ENOENT;
@@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
274 if (flags & MXC_EHCI_INTERNAL_PHY) { 287 if (flags & MXC_EHCI_INTERNAL_PHY) {
275 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 288 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
276 289
277 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 290 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
278 v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ 291 /* OC/USBPWR is not used */
279 else 292 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
280 v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ 293 } else {
294 /* OC/USBPWR is used */
295 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
296 }
281 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 297 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
282 298
283 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 299 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
285 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ 301 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
286 else 302 else
287 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ 303 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
304 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
305 v |= MXC_OTG_UCTRL_OPM_BIT;
306 else
307 v &= ~MXC_OTG_UCTRL_OPM_BIT;
288 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 308 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
289 } 309 }
290 break; 310 break;
291 case 1: /* Host 1 */ 311 case 1: /* Host 1 */
292 /*Host ULPI */ 312 /*Host ULPI */
293 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 313 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
294 if (flags & MXC_EHCI_WAKEUP_ENABLED) 314 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
295 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ 315 /* HOST1 wakeup/ULPI intr enable */
296 else 316 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
297 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ 317 } else {
318 /* HOST1 wakeup/ULPI intr disable */
319 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
320 }
298 321
299 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 322 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
300 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ 323 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
@@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
315 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; 338 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
316 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); 339 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
317 break; 340 break;
341 case 2: /* Host 2 ULPI */
342 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
343 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
344 /* HOST1 wakeup/ULPI intr enable */
345 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
346 } else {
347 /* HOST1 wakeup/ULPI intr disable */
348 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
349 }
350
351 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
352 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
353 else
354 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
355 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
356 break;
318 } 357 }
319 358
320error: 359error:
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 9c3e36232b5b..bc2c7bc6f10a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176{ 176{
177 u32 irq_stat; 177 u32 irq_stat;
178 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); 178 struct mxc_gpio_port *port = get_irq_data(irq);
179 179
180 irq_stat = __raw_readl(port->base + GPIO_ISR) & 180 irq_stat = __raw_readl(port->base + GPIO_ISR) &
181 __raw_readl(port->base + GPIO_IMR); 181 __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
188{ 188{
189 int i; 189 int i;
190 u32 irq_msk, irq_stat; 190 u32 irq_msk, irq_stat;
191 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); 191 struct mxc_gpio_port *port = get_irq_data(irq);
192 192
193 /* walk through all interrupt status registers */ 193 /* walk through all interrupt status registers */
194 for (i = 0; i < gpio_table_size; i++) { 194 for (i = 0; i < gpio_table_size; i++) {
@@ -349,3 +349,113 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
349 349
350 return 0; 350 return 0;
351} 351}
352
353#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
354 { \
355 .chip.label = "gpio-" #_id, \
356 .irq = _irq, \
357 .irq_high = _irq_high, \
358 .base = soc ## _IO_ADDRESS( \
359 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
360 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
361 }
362
363#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
364 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
365#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
366 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
367
368#define DEFINE_REGISTER_FUNCTION(prefix) \
369int __init prefix ## _register_gpios(void) \
370{ \
371 return mxc_gpio_init(prefix ## _gpio_ports, \
372 ARRAY_SIZE(prefix ## _gpio_ports)); \
373}
374
375#if defined(CONFIG_SOC_IMX1)
376static struct mxc_gpio_port imx1_gpio_ports[] = {
377 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
378 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
379 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
380 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
381};
382
383DEFINE_REGISTER_FUNCTION(imx1)
384
385#endif /* if defined(CONFIG_SOC_IMX1) */
386
387#if defined(CONFIG_SOC_IMX21)
388static struct mxc_gpio_port imx21_gpio_ports[] = {
389 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
390 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
391 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
392 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
393 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
394 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
395};
396
397DEFINE_REGISTER_FUNCTION(imx21)
398
399#endif /* if defined(CONFIG_SOC_IMX21) */
400
401#if defined(CONFIG_SOC_IMX25)
402static struct mxc_gpio_port imx25_gpio_ports[] = {
403 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
404 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
405 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
406 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
407};
408
409DEFINE_REGISTER_FUNCTION(imx25)
410
411#endif /* if defined(CONFIG_SOC_IMX25) */
412
413#if defined(CONFIG_SOC_IMX27)
414static struct mxc_gpio_port imx27_gpio_ports[] = {
415 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
416 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
417 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
418 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
419 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
420 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
421};
422
423DEFINE_REGISTER_FUNCTION(imx27)
424
425#endif /* if defined(CONFIG_SOC_IMX27) */
426
427#if defined(CONFIG_SOC_IMX31)
428static struct mxc_gpio_port imx31_gpio_ports[] = {
429 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
430 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
431 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
432};
433
434DEFINE_REGISTER_FUNCTION(imx31)
435
436#endif /* if defined(CONFIG_SOC_IMX31) */
437
438#if defined(CONFIG_SOC_IMX35)
439static struct mxc_gpio_port imx35_gpio_ports[] = {
440 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
441 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
442 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
443};
444
445DEFINE_REGISTER_FUNCTION(imx35)
446
447#endif /* if defined(CONFIG_SOC_IMX35) */
448
449#if defined(CONFIG_SOC_IMX50)
450static struct mxc_gpio_port imx50_gpio_ports[] = {
451 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
452 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
453 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
454 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
455 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
456 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
457};
458
459DEFINE_REGISTER_FUNCTION(imx50)
460
461#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7a1e1f89ff09..aea2cd3b6d15 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,7 +20,9 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx50_map_io(void);
23extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void);
24extern void mxc91231_map_io(void); 26extern void mxc91231_map_io(void);
25extern void mxc_init_irq(void __iomem *); 27extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *); 28extern void tzic_init_irq(void __iomem *);
@@ -30,7 +32,9 @@ extern void mx25_init_irq(void);
30extern void mx27_init_irq(void); 32extern void mx27_init_irq(void);
31extern void mx31_init_irq(void); 33extern void mx31_init_irq(void);
32extern void mx35_init_irq(void); 34extern void mx35_init_irq(void);
35extern void mx50_init_irq(void);
33extern void mx51_init_irq(void); 36extern void mx51_init_irq(void);
37extern void mx53_init_irq(void);
34extern void mxc91231_init_irq(void); 38extern void mxc91231_init_irq(void);
35extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 39extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
36extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 40extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
@@ -42,6 +46,8 @@ extern int mx31_clocks_init(unsigned long fref);
42extern int mx35_clocks_init(void); 46extern int mx35_clocks_init(void);
43extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, 47extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
44 unsigned long ckih1, unsigned long ckih2); 48 unsigned long ckih1, unsigned long ckih2);
49extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
50 unsigned long ckih1, unsigned long ckih2);
45extern int mxc91231_clocks_init(unsigned long fref); 51extern int mxc91231_clocks_init(unsigned long fref);
46extern int mxc_register_gpios(void); 52extern int mxc_register_gpios(void);
47extern int mxc_register_device(struct platform_device *pdev, void *data); 53extern int mxc_register_device(struct platform_device *pdev, void *data);
@@ -50,5 +56,6 @@ extern void mxc_arch_reset_init(void __iomem *);
50extern void mxc91231_power_off(void); 56extern void mxc91231_power_off(void);
51extern void mxc91231_arch_reset(int, const char *); 57extern void mxc91231_arch_reset(int, const char *);
52extern void mxc91231_prepare_idle(void); 58extern void mxc91231_prepare_idle(void);
53 59extern void mx51_efikamx_reset(void);
60extern int mx53_revision(void);
54#endif 61#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index d56213fb901b..3b3a37c25c56 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -10,58 +10,49 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX_NEEDS_DEPRECATED_SYMBOLS 13#include <mach/hardware.h>
14 14
15#ifdef CONFIG_ARCH_MX1 15#ifdef CONFIG_ARCH_MX1
16#include <mach/mx1.h> 16#define UART_PADDR MX1_UART1_BASE_ADDR
17#define UART_PADDR UART1_BASE_ADDR
18#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
19#endif 17#endif
20 18
21#ifdef CONFIG_ARCH_MX25 19#ifdef CONFIG_ARCH_MX25
22#ifdef UART_PADDR 20#ifdef UART_PADDR
23#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 21#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
24#endif 22#endif
25#include <mach/mx25.h>
26#define UART_PADDR MX25_UART1_BASE_ADDR 23#define UART_PADDR MX25_UART1_BASE_ADDR
27#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
28#endif 24#endif
29 25
30#ifdef CONFIG_ARCH_MX2 26#ifdef CONFIG_ARCH_MX2
31#ifdef UART_PADDR 27#ifdef UART_PADDR
32#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 28#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
33#endif 29#endif
34#include <mach/mx2x.h> 30#define UART_PADDR MX2x_UART1_BASE_ADDR
35#define UART_PADDR UART1_BASE_ADDR
36#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
37#endif 31#endif
38 32
39#ifdef CONFIG_ARCH_MX3 33#ifdef CONFIG_ARCH_MX3
40#ifdef UART_PADDR 34#ifdef UART_PADDR
41#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 35#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
42#endif 36#endif
43#include <mach/mx3x.h> 37#define UART_PADDR MX3x_UART1_BASE_ADDR
44#define UART_PADDR UART1_BASE_ADDR
45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
46#endif 38#endif
47 39
48#ifdef CONFIG_ARCH_MX5 40#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR 41#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 42#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif 43#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR 44#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif 45#endif
56 46
57#ifdef CONFIG_ARCH_MXC91231 47#ifdef CONFIG_ARCH_MXC91231
58#ifdef UART_PADDR 48#ifdef UART_PADDR
59#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
60#endif 50#endif
61#include <mach/mxc91231.h>
62#define UART_PADDR MXC91231_UART2_BASE_ADDR 51#define UART_PADDR MXC91231_UART2_BASE_ADDR
63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
64#endif 52#endif
53
54#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
55
65 .macro addruart, rp, rv 56 .macro addruart, rp, rv
66 ldr \rp, =UART_PADDR @ physical 57 ldr \rp, =UART_PADDR @ physical
67 ldr \rv, =UART_VADDR @ virtual 58 ldr \rv, =UART_VADDR @ virtual
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8c6896fd1e5f..8658c9caa650 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -10,9 +10,19 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12 12
13struct platform_device *imx_add_platform_device(const char *name, int id, 13struct platform_device *imx_add_platform_device_dmamask(
14 const char *name, int id,
14 const struct resource *res, unsigned int num_resources, 15 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data); 16 const void *data, size_t size_data, u64 dmamask);
17
18static inline struct platform_device *imx_add_platform_device(
19 const char *name, int id,
20 const struct resource *res, unsigned int num_resources,
21 const void *data, size_t size_data)
22{
23 return imx_add_platform_device_dmamask(
24 name, id, res, num_resources, data, size_data, 0);
25}
16 26
17#include <linux/fec.h> 27#include <linux/fec.h>
18struct imx_fec_data { 28struct imx_fec_data {
@@ -24,15 +34,63 @@ struct platform_device *__init imx_add_fec(
24 const struct fec_platform_data *pdata); 34 const struct fec_platform_data *pdata);
25 35
26#include <linux/can/platform/flexcan.h> 36#include <linux/can/platform/flexcan.h>
27struct platform_device *__init imx_add_flexcan(int id, 37struct imx_flexcan_data {
28 resource_size_t iobase, resource_size_t iosize, 38 int id;
29 resource_size_t irq, 39 resource_size_t iobase;
40 resource_size_t iosize;
41 resource_size_t irq;
42};
43struct platform_device *__init imx_add_flexcan(
44 const struct imx_flexcan_data *data,
30 const struct flexcan_platform_data *pdata); 45 const struct flexcan_platform_data *pdata);
31 46
47#include <linux/fsl_devices.h>
48struct imx_fsl_usb2_udc_data {
49 resource_size_t iobase;
50 resource_size_t irq;
51};
52struct platform_device *__init imx_add_fsl_usb2_udc(
53 const struct imx_fsl_usb2_udc_data *data,
54 const struct fsl_usb2_platform_data *pdata);
55
32#include <linux/gpio_keys.h> 56#include <linux/gpio_keys.h>
33struct platform_device *__init imx_add_gpio_keys( 57struct platform_device *__init imx_add_gpio_keys(
34 const struct gpio_keys_platform_data *pdata); 58 const struct gpio_keys_platform_data *pdata);
35 59
60#include <mach/mx21-usbhost.h>
61struct imx_imx21_hcd_data {
62 resource_size_t iobase;
63 resource_size_t irq;
64};
65struct platform_device *__init imx_add_imx21_hcd(
66 const struct imx_imx21_hcd_data *data,
67 const struct mx21_usbh_platform_data *pdata);
68
69struct imx_imx2_wdt_data {
70 int id;
71 resource_size_t iobase;
72 resource_size_t iosize;
73};
74struct platform_device *__init imx_add_imx2_wdt(
75 const struct imx_imx2_wdt_data *data);
76
77struct imx_imxdi_rtc_data {
78 resource_size_t iobase;
79 resource_size_t irq;
80};
81struct platform_device *__init imx_add_imxdi_rtc(
82 const struct imx_imxdi_rtc_data *data);
83
84#include <mach/imxfb.h>
85struct imx_imx_fb_data {
86 resource_size_t iobase;
87 resource_size_t iosize;
88 resource_size_t irq;
89};
90struct platform_device *__init imx_add_imx_fb(
91 const struct imx_imx_fb_data *data,
92 const struct imx_fb_platform_data *pdata);
93
36#include <mach/i2c.h> 94#include <mach/i2c.h>
37struct imx_imx_i2c_data { 95struct imx_imx_i2c_data {
38 int id; 96 int id;
@@ -44,6 +102,16 @@ struct platform_device *__init imx_add_imx_i2c(
44 const struct imx_imx_i2c_data *data, 102 const struct imx_imx_i2c_data *data,
45 const struct imxi2c_platform_data *pdata); 103 const struct imxi2c_platform_data *pdata);
46 104
105#include <linux/input/matrix_keypad.h>
106struct imx_imx_keypad_data {
107 resource_size_t iobase;
108 resource_size_t iosize;
109 resource_size_t irq;
110};
111struct platform_device *__init imx_add_imx_keypad(
112 const struct imx_imx_keypad_data *data,
113 const struct matrix_keymap_data *pdata);
114
47#include <mach/ssi.h> 115#include <mach/ssi.h>
48struct imx_imx_ssi_data { 116struct imx_imx_ssi_data {
49 int id; 117 int id;
@@ -82,6 +150,67 @@ struct platform_device *__init imx_add_imx_uart_1irq(
82 const struct imx_imx_uart_1irq_data *data, 150 const struct imx_imx_uart_1irq_data *data,
83 const struct imxuart_platform_data *pdata); 151 const struct imxuart_platform_data *pdata);
84 152
153#include <mach/usb.h>
154struct imx_imx_udc_data {
155 resource_size_t iobase;
156 resource_size_t iosize;
157 resource_size_t irq0;
158 resource_size_t irq1;
159 resource_size_t irq2;
160 resource_size_t irq3;
161 resource_size_t irq4;
162 resource_size_t irq5;
163 resource_size_t irq6;
164};
165struct platform_device *__init imx_add_imx_udc(
166 const struct imx_imx_udc_data *data,
167 const struct imxusb_platform_data *pdata);
168
169#include <mach/mx1_camera.h>
170struct imx_mx1_camera_data {
171 resource_size_t iobase;
172 resource_size_t iosize;
173 resource_size_t irq;
174};
175struct platform_device *__init imx_add_mx1_camera(
176 const struct imx_mx1_camera_data *data,
177 const struct mx1_camera_pdata *pdata);
178
179#include <mach/mx2_cam.h>
180struct imx_mx2_camera_data {
181 resource_size_t iobasecsi;
182 resource_size_t iosizecsi;
183 resource_size_t irqcsi;
184 resource_size_t iobaseemmaprp;
185 resource_size_t iosizeemmaprp;
186 resource_size_t irqemmaprp;
187};
188struct platform_device *__init imx_add_mx2_camera(
189 const struct imx_mx2_camera_data *data,
190 const struct mx2_camera_platform_data *pdata);
191
192#include <mach/mxc_ehci.h>
193struct imx_mxc_ehci_data {
194 int id;
195 resource_size_t iobase;
196 resource_size_t irq;
197};
198struct platform_device *__init imx_add_mxc_ehci(
199 const struct imx_mxc_ehci_data *data,
200 const struct mxc_usbh_platform_data *pdata);
201
202#include <mach/mmc.h>
203struct imx_mxc_mmc_data {
204 int id;
205 resource_size_t iobase;
206 resource_size_t iosize;
207 resource_size_t irq;
208 resource_size_t dmareq;
209};
210struct platform_device *__init imx_add_mxc_mmc(
211 const struct imx_mxc_mmc_data *data,
212 const struct imxmmc_platform_data *pdata);
213
85#include <mach/mxc_nand.h> 214#include <mach/mxc_nand.h>
86struct imx_mxc_nand_data { 215struct imx_mxc_nand_data {
87 /* 216 /*
@@ -99,24 +228,39 @@ struct platform_device *__init imx_add_mxc_nand(
99 const struct imx_mxc_nand_data *data, 228 const struct imx_mxc_nand_data *data,
100 const struct mxc_nand_platform_data *pdata); 229 const struct mxc_nand_platform_data *pdata);
101 230
102#include <mach/spi.h> 231struct imx_mxc_pwm_data {
103struct imx_spi_imx_data {
104 const char *devid;
105 int id; 232 int id;
106 resource_size_t iobase; 233 resource_size_t iobase;
107 resource_size_t iosize; 234 resource_size_t iosize;
108 int irq; 235 resource_size_t irq;
109}; 236};
110struct platform_device *__init imx_add_spi_imx( 237struct platform_device *__init imx_add_mxc_pwm(
111 const struct imx_spi_imx_data *data, 238 const struct imx_mxc_pwm_data *data);
112 const struct spi_imx_master *pdata); 239
240struct imx_mxc_w1_data {
241 resource_size_t iobase;
242};
243struct platform_device *__init imx_add_mxc_w1(
244 const struct imx_mxc_w1_data *data);
113 245
114#include <mach/esdhc.h> 246#include <mach/esdhc.h>
115struct imx_esdhc_imx_data { 247struct imx_sdhci_esdhc_imx_data {
116 int id; 248 int id;
117 resource_size_t iobase; 249 resource_size_t iobase;
118 resource_size_t irq; 250 resource_size_t irq;
119}; 251};
120struct platform_device *__init imx_add_esdhc( 252struct platform_device *__init imx_add_sdhci_esdhc_imx(
121 const struct imx_esdhc_imx_data *data, 253 const struct imx_sdhci_esdhc_imx_data *data,
122 const struct esdhc_platform_data *pdata); 254 const struct esdhc_platform_data *pdata);
255
256#include <mach/spi.h>
257struct imx_spi_imx_data {
258 const char *devid;
259 int id;
260 resource_size_t iobase;
261 resource_size_t iosize;
262 int irq;
263};
264struct platform_device *__init imx_add_spi_imx(
265 const struct imx_spi_imx_data *data,
266 const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index aeb08697726b..bd9bb9799141 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -54,15 +54,15 @@
54#elif defined CONFIG_MXC_TZIC 54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority 55 @ Load offset & priority of the highest priority
56 @ interrupt pending. 56 @ interrupt pending.
57 @ 0x080 is INTSEC0 register
57 @ 0xD80 is HIPND0 register 58 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0 59 mov \irqnr, #0
59 mov \irqstat, #0x0D80 601000: add \irqstat, \base, \irqnr, lsr #3
601000: 61 ldr \tmp, [\irqstat, #0xd80]
61 ldr \tmp, [\irqstat, \base] 62 ldr \irqstat, [\irqstat, #0x080]
62 cmp \tmp, #0 63 ands \tmp, \tmp, \irqstat
63 bne 1001f 64 bne 1001f
64 addeq \irqnr, \irqnr, #32 65 add \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128 66 cmp \irqnr, #128
67 blo 1000b 67 blo 1000b
68 b 2001f 68 b 2001f
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index af33b74f569e..0044e2f1bea8 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -23,6 +23,11 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <asm-generic/gpio.h> 24#include <asm-generic/gpio.h>
25 25
26
27/* There's a off-by-one betweem the gpio bank number and the gpiochip */
28/* range e.g. GPIO_1_5 is gpio 5 under linux */
29#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
30
26/* use gpiolib dispatchers */ 31/* use gpiolib dispatchers */
27#define gpio_get_value __gpio_get_value 32#define gpio_get_value __gpio_get_value
28#define gpio_set_value __gpio_set_value 33#define gpio_set_value __gpio_set_value
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index ebadf4ac43fc..26bb1bab4aeb 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,13 +22,92 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#define IMX_IO_ADDRESS(addr, module) \ 25#ifdef __ASSEMBLER__
26 ((void __force __iomem *) \ 26#define IOMEM(addr) (addr)
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ 27#else
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) 28#define IOMEM(addr) ((void __force __iomem *)(addr))
29#endif
30
31#define IMX_IO_P2V_MODULE(addr, module) \
32 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
33 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
34
35/*
36 * This is rather complicated for humans and ugly to verify, but for a machine
37 * it's OK. Still more as it is usually only applied to constants. The upsides
38 * on using this approach are:
39 *
40 * - same mapping on all i.MX machines
41 * - works for assembler, too
42 * - no need to nurture #defines for virtual addresses
43 *
44 * The downside it, it's hard to verify (but I have a script for that).
45 *
46 * Obviously this needs to be injective for each SoC. In general it maps the
47 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
48 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
49 *
50 * It applies the following mappings for the different SoCs:
51 *
52 * mx1:
53 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
54 * mx21:
55 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
56 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
57 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
58 * mx25:
59 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
60 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
61 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
62 * mx27:
63 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
64 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
65 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
66 * mx31:
67 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
68 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
69 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
70 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
71 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
72 * mx35:
73 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
74 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
75 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
76 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
77 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
78 * mx50:
79 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
80 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
81 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
82 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
83 * mx51:
84 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
85 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
89 * mxc91231:
90 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
91 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
92 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
93 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
94 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
95 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
96 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
97 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
98 */
99#define IMX_IO_P2V(x) ( \
100 0xf4000000 + \
101 (((x) & 0x50000000) >> 6) + \
102 (((x) & 0x0b000000) >> 4) + \
103 (((x) & 0x000fffff)))
104
105#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
29 106
30#ifdef CONFIG_ARCH_MX5 107#ifdef CONFIG_ARCH_MX5
108#include <mach/mx50.h>
31#include <mach/mx51.h> 109#include <mach/mx51.h>
110#include <mach/mx53.h>
32#endif 111#endif
33 112
34#ifdef CONFIG_ARCH_MX3 113#ifdef CONFIG_ARCH_MX3
@@ -61,4 +140,11 @@
61 140
62#include <mach/mxc.h> 141#include <mach/mxc.h>
63 142
143#define imx_map_entry(soc, name, _type) { \
144 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
145 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
146 .length = soc ## _ ## name ## _SIZE, \
147 .type = _type, \
148}
149
64#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 150#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 5263506b7ddf..9de8f062ad5d 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -1,6 +1,8 @@
1/* 1/*
2 * This structure describes the machine which we are running on. 2 * This structure describes the machine which we are running on.
3 */ 3 */
4#ifndef __MACH_IMXFB_H__
5#define __MACH_IMXFB_H__
4 6
5#include <linux/fb.h> 7#include <linux/fb.h>
6 8
@@ -79,3 +81,4 @@ struct imx_fb_platform_data {
79}; 81};
80 82
81void set_imx_fb_info(struct imx_fb_platform_data *); 83void set_imx_fb_info(struct imx_fb_platform_data *);
84#endif /* ifndef __MACH_IMXFB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
new file mode 100644
index 000000000000..058a922ca147
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -0,0 +1,977 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX50_H__
20#define __MACH_IOMUX_MX50_H__
21
22#include <mach/iomux-v3.h>
23
24#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
25
26#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
28
29#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
30
31#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
33
34#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
36
37#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
39 PAD_CTL_DSE_HIGH)
40
41#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
43 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
44
45#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
47
48#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
50
51#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
52#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
53#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
54
55#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
56#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
58
59#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
60#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
62
63#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
64#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
65#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
66
67#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
68#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
69#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
70
71#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
72#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
73#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
74
75#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
76#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
78 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
79#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
80
81#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
82#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
83#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
84#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
85
86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
87 MX50_I2C_PAD_CTRL)
88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL)
90
91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
92 MX50_I2C_PAD_CTRL)
93#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
95
96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
97 MX50_I2C_PAD_CTRL)
98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL)
100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
101
102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
103 MX50_I2C_PAD_CTRL)
104#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
105#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
106#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
107
108#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
109 MX50_I2C_PAD_CTRL)
110#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
112#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
114#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
115
116#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
117 MX50_I2C_PAD_CTRL)
118#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
119#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
120#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
122#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
123#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
124 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
125
126#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
127#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
128#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
129#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
130
131#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
132#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
133#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
134 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
135#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
136#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
137#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
138
139#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
140#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
141#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
142#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
144#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
145
146#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
147#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
148#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
149 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
150#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
151#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
152#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
153
154#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
156#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
157#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
158
159#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
161
162#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
164
165#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
166#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
167#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
168
169#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
170#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
171#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
172
173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL)
176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
179#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
180
181#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
182#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
183#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
184#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
185#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
188
189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL)
190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
191
192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
194
195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL)
196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL)
198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
200
201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL)
205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL)
206
207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL)
208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
211
212#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
213#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
216
217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL)
218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
221
222#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
223#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
226
227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL)
228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
231#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
232#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
233
234#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
235#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
236#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
237#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
240
241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL)
242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL)
244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
247#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
248
249#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
250#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
251#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
252#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
253#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
254#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
255#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
256
257#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
259
260#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
262
263#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
265
266#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
267#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
268
269#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
271#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
272#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
273#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
274#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
276
277#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL)
282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
284
285#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
287#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
288#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
289#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
290#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
291#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
292
293#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL)
298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
300
301#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
303#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
304#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
305#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
306#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
307#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
308#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
309
310#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL)
315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
318
319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL)
320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL)
324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL)
325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
327
328#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
329#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
330#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
331#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
332#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
333#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
334#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
335#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
336
337#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
338#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
339#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
340
341#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
342#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
343#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
344
345#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
346#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
347#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
348
349#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
350#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
351#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
352
353#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
354#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
355#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
356
357#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
358#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
359
360#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
361#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
362#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
363
364#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
365#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
366#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
367
368#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
369#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
370#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
371#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
372
373#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
374#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
375#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
376#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
377
378#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
379#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
380#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
381#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
382
383#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
384#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
385#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
386#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
387
388#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
389#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
390#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
391#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
392#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
393#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
394
395#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
396#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
397#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
398#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
399#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
400#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
401
402#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
403#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
404#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
405#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
406#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
407#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
408
409#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
410#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
411#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
412#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
413#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
414#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
415
416#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
417#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
418#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
419#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
420#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
421
422#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
423#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
424#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
425#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
426#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
427
428#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
429
430#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
431
432#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
433
434#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
435
436#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
437
438#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
439
440#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
441
442#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
443
444#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
445
446#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
447
448#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
449
450#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
451
452#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
453
454#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
455#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
456#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
457
458#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
459#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
460#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
461#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
462
463#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
464#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
465#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
466#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
467
468#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
469#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
470#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
471#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
472#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
473
474#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
475#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
476#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
477#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
478
479#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
480#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
481#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
482#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
483
484#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
485#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
486#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
487#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
488#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
489
490#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
491#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
492#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
493#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
494
495
496#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
497#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
498#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
499#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
500
501#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
502#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
505
506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
510
511#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
512#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
513#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
514#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
515#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
516
517#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
518#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
519#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
520
521#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
522#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
523#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
524
525#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
526#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
527#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
528#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
529
530#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
531#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
532#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
533#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
534
535#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
536#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
537#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
538#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
539#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
540
541#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
542#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
543#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
544#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
545
546#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
547#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
548#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
549#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
550#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
551
552#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
553#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
554#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
555#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
556
557#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
558#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
559#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
560#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
561
562#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
563#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
564#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
565#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
566
567#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
568#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
569#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
570#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
571
572#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
573#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
574#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
575#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
576
577#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
578#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
579#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
580#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
581#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
582#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
583
584#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
585#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
586#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
587#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
588#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
589#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
590#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
591
592#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
593#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
594#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
595#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
596#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
597#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
598#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
599
600#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
601#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
602#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
603#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
604#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
605#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
606#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
607
608#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
609#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
610#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
611#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
612#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
613#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
614
615#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
616#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
617#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
618#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
619#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
620#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
621#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
622
623#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
624#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
625#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
626#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
627#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
628#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
629#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
630
631#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
632#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
633#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
634#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
635#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
636#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
637#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
638
639#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
640#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
641#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
642#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
643#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
644#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
645#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
646
647#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
648#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
649#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
650#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
651#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
652
653#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
654#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
655#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
656#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
657#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
658
659#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
660#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
661#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
662#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
663#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
664
665#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
666#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
667#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
668#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
669#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
670
671#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
672#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
673#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
674
675#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
676#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
677#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
678
679#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
680#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
681#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
682
683#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
684#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
685#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
686
687#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
688#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
689#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
690#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
691
692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL)
695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL)
696
697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
699#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
700#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
701
702#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
703#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
704#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
705#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
706
707#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
708#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
709#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
710#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
711
712#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
713#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
714#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
715#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
716
717#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
718#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
719#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
720#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
721#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
722
723#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
724#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
725#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
726#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
727#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
728
729#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
730#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
731#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
732#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
733#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
734
735#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
736#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
737#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
738#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
739#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
740
741#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
742#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
743#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
744#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
745#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
746
747#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
748#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
749#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
750#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
751#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
752
753#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
754#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
755#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
756#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
757#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
758
759#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
760#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
761#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
762#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
763#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
764
765#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
766#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
767#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
768#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
769#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
770
771#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
772#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
773#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
774#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
775#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
776
777#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
778#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
779#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
780#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
781#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
782
783#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
784#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
785#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
786#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
787#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
788
789#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
790#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
791#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
792#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
793#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
794
795#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
796#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
797#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
798#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
799#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
800
801#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
802#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
803#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
804#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
805#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
806
807#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
808#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
809#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
810#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
811#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
812
813#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
814#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
815#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
816#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
817#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
818
819#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
820#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
821#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
822#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
823#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
824#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
825
826#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
827#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
828#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
829#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
830
831#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
832#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
833#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
834
835#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
836#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
837#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
838
839#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
840#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
841#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
842
843#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
844#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
845#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
846
847#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
848#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
849#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
850
851#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
852#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
853#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
854
855#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
856#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
857#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
858
859#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
860#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
861#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
862
863#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
864#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
865#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
866
867#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
868#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
869#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
870
871#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
872#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
873#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
874
875#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
876#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
877#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
878
879#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
880#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
881#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
882
883#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
884#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
885#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
886
887#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
888#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
889#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
890
891#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
892#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
893#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
894
895#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
896#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
897#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
898
899#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
900#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
901#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
902
903#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
904#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
905#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
906
907#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
908#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
909#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
910
911#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
912#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
913#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
914
915#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
916#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
917#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
918
919#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
920#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
921#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
922#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
923
924#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
925#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
926#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
927#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
928
929#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
930#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
931#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
932 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
933#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
934
935#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
936#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
937#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
938#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
939
940#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
941#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
942#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
943
944#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
945#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
946
947#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
948#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
949
950#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
951#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
952
953#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
954#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
955
956#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
957#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
958
959#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
960#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
961
962#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
963#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
964
965#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
966#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
967
968#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
969#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
970
971#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
972#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
973
974#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
975#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
976
977#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index d7a41e9a2605..b6767f90ef14 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -15,373 +15,1553 @@
15 15
16#include <mach/iomux-v3.h> 16#include <mach/iomux-v3.h>
17 17
18/*
19 * various IOMUX alternate output functions (1-7)
20 */
21typedef enum iomux_config {
22 IOMUX_CONFIG_ALT0,
23 IOMUX_CONFIG_ALT1,
24 IOMUX_CONFIG_ALT2,
25 IOMUX_CONFIG_ALT3,
26 IOMUX_CONFIG_ALT4,
27 IOMUX_CONFIG_ALT5,
28 IOMUX_CONFIG_ALT6,
29 IOMUX_CONFIG_ALT7,
30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
32} iomux_pin_cfg_t;
33
34/* Pad control groupings */ 18/* Pad control groupings */
35#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ 19#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
36 PAD_CTL_DSE_HIGH) 20 PAD_CTL_HYS | PAD_CTL_SRE_FAST)
37#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
38 PAD_CTL_SRE_FAST)
39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
40 PAD_CTL_SRE_FAST)
41#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ 21#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
42 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) 22 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
43#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 23 PAD_CTL_HYS)
44 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 24#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
45 PAD_CTL_PKE | PAD_CTL_HYS) 25 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ 26 PAD_CTL_HYS)
47 PAD_CTL_SRE_FAST) 27#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
48#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 28 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_PUS_100K_UP) 29 PAD_CTL_HYS | PAD_CTL_PUE)
50#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 30#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
51 PAD_CTL_SRE_FAST) 31 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
52#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ 32#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
53 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ 33 PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
54 PAD_CTL_DVS) 34 PAD_CTL_SRE_FAST | PAD_CTL_DVS)
35#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
55 36
56#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 37#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
57 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) 38#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
58#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) 39#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
59#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) 40#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
60#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
61#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
62 41
63/* 42/*
64 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 43 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
65 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> 44 * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
66 * See also iomux-v3.h 45 * See also iomux-v3.h
67 */ 46 */
68 47
69/* PAD MUX ALT INPSE PATH PADCTRL */ 48/* Raw pin modes without pad control */
70#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) 49/* PAD MUX ALT INPSE PATH PADCTRL */
71#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) 50#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0)
72#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) 51#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0)
73#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) 52#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0)
74#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) 53#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0)
75#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) 54#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0)
76#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) 55#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0)
77#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) 56#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0)
78#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) 57#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0)
79#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) 58#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0)
80#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) 59#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0)
81#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) 60#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0)
82#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) 61#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0)
83#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) 62#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0)
84#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) 63#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0)
85#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) 64#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0)
86#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) 65#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0)
87#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ 66#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0)
88 0x09b4, 0, MX51_I2C_PAD_CTRL) 67#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0)
89#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) 68#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0)
90#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) 69#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0)
91#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 70#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0)
92#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ 71#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0)
93 0x09b0, 0, MX51_I2C_PAD_CTRL) 72#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0)
94#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 73#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0)
95#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 74#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0)
96#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 75#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0)
97#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 76#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0)
98#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) 77#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0)
99#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) 78#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0)
100#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) 79#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0)
101#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) 80#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0)
102#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) 81#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0)
103#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) 82#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0)
104#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) 83#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0)
105#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) 84#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0)
106#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) 85#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0)
107#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) 86#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0)
108#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) 87#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0)
109#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) 88#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0)
110#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) 89#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0)
111#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) 90#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0)
112#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) 91#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0)
113#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) 92#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0)
114#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) 93#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0)
115#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) 94#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0)
116#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) 95#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0)
117#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) 96#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0)
118#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) 97#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0)
119#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) 98#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0)
120#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 99#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0)
121#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 100#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0)
122#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 101#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0)
123#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) 102#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0)
124#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 103#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0)
125#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) 104#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0)
126#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 105#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0)
127#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 106#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0)
128#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 107#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0)
129#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 108#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0)
130#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) 109#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0)
131#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 110#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0)
132#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) 111#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0)
133#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 112#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0)
134#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) 113#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0)
135#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 114#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0)
136#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) 115#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0)
137#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 116#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0)
138#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) 117#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0)
139#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 118#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0)
140#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) 119#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0)
141#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) 120#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0)
142#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) 121#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0)
143#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) 122#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0)
144#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) 123#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0)
145#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) 124#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0)
146#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 125#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0)
147#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 126#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0)
148#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 127#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0)
149#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 128#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0)
150#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) 129#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0)
151#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 130#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0)
152#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 131#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0)
153#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) 132#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0)
154#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) 133#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0)
155#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) 134#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0)
156#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 135#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0)
157#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 136#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0)
158#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 137#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0)
159#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 138#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0)
160#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) 139#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0)
161#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 140#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0)
162#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) 141#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0)
163#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 142#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0)
164#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) 143#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0)
165#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 144#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0)
166#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) 145#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0)
167#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 146#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0)
168#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) 147#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0)
169#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 148#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0)
170#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) 149#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0)
171#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 150#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0)
172#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) 151#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0)
173#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 152#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0)
174#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 153#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0)
175#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 154#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0)
176#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 155#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0)
177#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 156#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0)
178#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) 157#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0)
179#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) 158#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0)
180#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) 159#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0)
181#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) 160#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0)
182#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) 161#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0)
183#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) 162#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0)
184#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) 163#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0)
185#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) 164#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0)
186#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) 165#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0)
187#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) 166#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0)
188#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) 167#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0)
189#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) 168#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0)
190#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) 169#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0)
191#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) 170#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0)
192#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) 171#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0)
193#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) 172#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0)
194#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) 173#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0)
195#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) 174#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0)
196#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) 175#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0)
197#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) 176#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0)
198#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) 177#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0)
199#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) 178#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0)
200#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) 179#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0)
201#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) 180#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0)
202#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) 181#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0)
203#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) 182#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0)
204#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 183#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0)
205#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 184#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0)
206#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 185#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0)
207#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) 186#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0)
208#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) 187#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0)
209#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) 188#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0)
210#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) 189#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0)
211#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) 190#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0)
212#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) 191#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0)
213#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) 192#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0)
214#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) 193#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0)
215#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) 194#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0)
216#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) 195#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0)
217#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) 196#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0)
218#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) 197#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0)
219#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) 198#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0)
220#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 199#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0)
221#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) 200#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0)
222#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 201#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0)
223#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 202#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0)
224#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 203#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0)
225#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 204#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0)
226#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 205#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0)
227#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 206#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0)
228#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 207#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0)
229#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 208#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0)
230#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 209#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0)
231#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 210#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0)
232#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 211#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0)
233#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 212#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0)
234#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 213#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0)
235#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 214#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0)
236#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 215#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0)
237#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 216#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0)
238#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 217#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0)
239#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 218#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0)
240#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 219#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0)
241#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 220#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0)
242#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 221#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0)
243#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 222#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0)
244#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) 223#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0)
245#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) 224#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0)
246#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) 225#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0)
247#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) 226#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0)
248#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) 227#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0)
249#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) 228#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0)
250#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) 229#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0)
251#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) 230#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0)
252#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) 231#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0)
253#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) 232#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0)
254#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) 233#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0)
255#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) 234#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0)
256#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) 235#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0)
257#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) 236#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0)
258#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) 237#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0)
259#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) 238#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0)
260#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 239#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0)
261#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 240#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0)
262#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) 241#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0)
263#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ 242#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0)
264 0x09b8, 1, MX51_I2C_PAD_CTRL) 243#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0)
265#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 244#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0)
266#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) 245#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0)
267#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ 246#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0)
268 0x09bc, 1, MX51_I2C_PAD_CTRL) 247#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0)
269#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 248#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0)
270#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 249#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0)
271#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 250#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0)
272#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) 251#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0)
273#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 252#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0)
274#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 253#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0)
275#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 254#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0)
276#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 255#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0)
277#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 256#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0)
278#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 257#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0)
279#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 258#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0)
280#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 259#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0)
281#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 260#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0)
282#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 261#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0)
283#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) 262#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0)
284#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) 263#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0)
285#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) 264#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0)
286#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) 265#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0)
287#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) 266#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0)
288#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) 267#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0)
289#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) 268#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0)
290#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) 269#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0)
291#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 270#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0)
292#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 271#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0)
293#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 272#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0)
294#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) 273#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0)
295#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) 274#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0)
296#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) 275#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0)
297#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) 276#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0)
298#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) 277#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0)
299#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) 278#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0)
300#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) 279#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0)
301#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) 280#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0)
302#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) 281#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0)
303#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) 282#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0)
304#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) 283#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0)
305#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) 284#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0)
306#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) 285#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0)
307#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) 286#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0)
308#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) 287#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0)
309#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) 288#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0)
310#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) 289#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0)
311#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) 290#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0)
312#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) 291#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0)
313#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) 292#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0)
314#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) 293#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0)
315#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) 294#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0)
316#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) 295#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0)
317#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) 296#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0)
318#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) 297#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0)
319#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) 298#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0)
320#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) 299#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0)
321#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) 300#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0)
322#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) 301#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0)
323#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) 302#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0)
324#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) 303#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0)
325#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) 304#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0)
326#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) 305#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0)
327#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) 306#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0)
328#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) 307#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0)
329#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) 308#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0)
330#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) 309#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0)
331#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) 310#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0)
332#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) 311#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0)
333#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) 312#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0)
334#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) 313#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0)
335#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) 314#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0)
336#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) 315#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0)
337#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) 316#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0)
338#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 317#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0)
339#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 318#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0)
340#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 319#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0)
341#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ 320#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0)
342 MX51_SDHCI_PAD_CTRL) 321#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0)
343#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) 322#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0)
344#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ 323#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0)
345 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) 324#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0)
346#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) 325#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0)
347#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ 326#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0)
348 MX51_SDHCI_PAD_CTRL) 327#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0)
349#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) 328#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0)
350#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ 329#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0)
351 MX51_SDHCI_PAD_CTRL) 330#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0)
352#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) 331#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0)
353#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ 332#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0)
354 MX51_SDHCI_PAD_CTRL) 333#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0)
355#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) 334#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0)
356#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ 335#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0)
357 MX51_SDHCI_PAD_CTRL) 336#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0)
358#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) 337#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0)
359#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ 338#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0)
360 MX51_SDHCI_PAD_CTRL) 339#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0)
361#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ 340#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0)
362 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) 341#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0)
363#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ 342#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0)
364 MX51_SDHCI_PAD_CTRL) 343#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0)
365#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ 344#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0)
366 MX51_SDHCI_PAD_CTRL) 345#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0)
367#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ 346#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0)
368 MX51_SDHCI_PAD_CTRL) 347#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0)
369#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ 348#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0)
370 MX51_SDHCI_PAD_CTRL) 349#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0)
371#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 350#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0)
372#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 351#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0)
373#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 352#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0)
374#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 353#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0)
375 0x9b8, 3, MX51_I2C_PAD_CTRL) 354#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0)
376#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 355#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0)
377#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 356#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0)
378 0x9bc, 3, MX51_I2C_PAD_CTRL) 357#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0)
379#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 358#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0)
380#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 359#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0)
381#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 360#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0)
382#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 361#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0)
383#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 362#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0)
384#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 363#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0)
385#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 364#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0)
365#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0)
366#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0)
367#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0)
368#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0)
369#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0)
370#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0)
371#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0)
372#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0)
373#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0)
374#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0)
375#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0)
376#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0)
377#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0)
378#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0)
379#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0)
380#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0)
381#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0)
382#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0)
383#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0)
384#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0)
385#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0)
386#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0)
387#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0)
388#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0)
389#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0)
390#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0)
391#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0)
392#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0)
393#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0)
394#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0)
395#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0)
396#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0)
397#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0)
398#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0)
399#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0)
400#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0)
401#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0)
402#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0)
403#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0)
404#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0)
405#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0)
406#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0)
407#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0)
408#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0)
409#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0)
410#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0)
411#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0)
412#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0)
413#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0)
414#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0)
415#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0)
416#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0)
417#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0)
418#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0)
419#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0)
420#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0)
421#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0)
422#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0)
423#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0)
424#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0)
425#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0)
426#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0)
427#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0)
428#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0)
429#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0)
430#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0)
431#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0)
432#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0)
433#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0)
434#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0)
435#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0)
436#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0)
437#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0)
438#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0)
439#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0)
440#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0)
441#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0)
442#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0)
443#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0)
444#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0)
445#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0)
446#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0)
447#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0)
448#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0)
449#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0)
450#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0)
451#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0)
452#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0)
453#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0)
454#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0)
455#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0)
456#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0)
457#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0)
458#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0)
459#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0)
460#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0)
461#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0)
462#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0)
463#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0)
464#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0)
465#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0)
466#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0)
467#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0)
468#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0)
469#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0)
470#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0)
471#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0)
472#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0)
473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0)
477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
480#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0)
481#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0)
482#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0)
483#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0)
484#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0)
485#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0)
486#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0)
487#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0)
488#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0)
489#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0)
490#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0)
491#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0)
492#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0)
493#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0)
494#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0)
495#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0)
496#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0)
497#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0)
498#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0)
499#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0)
500#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0)
501#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0)
502#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0)
503#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0)
504#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0)
505#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0)
506#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0)
507#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0)
508#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0)
509#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0)
510#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0)
511#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0)
512#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0)
513#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0)
514#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0)
515#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0)
516#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0)
517#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0)
518#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0)
519#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0)
520#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0)
521#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0)
522#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0)
523#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0)
524#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0)
525#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0)
526#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0)
527#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0)
528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0)
532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
535#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0)
536#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0)
537#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0)
538#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0)
539#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0)
540#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0)
541#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0)
542#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0)
543#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0)
544#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0)
545#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0)
546#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0)
547#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0)
548#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0)
549#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0)
550#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0)
551#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0)
552#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0)
553#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0)
554#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0)
555#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0)
556#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0)
557#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0)
558#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0)
559#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0)
560#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0)
561#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0)
562#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0)
563#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0)
564#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0)
565#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0)
566#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0)
567#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
568#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0)
569#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0)
570#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0)
571#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0)
572#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
573#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
574#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0)
575#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
576#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
577#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0)
578#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0)
579#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0)
580#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0)
581#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0)
582#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0)
583#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0)
584#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0)
585#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0)
586#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0)
587#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0)
588#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0)
589#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0)
590#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0)
591#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0)
592#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0)
593#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0)
594#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0)
595#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0)
596#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0)
597#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0)
598#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0)
599#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0)
600#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0)
601#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0)
602#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0)
603#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0)
604#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0)
605#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0)
606#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0)
607#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0)
608#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0)
609#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0)
610#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0)
611#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0)
612#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0)
613#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0)
614#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0)
615#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0)
616#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0)
617#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0)
618#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0)
619#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0)
620#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0)
621#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0)
622#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0)
623#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0)
624#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0)
625#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0)
626#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0)
627#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0)
628#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0)
629#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0)
630#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0)
631#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0)
632#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0)
633#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0)
634#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0)
635#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0)
636#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0)
637#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0)
638#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0)
639#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0)
640#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0)
641#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0)
642#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0)
643#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0)
644#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0)
645#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0)
646#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0)
647#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0)
648#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0)
649#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0)
650#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0)
651#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0)
652#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0)
653#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0)
654#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0)
655#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0)
656#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0)
657#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0)
658#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0)
659#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0)
660#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0)
661#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0)
662#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0)
663#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0)
664#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0)
665#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0)
666#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0)
667#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0)
668#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0)
669#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0)
670#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0)
671#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0)
672#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0)
673#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0)
674#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0)
675#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0)
676#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0)
677#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0)
678#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0)
679#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0)
680#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0)
681#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0)
682#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0)
683#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0)
684#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0)
685#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0)
686#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0)
687#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0)
688#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0)
689#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0)
690#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0)
691#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0)
692#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0)
693#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0)
694#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0)
695#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0)
696#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0)
697#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0)
698#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0)
699#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0)
700#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0)
701#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0)
702#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0)
703#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0)
704#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0)
705#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0)
706#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0)
707#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0)
708#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0)
709#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0)
710#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0)
711#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0)
712#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0)
713#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0)
714#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0)
715#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0)
716#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0)
717#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0)
718#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0)
719#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0)
720#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0)
721#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0)
722#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0)
723#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0)
724#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0)
725#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0)
726#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0)
727#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0)
728#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0)
729#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0)
730#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0)
731#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0)
732#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0)
733#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0)
734#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0)
735#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0)
736#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0)
737#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0)
738#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0)
739#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0)
740#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0)
741#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0)
742#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0)
743#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0)
744#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0)
745#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0)
746#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0)
747#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0)
748#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0)
749#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0)
750#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0)
751#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0)
752#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0)
753#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0)
754#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0)
755#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0)
756#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0)
757#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0)
758#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0)
759#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0)
760#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0)
761#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0)
762#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0)
763#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0)
764#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0)
765#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0)
766#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0)
767#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0)
768#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0)
769#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0)
770#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0)
771#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0)
772#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0)
773#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0)
774#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0)
775#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0)
776#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0)
777#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0)
778#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0)
779#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0)
780#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0)
781#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0)
782#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0)
783#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0)
784#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0)
785#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0)
786#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0)
787#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0)
788#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0)
789#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0)
790#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0)
791#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0)
792#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0)
793#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0)
794#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0)
795#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0)
796#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0)
797#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0)
798#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0)
799#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0)
800#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0)
801#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0)
802#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0)
803#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0)
804#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0)
805#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0)
806
807/* The same pins as above but with the default pad control values applied */
808#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
809#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
810#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
811#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
812#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
813#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
814#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
815#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
816#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
817#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
818#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
819#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
820#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
821#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
822#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
823#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
824#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
825#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
826#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
827#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
828#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
829#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
830#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
831#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
832#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
833#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
834#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
835#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL))
836#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
837#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
838#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
839#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
840#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL))
841#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
842#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
843#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
844#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
845#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL))
846#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
847#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
848#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
849#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL))
850#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
851#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
852#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
853#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
854#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL))
855#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
856#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
857#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
858#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
859#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL))
860#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
861#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
862#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
863#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
864#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL))
865#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
866#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
867#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
868#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
869#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
870#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL))
871#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
872#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
873#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
874#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
875#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
876#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL))
877#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
878#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
879#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
880#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL))
881#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
882#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
883#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
884#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL))
885#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
886#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
887#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
888#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL))
889#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
890#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
891#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL))
892#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
893#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
894#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL))
895#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
896#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
897#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
898#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL))
899#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
900#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
901#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL))
902#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
903#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
904#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL))
905#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
906#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
907#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL))
908#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
909#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL))
910#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
911#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
912#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL))
913#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
914#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL))
915#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
916#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
917#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
918#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL))
919#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
920#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
921#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
922#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
923#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL))
924#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
925#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
926#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
927#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
928#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL))
929#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
930#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
931#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
932#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
933#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
934#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
935#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
936#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \
937 MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
938 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
939#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
940#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
941#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
942#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
943#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
944#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
945#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
946#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
947#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
948#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
949#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
950#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
951#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
952#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
953#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
954#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
955#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
956#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
957#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
958#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
959#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
960#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
961#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
962#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
963#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
964#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
965#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
966#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
967#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
968#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
969#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
970#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
971#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
972#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
973#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
974#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
975#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
976#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
977#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
978#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL))
979#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
980#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
981#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
982#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
983#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
984#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
996#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
997#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
998#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
1017#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1018#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1019#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1020#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1021#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1022#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1023#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
1024#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1025#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1026#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1027#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1028#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1029#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1030#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1031#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1032#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1033#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1034#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1035#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1077#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1078#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1079#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1080#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1081#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1082#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1083#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1084#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1085#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1086#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1087#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1088#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1089#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1090#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1091#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1092#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1093#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1094#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
1095#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1096#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1097#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1098#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1099#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1100#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1101#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1102#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1103#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1104#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1105#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1106#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1107#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1108#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1109#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1110#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1111#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1112#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1113#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1114#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1115#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1116#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1117#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1118#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1119#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1120#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1121#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1122#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1123#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1124#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1125#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
1126#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1127#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1128#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1129#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1130#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
1131#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1132#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1133#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1134#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1135#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1136#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1137#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1138#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1139#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1140#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1141#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1142#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1143#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1144#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1145#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1146#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1147#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1148#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1149#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1150#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1151#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1152#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1153#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1154#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1155#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1156#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1157#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1158#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1159#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1160#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1161#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1162#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1163#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1164#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1165#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1166#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1167#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1168#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1169#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1170#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1171#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1172#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1173#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1174#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1175#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1176#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1177#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1178#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1179#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1180#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1181#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1182#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1183#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1184#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1185#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1186#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1187#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1188#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1189#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1190#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1191#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1192#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1193#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1194#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1195#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1196#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1197#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1198#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1199#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1200#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1201#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1202#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1203#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1204#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1205#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1206#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1207#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1208#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1209#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1210#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1211#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1212#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1213#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1214#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1215#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1216#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1217#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1218#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1219#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1220#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1221#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1222#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1223#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1224#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1225#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1226#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1227#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1228#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1229#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1230#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1231#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1232#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1233#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1234#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1235#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1236#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1237#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1238#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1239#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
1240#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1241#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1242#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1243#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1244#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1245#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1246#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
1247#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
1248#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1249#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1250#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1251#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1252#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1253#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1254#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1255#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1256#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1257#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1258#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1259#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1260#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1261#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1262#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1263#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1264#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1265#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1266#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1267#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1268#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1269#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1270#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1271#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1272#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1273#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1274#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1275#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1276#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1277#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1278#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1279#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1280#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1281#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1282#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1283#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1284#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1285#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1286#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1287#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1288#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1289#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1290#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1291#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1292#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1293#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1294#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1295#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1296#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1297#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1298#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1299#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1300#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1301#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1302#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1303#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1304#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1305#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1306#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1307#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1308#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1309#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1310#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1311#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1312#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1313#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1314#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1315#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1316#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1317#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1318#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1319#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1320#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1321#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1322#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1323#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1324#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1325#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1326#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1327#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1328#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1329#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1330#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1331#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1332#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1333#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1334#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1335#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1336#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1337#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1338#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1339#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1340#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1341#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1342#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1343#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1344#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL))
1345#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1346#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL))
1347#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1348#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1349#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1350#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1351#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1352#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL))
1353#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1354#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1355#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1356#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
1357#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1358#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1359#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1360#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1361#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1362#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL))
1363#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1364#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1365#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1366#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1367#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1368#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1369#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1370#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1371#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1372#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1373#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1374#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1375#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1376#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1377#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1378#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1379#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1380#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1381#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1382#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1383#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1384#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1385#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1386#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1387#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1388#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1389#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1390#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1391#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1392#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1393#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1394#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1395#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1396#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1397#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1398#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1399#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1400#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1401#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1402#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
1403#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1404#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1405#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1406#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1407#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1408#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1409#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1410#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1411#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1412#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1413#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1414#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1415#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1416#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1417#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1418#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1419#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
1420#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1421#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1422#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1423#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1424#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1425#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1426#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1427#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1428#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1429#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1430#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1431#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1432#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1433#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1434#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1435#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1436#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1437#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1438#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1439#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1440#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1441#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1442#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1443#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1444#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1445#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1446#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1447#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1448#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1449#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
1450#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1451#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1452#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1453#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1454#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1455#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1456#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1457#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1458#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1459#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
1460#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1461#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1462#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1463#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1464#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1465#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1466#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1467#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1468#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1469#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1470#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1471#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1472#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1473#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1474#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1475#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1476#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1477#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1478#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1505#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1506#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1507#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1508#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1509#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1510#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1511#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1512#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1513#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1514#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1515#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1516#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1533#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1534#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1535#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1536#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1537#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1538#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1539#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1540#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1541#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1542#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1543#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1544#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1545#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1546#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1547#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1548#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1549#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1550#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1551#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1552#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1553#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1554#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1555#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1556#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1557#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1558#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1559#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1560#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1561#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1562#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1563#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1564#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1565#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
386 1566
387#endif /* __MACH_IOMUX_MX51_H__ */ 1567#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
new file mode 100644
index 000000000000..5deee019c29e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -0,0 +1,323 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc..
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX53_H__
20#define __MACH_IOMUX_MX53_H__
21
22#include <mach/iomux-v3.h>
23
24/*
25 * various IOMUX alternate output functions (1-7)
26 */
27typedef enum iomux_config {
28 IOMUX_CONFIG_ALT0,
29 IOMUX_CONFIG_ALT1,
30 IOMUX_CONFIG_ALT2,
31 IOMUX_CONFIG_ALT3,
32 IOMUX_CONFIG_ALT4,
33 IOMUX_CONFIG_ALT5,
34 IOMUX_CONFIG_ALT6,
35 IOMUX_CONFIG_ALT7,
36 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
37 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
38} iomux_pin_cfg_t;
39
40/* These 2 defines are for pins that may not have a mux register, but could
41 * have a pad setting register, and vice-versa. */
42#define NON_MUX_I 0x00
43#define NON_PAD_I 0x00
44
45#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47/* UART1 */
48#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
49#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
50#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
51#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
52
53/* UART2 */
54#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
55#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
56#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
57#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
58
59/* UART3 */
60#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
61#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
62#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL)
63#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
64
65#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
66#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
67#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
68#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
69#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
70#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
71#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
72#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
73#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
74#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
75#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
76#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
77#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
78#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
79#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
80#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
81#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
82#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
83#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
84#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
85#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
86#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
87#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
88#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
89#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
90#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
91#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
92#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
93#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
94#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
95#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
96#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
97#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
98#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
99#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
100#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
101#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
102#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
103#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
104#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
105#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
106#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
107#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
108#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
109#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
110#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
111#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
112#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
113#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
114#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
115#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
116#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
117#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
118#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
119#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
120#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
121#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
122#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
123#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
124#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
125#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
126#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
127#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
128#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
129#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
130#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
131#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
132#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
133#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
134#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
135#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
136#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
137#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
138#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
139#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
140#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
141#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
142#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
143#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
144#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
145#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
146#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
147#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
148#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
149#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
150#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
151#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
152#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
153#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
154#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
155#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
156#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
157#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
158#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
159#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
160#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
161#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
162#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
163#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
164#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
165#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
166#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
167#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
168#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
169#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
170#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
171#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
172#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
173#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
174#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
175#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
176#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
177#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
178#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
179#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
180#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
181#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
182#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
183#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
184#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
185#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
186#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
187#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
188#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
189#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
190#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
191#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
192#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
193#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
194#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
195#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
196#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
197#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
198#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
199#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
200#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
201#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
202#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
203#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
204#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
205#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
206#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
207#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
208#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
209#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
210#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
211#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
212#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
213#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
214#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
215#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
216#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
217#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
218#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
219#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
220#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
221#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
222#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
223#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
224#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
225#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
226#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
227#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
228#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
229#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
230#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
231#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
232#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
233#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
234#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
235#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
236#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
237#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
238#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
239#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
240#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
241#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
242#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
243#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
244#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
245#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
246#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
247#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
248#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
249#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
250#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
251#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
252#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
253#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
254#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
255#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
256#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
257#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
258#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
259#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
260#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
261#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
262#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
263#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
264#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
265#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
266#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
267#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
268#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
269#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
270#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
271#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
272#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
273#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
274#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
275#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
276#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
277#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
278#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
279#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
280#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
281#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
282#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
283#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
284#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
285#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
286#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
287#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
288#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
289#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
290#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
291#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
292#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
293#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
294#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
295#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
296#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
297#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
298#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
299#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
300#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
301#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
302#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
303#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
304#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
305#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
306#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
307#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
308#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
309#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
310#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
311#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
312#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
313#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
314#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
315#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
316#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
317#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
318#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
319#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
320#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
321#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
322
323#endif /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 0880a4a1aed1..2277b01c855d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -42,28 +42,44 @@
42 * If <padname> or <padmode> refers to a GPIO, it is named 42 * If <padname> or <padmode> refers to a GPIO, it is named
43 * GPIO_<unit>_<num> 43 * GPIO_<unit>_<num>
44 * 44 *
45 */ 45 * IOMUX/PAD Bit field definitions
46 46 *
47struct pad_desc { 47 * MUX_CTRL_OFS: 0..11 (12)
48 unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ 48 * PAD_CTRL_OFS: 12..23 (12)
49 unsigned mux_mode:8; 49 * SEL_INPUT_OFS: 24..35 (12)
50 unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ 50 * MUX_MODE + SION: 36..40 (5)
51#define NO_PAD_CTRL (1 << 16) 51 * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
52 unsigned pad_ctrl:17; 52 * SEL_INP: 58..61 (4)
53 unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ 53 * reserved: 63 (1)
54 unsigned select_input:3; 54*/
55}; 55
56 56typedef u64 iomux_v3_cfg_t;
57#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ 57
58 _select_input, _pad_ctrl) \ 58#define MUX_CTRL_OFS_SHIFT 0
59 { \ 59#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
60 .mux_ctrl_ofs = _mux_ctrl_ofs, \ 60#define MUX_PAD_CTRL_OFS_SHIFT 12
61 .mux_mode = _mux_mode, \ 61#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
62 .pad_ctrl_ofs = _pad_ctrl_ofs, \ 62#define MUX_SEL_INPUT_OFS_SHIFT 24
63 .pad_ctrl = _pad_ctrl, \ 63#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
64 .select_input_ofs = _select_input_ofs, \ 64
65 .select_input = _select_input, \ 65#define MUX_MODE_SHIFT 36
66 } 66#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
67#define MUX_PAD_CTRL_SHIFT 41
68#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
69#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16))
70#define MUX_SEL_INPUT_SHIFT 58
71#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
72
73#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
74
75#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
76 _sel_input, _pad_ctrl) \
77 (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
78 ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
79 ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
80 ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
81 ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
82 ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
67 83
68/* 84/*
69 * Use to set PAD control 85 * Use to set PAD control
@@ -107,13 +123,13 @@ struct pad_desc {
107/* 123/*
108 * setups a single pad in the iomuxer 124 * setups a single pad in the iomuxer
109 */ 125 */
110int mxc_iomux_v3_setup_pad(struct pad_desc *pad); 126int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
111 127
112/* 128/*
113 * setups mutliple pads 129 * setups mutliple pads
114 * convenient way to call the above function with tables 130 * convenient way to call the above function with tables
115 */ 131 */
116int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); 132int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
117 133
118/* 134/*
119 * Initialise the iomux controller 135 * Initialise the iomux controller
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 86781f7b0c0c..58a49cc83797 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,13 +23,17 @@
23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24 24
25/* these are ordered by size to support multi-SoC kernels */ 25/* these are ordered by size to support multi-SoC kernels */
26#if defined CONFIG_ARCH_MX2 26#if defined CONFIG_ARCH_MX53
27#define MXC_GPIO_IRQS (32 * 7)
28#elif defined CONFIG_ARCH_MX2
29#define MXC_GPIO_IRQS (32 * 6)
30#elif defined CONFIG_ARCH_MX50
27#define MXC_GPIO_IRQS (32 * 6) 31#define MXC_GPIO_IRQS (32 * 6)
28#elif defined CONFIG_ARCH_MX1 32#elif defined CONFIG_ARCH_MX1
29#define MXC_GPIO_IRQS (32 * 4) 33#define MXC_GPIO_IRQS (32 * 4)
30#elif defined CONFIG_ARCH_MX25 34#elif defined CONFIG_ARCH_MX25
31#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
32#elif defined CONFIG_ARCH_MX5 36#elif defined CONFIG_ARCH_MX51
33#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
34#elif defined CONFIG_ARCH_MXC91231 38#elif defined CONFIG_ARCH_MXC91231
35#define MXC_GPIO_IRQS (32 * 4) 39#define MXC_GPIO_IRQS (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 564ec9dbc93d..83861408133f 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,7 +16,9 @@
16#define MX25_PHYS_OFFSET UL(0x80000000) 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000) 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX50_PHYS_OFFSET UL(0x70000000)
19#define MX51_PHYS_OFFSET UL(0x90000000) 20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000)
20#define MXC91231_PHYS_OFFSET UL(0x90000000) 22#define MXC91231_PHYS_OFFSET UL(0x90000000)
21 23
22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 24#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -32,8 +34,12 @@
32# define PHYS_OFFSET MX3x_PHYS_OFFSET 34# define PHYS_OFFSET MX3x_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MXC91231 35# elif defined CONFIG_ARCH_MXC91231
34# define PHYS_OFFSET MXC91231_PHYS_OFFSET 36# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5 37# elif defined CONFIG_ARCH_MX50
38# define PHYS_OFFSET MX50_PHYS_OFFSET
39# elif defined CONFIG_ARCH_MX51
36# define PHYS_OFFSET MX51_PHYS_OFFSET 40# define PHYS_OFFSET MX51_PHYS_OFFSET
41# elif defined CONFIG_ARCH_MX53
42# define PHYS_OFFSET MX53_PHYS_OFFSET
37# endif 43# endif
38#endif 44#endif
39 45
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 641b24618239..75d96214b831 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -19,7 +19,6 @@
19 */ 19 */
20#define MX1_IO_BASE_ADDR 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define MX1_IO_SIZE SZ_1M 21#define MX1_IO_SIZE SZ_1M
22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 22
24#define MX1_CS0_PHYS 0x10000000 23#define MX1_CS0_PHYS 0x10000000
25#define MX1_CS0_SIZE 0x02000000 24#define MX1_CS0_SIZE 0x02000000
@@ -66,6 +65,10 @@
66#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) 65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
67#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) 66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) 67#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
70#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
71#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
69#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) 72#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
70#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) 73#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
71#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) 74#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
@@ -73,12 +76,12 @@
73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) 76#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 77
75/* macro to get at IO space when running virtually */ 78/* macro to get at IO space when running virtually */
76#define MX1_IO_ADDRESS(x) ( \ 79#define MX1_IO_P2V(x) IMX_IO_P2V(x)
77 IMX_IO_ADDRESS(x, MX1_IO)) 80#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
78 81
79/* fixed interrput numbers */ 82/* fixed interrput numbers */
80#define MX1_INT_SOFTINT 0 83#define MX1_INT_SOFTINT 0
81#define MX1_CSI_INT 6 84#define MX1_INT_CSI 6
82#define MX1_DSPA_MAC_INT 7 85#define MX1_DSPA_MAC_INT 7
83#define MX1_DSPA_INT 8 86#define MX1_DSPA_INT 8
84#define MX1_COMP_INT 9 87#define MX1_COMP_INT 9
@@ -115,13 +118,13 @@
115#define MX1_SSI_RX_INT 44 118#define MX1_SSI_RX_INT 44
116#define MX1_SSI_RX_ERR_INT 45 119#define MX1_SSI_RX_ERR_INT 45
117#define MX1_TOUCH_INT 46 120#define MX1_TOUCH_INT 46
118#define MX1_USBD_INT0 47 121#define MX1_INT_USBD0 47
119#define MX1_USBD_INT1 48 122#define MX1_INT_USBD1 48
120#define MX1_USBD_INT2 49 123#define MX1_INT_USBD2 49
121#define MX1_USBD_INT3 50 124#define MX1_INT_USBD3 50
122#define MX1_USBD_INT4 51 125#define MX1_INT_USBD4 51
123#define MX1_USBD_INT5 52 126#define MX1_INT_USBD5 52
124#define MX1_USBD_INT6 53 127#define MX1_INT_USBD6 53
125#define MX1_BTSYS_INT 55 128#define MX1_BTSYS_INT 55
126#define MX1_BTTIM_INT 56 129#define MX1_BTTIM_INT 56
127#define MX1_BTWUI_INT 57 130#define MX1_BTWUI_INT 57
@@ -164,134 +167,6 @@
164 * to not break drivers/usb/gadget/imx_udc. Should go 167 * to not break drivers/usb/gadget/imx_udc. Should go
165 * away after this driver uses the new name. 168 * away after this driver uses the new name.
166 */ 169 */
167#define USBD_INT0 MX1_USBD_INT0 170#define USBD_INT0 MX1_INT_USBD0
168
169#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
170/* these should go away */
171#define IMX_IO_PHYS MX1_IO_BASE_ADDR
172#define IMX_IO_SIZE MX1_IO_SIZE
173#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
174#define IMX_CS0_PHYS MX1_CS0_PHYS
175#define IMX_CS0_SIZE MX1_CS0_SIZE
176#define IMX_CS1_PHYS MX1_CS1_PHYS
177#define IMX_CS1_SIZE MX1_CS1_SIZE
178#define IMX_CS2_PHYS MX1_CS2_PHYS
179#define IMX_CS2_SIZE MX1_CS2_SIZE
180#define IMX_CS3_PHYS MX1_CS3_PHYS
181#define IMX_CS3_SIZE MX1_CS3_SIZE
182#define IMX_CS4_PHYS MX1_CS4_PHYS
183#define IMX_CS4_SIZE MX1_CS4_SIZE
184#define IMX_CS5_PHYS MX1_CS5_PHYS
185#define IMX_CS5_SIZE MX1_CS5_SIZE
186#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
187#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
188#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
189#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
190#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
191#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
192#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
194#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
195#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
196#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
197#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
198#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
199#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
200#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
201#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
202#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
203#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
204#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
205#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
206#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
207#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
208#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
209#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
210#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
211#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
212#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
213#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
214#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
215#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
216#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
217#define INT_SOFTINT MX1_INT_SOFTINT
218#define CSI_INT MX1_CSI_INT
219#define DSPA_MAC_INT MX1_DSPA_MAC_INT
220#define DSPA_INT MX1_DSPA_INT
221#define COMP_INT MX1_COMP_INT
222#define MSHC_XINT MX1_MSHC_XINT
223#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
224#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
225#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
226#define LCDC_INT MX1_LCDC_INT
227#define SIM_INT MX1_SIM_INT
228#define SIM_DATA_INT MX1_SIM_DATA_INT
229#define RTC_INT MX1_RTC_INT
230#define RTC_SAMINT MX1_RTC_SAMINT
231#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
232#define UART2_MINT_RTS MX1_UART2_MINT_RTS
233#define UART2_MINT_DTR MX1_UART2_MINT_DTR
234#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
235#define UART2_MINT_TX MX1_UART2_MINT_TX
236#define UART2_MINT_RX MX1_UART2_MINT_RX
237#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
238#define UART1_MINT_RTS MX1_UART1_MINT_RTS
239#define UART1_MINT_DTR MX1_UART1_MINT_DTR
240#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
241#define UART1_MINT_TX MX1_UART1_MINT_TX
242#define UART1_MINT_RX MX1_UART1_MINT_RX
243#define VOICE_DAC_INT MX1_VOICE_DAC_INT
244#define VOICE_ADC_INT MX1_VOICE_ADC_INT
245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_INT_I2C
249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
252#define SSI_RX_INT MX1_SSI_RX_INT
253#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
254#define TOUCH_INT MX1_TOUCH_INT
255#define USBD_INT1 MX1_USBD_INT1
256#define USBD_INT2 MX1_USBD_INT2
257#define USBD_INT3 MX1_USBD_INT3
258#define USBD_INT4 MX1_USBD_INT4
259#define USBD_INT5 MX1_USBD_INT5
260#define USBD_INT6 MX1_USBD_INT6
261#define BTSYS_INT MX1_BTSYS_INT
262#define BTTIM_INT MX1_BTTIM_INT
263#define BTWUI_INT MX1_BTWUI_INT
264#define TIM2_INT MX1_TIM2_INT
265#define TIM1_INT MX1_TIM1_INT
266#define DMA_ERR MX1_DMA_ERR
267#define DMA_INT MX1_DMA_INT
268#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
269#define WDT_INT MX1_WDT_INT
270#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
271#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
272#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
273#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
274#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
275#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
276#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
277#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
278#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
279#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
280#define DMA_REQ_EXT MX1_DMA_REQ_EXT
281#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
282#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
283#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
284#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
285#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
286#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
287#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
288#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
289#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
290#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
291#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
292#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
293#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
294#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
295#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
296 171
297#endif /* ifndef __MACH_MX1_H__ */ 172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8bc59720b6e4..6cd049ebbd8d 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -26,7 +26,6 @@
26#define __MACH_MX21_H__ 26#define __MACH_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000 28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30#define MX21_AIPI_SIZE SZ_1M 29#define MX21_AIPI_SIZE SZ_1M
31#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) 30#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) 31#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
@@ -49,6 +48,12 @@
49#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) 48#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
50#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) 49#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
51#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) 50#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
51#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
52#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
53#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
54#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
55#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
56#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
52#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) 57#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
53#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) 58#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
54#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) 59#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
@@ -64,7 +69,6 @@
64#define MX21_AVIC_BASE_ADDR 0x10040000 69#define MX21_AVIC_BASE_ADDR 0x10040000
65 70
66#define MX21_SAHB1_BASE_ADDR 0x80000000 71#define MX21_SAHB1_BASE_ADDR 0x80000000
67#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68#define MX21_SAHB1_SIZE SZ_1M 72#define MX21_SAHB1_SIZE SZ_1M
69#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 73#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
70 74
@@ -82,7 +86,6 @@
82 86
83/* NAND, SDRAM, WEIM etc controllers */ 87/* NAND, SDRAM, WEIM etc controllers */
84#define MX21_X_MEMC_BASE_ADDR 0xdf000000 88#define MX21_X_MEMC_BASE_ADDR 0xdf000000
85#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
86#define MX21_X_MEMC_SIZE SZ_256K 89#define MX21_X_MEMC_SIZE SZ_256K
87 90
88#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) 91#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +95,8 @@
92 95
93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ 96#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94 97
95#define MX21_IO_ADDRESS(x) ( \ 98#define MX21_IO_P2V(x) IMX_IO_P2V(x)
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ 99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
99 100
100/* fixed interrupt numbers */ 101/* fixed interrupt numbers */
101#define MX21_INT_CSPI3 6 102#define MX21_INT_CSPI3 6
@@ -184,39 +185,4 @@
184#define MX21_DMA_REQ_CSI_STAT 30 185#define MX21_DMA_REQ_CSI_STAT 30
185#define MX21_DMA_REQ_CSI_RX 31 186#define MX21_DMA_REQ_CSI_RX 31
186 187
187#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
188/* these should go away */
189#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
190#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
191#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
192#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
193#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
194#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
195#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
196#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
197#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
198#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
199#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
200#define X_MEMC_SIZE MX21_X_MEMC_SIZE
201#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
202#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
203#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
204#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
205#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
206#define MXC_INT_FIRI MX21_INT_FIRI
207#define MXC_INT_BMI MX21_INT_BMI
208#define MXC_INT_EMMAENC MX21_INT_EMMAENC
209#define MXC_INT_EMMADEC MX21_INT_EMMADEC
210#define MXC_INT_USBWKUP MX21_INT_USBWKUP
211#define MXC_INT_USBDMA MX21_INT_USBDMA
212#define MXC_INT_USBHOST MX21_INT_USBHOST
213#define MXC_INT_USBFUNC MX21_INT_USBFUNC
214#define MXC_INT_USBMNP MX21_INT_USBMNP
215#define MXC_INT_USBCTRL MX21_INT_USBCTRL
216#define MXC_INT_USBCTRL MX21_INT_USBCTRL
217#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
218#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
219#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220#endif
221
222#endif /* ifndef __MACH_MX21_H__ */ 188#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index cf46a45b0d4e..087cd7ac8d52 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -2,13 +2,10 @@
2#define __MACH_MX25_H__ 2#define __MACH_MX25_H__
3 3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000 4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
6#define MX25_AIPS1_SIZE SZ_1M 5#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53f00000 6#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9#define MX25_AIPS2_SIZE SZ_1M 7#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000 8#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 9#define MX25_AVIC_SIZE SZ_1M
13 10
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) 11#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -21,20 +18,15 @@
21 18
22#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
23#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) 20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
24#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) 28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
25 29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
26#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
28#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
29#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
30
31#define MX25_IO_ADDRESS(x) ( \
32 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
33 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
34 IMX_IO_ADDRESS(x, MX25_AVIC))
35
36#define MX25_AIPS1_IO_ADDRESS(x) \
37 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
38 30
39#define MX25_UART1_BASE_ADDR 0x43f90000 31#define MX25_UART1_BASE_ADDR 0x43f90000
40#define MX25_UART2_BASE_ADDR 0x43f94000 32#define MX25_UART2_BASE_ADDR 0x43f94000
@@ -55,9 +47,19 @@
55#define MX25_LCDC_BASE_ADDR 0x53fbc000 47#define MX25_LCDC_BASE_ADDR 0x53fbc000
56#define MX25_KPP_BASE_ADDR 0x43fa8000 48#define MX25_KPP_BASE_ADDR 0x43fa8000
57#define MX25_SDMA_BASE_ADDR 0x53fd4000 49#define MX25_SDMA_BASE_ADDR 0x53fd4000
58#define MX25_OTG_BASE_ADDR 0x53ff4000 50#define MX25_USB_BASE_ADDR 0x53ff4000
51#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
52/*
53 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
54 * for the host controller. Early documentation drafts specified 0x400 and
55 * Freescale internal sources confirm only the latter value to work.
56 */
57#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
59#define MX25_CSI_BASE_ADDR 0x53ff8000 58#define MX25_CSI_BASE_ADDR 0x53ff8000
60 59
60#define MX25_IO_P2V(x) IMX_IO_P2V(x)
61#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
62
61#define MX25_INT_CSPI3 0 63#define MX25_INT_CSPI3 0
62#define MX25_INT_I2C1 3 64#define MX25_INT_I2C1 3
63#define MX25_INT_I2C2 4 65#define MX25_INT_I2C2 4
@@ -69,18 +71,28 @@
69#define MX25_INT_SSI1 12 71#define MX25_INT_SSI1 12
70#define MX25_INT_CSPI2 13 72#define MX25_INT_CSPI2 13
71#define MX25_INT_CSPI1 14 73#define MX25_INT_CSPI1 14
74#define MX25_INT_GPIO3 16
72#define MX25_INT_CSI 17 75#define MX25_INT_CSI 17
73#define MX25_INT_UART3 18 76#define MX25_INT_UART3 18
77#define MX25_INT_GPIO4 23
74#define MX25_INT_KPP 24 78#define MX25_INT_KPP 24
75#define MX25_INT_DRYICE 25 79#define MX25_INT_DRYICE 25
80#define MX25_INT_PWM1 26
76#define MX25_INT_UART2 32 81#define MX25_INT_UART2 32
77#define MX25_INT_NFC 33 82#define MX25_INT_NFC 33
78#define MX25_INT_SDMA 34 83#define MX25_INT_SDMA 34
84#define MX25_INT_USB_HS 35
85#define MX25_INT_PWM2 36
86#define MX25_INT_USB_OTG 37
79#define MX25_INT_LCDC 39 87#define MX25_INT_LCDC 39
80#define MX25_INT_UART5 40 88#define MX25_INT_UART5 40
89#define MX25_INT_PWM3 41
90#define MX25_INT_PWM4 42
81#define MX25_INT_CAN1 43 91#define MX25_INT_CAN1 43
82#define MX25_INT_CAN2 44 92#define MX25_INT_CAN2 44
83#define MX25_INT_UART1 45 93#define MX25_INT_UART1 45
94#define MX25_INT_GPIO2 51
95#define MX25_INT_GPIO1 52
84#define MX25_INT_FEC 57 96#define MX25_INT_FEC 57
85 97
86#define MX25_DMA_REQ_SSI2_RX1 22 98#define MX25_DMA_REQ_SSI2_RX1 22
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 2237ba2e5351..cbc43ad5ef48 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -29,7 +29,6 @@
29#endif 29#endif
30 30
31#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
33#define MX27_AIPI_SIZE SZ_1M 32#define MX27_AIPI_SIZE SZ_1M
34#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) 33#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
35#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) 34#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
@@ -52,6 +51,12 @@
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 51#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 52#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 53#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
54#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
55#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
56#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
57#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
58#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
59#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
55#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) 60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
56#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) 61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
57#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) 62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
@@ -65,11 +70,13 @@
65#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) 70#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
66#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) 71#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
67#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) 72#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
68#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) 73#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
69#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR 74#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
75#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
76#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
70#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) 77#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
71#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) 78#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
72#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) 79#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
73#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) 80#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
74#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) 81#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
75#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) 82#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
@@ -87,7 +94,6 @@
87#define MX27_ROMP_BASE_ADDR 0x10041000 94#define MX27_ROMP_BASE_ADDR 0x10041000
88 95
89#define MX27_SAHB1_BASE_ADDR 0x80000000 96#define MX27_SAHB1_BASE_ADDR 0x80000000
90#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
91#define MX27_SAHB1_SIZE SZ_1M 97#define MX27_SAHB1_SIZE SZ_1M
92#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) 98#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
93#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) 99#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +111,6 @@
105 111
106/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 112/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
107#define MX27_X_MEMC_BASE_ADDR 0xd8000000 113#define MX27_X_MEMC_BASE_ADDR 0xd8000000
108#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
109#define MX27_X_MEMC_SIZE SZ_1M 114#define MX27_X_MEMC_SIZE SZ_1M
110#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) 115#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) 116#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +128,8 @@
123/* IRAM */ 128/* IRAM */
124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 129#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
125 130
126#define MX27_IO_ADDRESS(x) ( \ 131#define MX27_IO_P2V(x) IMX_IO_P2V(x)
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ 132#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130 133
131#ifndef __ASSEMBLER__ 134#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs, 135static inline void mx27_setup_weimcs(size_t cs,
@@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs,
192#define MX27_INT_EMMAPRP 51 195#define MX27_INT_EMMAPRP 51
193#define MX27_INT_EMMAPP 52 196#define MX27_INT_EMMAPP 52
194#define MX27_INT_VPU 53 197#define MX27_INT_VPU 53
195#define MX27_INT_USB1 54 198#define MX27_INT_USB_HS1 54
196#define MX27_INT_USB2 55 199#define MX27_INT_USB_HS2 55
197#define MX27_INT_USB3 56 200#define MX27_INT_USB_OTG 56
198#define MX27_INT_SCC_SMN 57 201#define MX27_INT_SCC_SMN 57
199#define MX27_INT_SCC_SCM 58 202#define MX27_INT_SCC_SCM 58
200#define MX27_INT_SAHARA 59 203#define MX27_INT_SAHARA 59
@@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs,
241#define MX27_DMA_REQ_SDHC3 36 244#define MX27_DMA_REQ_SDHC3 36
242#define MX27_DMA_REQ_NFC 37 245#define MX27_DMA_REQ_NFC 37
243 246
244/* silicon revisions specific to i.MX27 */
245#define CHIP_REV_1_0 0x00
246#define CHIP_REV_2_0 0x01
247
248#ifndef __ASSEMBLY__ 247#ifndef __ASSEMBLY__
249extern int mx27_revision(void); 248extern int mx27_revision(void);
250#endif 249#endif
251 250
252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
253/* these should go away */
254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
256#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
257#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
258#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
259#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
260#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
261#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
262#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
263#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
264#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
265#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
266#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
267#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
268#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
269#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
270#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
271#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
272#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
273#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
274#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
275#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
276#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
277#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
278#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
279#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
280#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
281#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
282#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
283#define X_MEMC_SIZE MX27_X_MEMC_SIZE
284#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
285#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
286#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
287#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
288#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
289#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
290#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
291#define MXC_INT_I2C2 MX27_INT_I2C2
292#define MXC_INT_GPT6 MX27_INT_GPT6
293#define MXC_INT_GPT5 MX27_INT_GPT5
294#define MXC_INT_GPT4 MX27_INT_GPT4
295#define MXC_INT_RTIC MX27_INT_RTIC
296#define MXC_INT_SDHC MX27_INT_SDHC
297#define MXC_INT_SDHC3 MX27_INT_SDHC3
298#define MXC_INT_ATA MX27_INT_ATA
299#define MXC_INT_UART6 MX27_INT_UART6
300#define MXC_INT_UART5 MX27_INT_UART5
301#define MXC_INT_FEC MX27_INT_FEC
302#define MXC_INT_VPU MX27_INT_VPU
303#define MXC_INT_USB1 MX27_INT_USB1
304#define MXC_INT_USB2 MX27_INT_USB2
305#define MXC_INT_USB3 MX27_INT_USB3
306#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
307#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
308#define MXC_INT_SAHARA MX27_INT_SAHARA
309#define MXC_INT_IIM MX27_INT_IIM
310#define MXC_INT_CCM MX27_INT_CCM
311#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
312#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
313#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
314#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
315#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
316#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
321
322#endif /* ifndef __MACH_MX27_H__ */ 251#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index afb895a0b5b8..6d07839fdec2 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -27,7 +27,6 @@
27 27
28/* Register offsets */ 28/* Register offsets */
29#define MX2x_AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
31#define MX2x_AIPI_SIZE SZ_1M 30#define MX2x_AIPI_SIZE SZ_1M
32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 31#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 32#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
@@ -65,43 +64,9 @@
65#define MX2x_AVIC_BASE_ADDR 0x10040000 64#define MX2x_AVIC_BASE_ADDR 0x10040000
66 65
67#define MX2x_SAHB1_BASE_ADDR 0x80000000 66#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define MX2x_SAHB1_SIZE SZ_1M 67#define MX2x_SAHB1_SIZE SZ_1M
70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71 69
72/*
73 * This macro defines the physical to virtual address mapping for all the
74 * peripheral modules. It is used by passing in the physical address as x
75 * and returning the virtual address. If the physical address is not mapped,
76 * it returns 0xDEADBEEF
77 */
78#define IO_ADDRESS(x) \
79 (void __force __iomem *) \
80 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
81 AIPI_IO_ADDRESS(x) : \
82 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
83 SAHB1_IO_ADDRESS(x) : \
84 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
85 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
86
87/* define the address mapping macros: in physical address order */
88#define AIPI_IO_ADDRESS(x) \
89 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
90
91#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
92
93#define SAHB1_IO_ADDRESS(x) \
94 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
95
96#define CS4_IO_ADDRESS(x) \
97 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
98
99#define X_MEMC_IO_ADDRESS(x) \
100 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
101
102#define PCMCIA_IO_ADDRESS(x) \
103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
104
105/* fixed interrupt numbers */ 70/* fixed interrupt numbers */
106#define MX2x_INT_CSPI3 6 71#define MX2x_INT_CSPI3 6
107#define MX2x_INT_GPIO 8 72#define MX2x_INT_GPIO 8
@@ -176,118 +141,4 @@
176#define MX2x_DMA_REQ_CSI_STAT 30 141#define MX2x_DMA_REQ_CSI_STAT 30
177#define MX2x_DMA_REQ_CSI_RX 31 142#define MX2x_DMA_REQ_CSI_RX 31
178 143
179#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
180/* these should go away */
181#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
182#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
183#define AIPI_SIZE MX2x_AIPI_SIZE
184#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
185#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
186#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
187#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
188#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
189#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
190#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
191#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
192#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
193#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
194#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
195#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
196#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
197#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
198#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
199#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
200#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
201#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
202#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
203#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
204#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
205#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
206#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
207#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
208#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
209#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
210#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
211#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
212#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
213#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
214#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
215#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
216#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
217#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
218#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
219#define SAHB1_SIZE MX2x_SAHB1_SIZE
220#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
221#define MXC_INT_CSPI3 MX2x_INT_CSPI3
222#define MXC_INT_GPIO MX2x_INT_GPIO
223#define MXC_INT_SDHC2 MX2x_INT_SDHC2
224#define MXC_INT_SDHC1 MX2x_INT_SDHC1
225#define MXC_INT_I2C MX2x_INT_I2C
226#define MXC_INT_SSI2 MX2x_INT_SSI2
227#define MXC_INT_SSI1 MX2x_INT_SSI1
228#define MXC_INT_CSPI2 MX2x_INT_CSPI2
229#define MXC_INT_CSPI1 MX2x_INT_CSPI1
230#define MXC_INT_UART4 MX2x_INT_UART4
231#define MXC_INT_UART3 MX2x_INT_UART3
232#define MXC_INT_UART2 MX2x_INT_UART2
233#define MXC_INT_UART1 MX2x_INT_UART1
234#define MXC_INT_KPP MX2x_INT_KPP
235#define MXC_INT_RTC MX2x_INT_RTC
236#define MXC_INT_PWM MX2x_INT_PWM
237#define MXC_INT_GPT3 MX2x_INT_GPT3
238#define MXC_INT_GPT2 MX2x_INT_GPT2
239#define MXC_INT_GPT1 MX2x_INT_GPT1
240#define MXC_INT_WDOG MX2x_INT_WDOG
241#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
242#define MXC_INT_NANDFC MX2x_INT_NANDFC
243#define MXC_INT_CSI MX2x_INT_CSI
244#define MXC_INT_DMACH0 MX2x_INT_DMACH0
245#define MXC_INT_DMACH1 MX2x_INT_DMACH1
246#define MXC_INT_DMACH2 MX2x_INT_DMACH2
247#define MXC_INT_DMACH3 MX2x_INT_DMACH3
248#define MXC_INT_DMACH4 MX2x_INT_DMACH4
249#define MXC_INT_DMACH5 MX2x_INT_DMACH5
250#define MXC_INT_DMACH6 MX2x_INT_DMACH6
251#define MXC_INT_DMACH7 MX2x_INT_DMACH7
252#define MXC_INT_DMACH8 MX2x_INT_DMACH8
253#define MXC_INT_DMACH9 MX2x_INT_DMACH9
254#define MXC_INT_DMACH10 MX2x_INT_DMACH10
255#define MXC_INT_DMACH11 MX2x_INT_DMACH11
256#define MXC_INT_DMACH12 MX2x_INT_DMACH12
257#define MXC_INT_DMACH13 MX2x_INT_DMACH13
258#define MXC_INT_DMACH14 MX2x_INT_DMACH14
259#define MXC_INT_DMACH15 MX2x_INT_DMACH15
260#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
261#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
262#define MXC_INT_SLCDC MX2x_INT_SLCDC
263#define MXC_INT_LCDC MX2x_INT_LCDC
264#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
265#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
266#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
267#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
268#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
269#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
270#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
271#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
272#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
273#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
274#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
275#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
276#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
277#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
278#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
279#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
280#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
281#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
282#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
283#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
284#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
285#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
286#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
287#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
288#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
289#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
290#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
291#endif
292
293#endif /* ifndef __MACH_MX2x_H__ */ 144#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 61cfe827498b..79e7fc01bb59 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -15,7 +15,6 @@
15#define MX31_L2CC_SIZE SZ_1M 15#define MX31_L2CC_SIZE SZ_1M
16 16
17#define MX31_AIPS1_BASE_ADDR 0x43f00000 17#define MX31_AIPS1_BASE_ADDR 0x43f00000
18#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
19#define MX31_AIPS1_SIZE SZ_1M 18#define MX31_AIPS1_SIZE SZ_1M
20#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) 19#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
21#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) 20#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -25,7 +24,10 @@
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) 24#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) 25#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) 26#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) 27#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
28#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
29#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
30#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) 31#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
30#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) 32#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
31#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) 33#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
@@ -41,10 +43,9 @@
41#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) 43#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
42 44
43#define MX31_SPBA0_BASE_ADDR 0x50000000 45#define MX31_SPBA0_BASE_ADDR 0x50000000
44#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
45#define MX31_SPBA0_SIZE SZ_1M 46#define MX31_SPBA0_SIZE SZ_1M
46#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) 47#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
47#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) 48#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
48#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) 49#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
49#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) 50#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
50#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) 51#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
@@ -55,7 +56,6 @@
55#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) 56#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
56 57
57#define MX31_AIPS2_BASE_ADDR 0x53f00000 58#define MX31_AIPS2_BASE_ADDR 0x53f00000
58#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
59#define MX31_AIPS2_SIZE SZ_1M 59#define MX31_AIPS2_SIZE SZ_1M
60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) 60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) 61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +84,6 @@
84#define MX31_ROMP_SIZE SZ_1M 84#define MX31_ROMP_SIZE SZ_1M
85 85
86#define MX31_AVIC_BASE_ADDR 0x68000000 86#define MX31_AVIC_BASE_ADDR 0x68000000
87#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
88#define MX31_AVIC_SIZE SZ_1M 87#define MX31_AVIC_SIZE SZ_1M
89 88
90#define MX31_IPU_MEM_BASE_ADDR 0x70000000 89#define MX31_IPU_MEM_BASE_ADDR 0x70000000
@@ -97,15 +96,14 @@
97#define MX31_CS3_BASE_ADDR 0xb2000000 96#define MX31_CS3_BASE_ADDR 0xb2000000
98 97
99#define MX31_CS4_BASE_ADDR 0xb4000000 98#define MX31_CS4_BASE_ADDR 0xb4000000
100#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 99#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
101#define MX31_CS4_SIZE SZ_32M 100#define MX31_CS4_SIZE SZ_32M
102 101
103#define MX31_CS5_BASE_ADDR 0xb6000000 102#define MX31_CS5_BASE_ADDR 0xb6000000
104#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 103#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
105#define MX31_CS5_SIZE SZ_32M 104#define MX31_CS5_SIZE SZ_32M
106 105
107#define MX31_X_MEMC_BASE_ADDR 0xb8000000 106#define MX31_X_MEMC_BASE_ADDR 0xb8000000
108#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109#define MX31_X_MEMC_SIZE SZ_64K 107#define MX31_X_MEMC_SIZE SZ_64K
110#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) 108#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) 109#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +119,8 @@
121 119
122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 120#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
123 121
124#define MX31_IO_ADDRESS(x) ( \ 122#define MX31_IO_P2V(x) IMX_IO_P2V(x)
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ 123#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
130 124
131#ifndef __ASSEMBLER__ 125#ifndef __ASSEMBLER__
132static inline void mx31_setup_weimcs(size_t cs, 126static inline void mx31_setup_weimcs(size_t cs,
@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs,
143#define MX31_INT_MPEG4_ENCODER 5 137#define MX31_INT_MPEG4_ENCODER 5
144#define MX31_INT_RTIC 6 138#define MX31_INT_RTIC 6
145#define MX31_INT_FIRI 7 139#define MX31_INT_FIRI 7
146#define MX31_INT_MMC_SDHC2 8 140#define MX31_INT_SDHC2 8
147#define MX31_INT_MMC_SDHC1 9 141#define MX31_INT_SDHC1 9
148#define MX31_INT_I2C1 10 142#define MX31_INT_I2C1 10
149#define MX31_INT_SSI2 11 143#define MX31_INT_SSI2 11
150#define MX31_INT_SSI1 12 144#define MX31_INT_SSI1 12
@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs,
170#define MX31_INT_UART2 32 164#define MX31_INT_UART2 32
171#define MX31_INT_NFC 33 165#define MX31_INT_NFC 33
172#define MX31_INT_SDMA 34 166#define MX31_INT_SDMA 34
173#define MX31_INT_USB1 35 167#define MX31_INT_USB_HS1 35
174#define MX31_INT_USB2 36 168#define MX31_INT_USB_HS2 36
175#define MX31_INT_USB3 37 169#define MX31_INT_USB_OTG 37
176#define MX31_INT_USB4 38
177#define MX31_INT_MSHC1 39 170#define MX31_INT_MSHC1 39
178#define MX31_INT_MSHC2 40 171#define MX31_INT_MSHC2 40
179#define MX31_INT_IPU_ERR 41 172#define MX31_INT_IPU_ERR 41
@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs,
197#define MX31_INT_EXT_WDOG 62 190#define MX31_INT_EXT_WDOG 62
198#define MX31_INT_EXT_TV 63 191#define MX31_INT_EXT_TV 63
199 192
193#define MX31_DMA_REQ_SDHC1 20
194#define MX31_DMA_REQ_SDHC2 21
200#define MX31_DMA_REQ_SSI2_RX1 22 195#define MX31_DMA_REQ_SSI2_RX1 22
201#define MX31_DMA_REQ_SSI2_TX1 23 196#define MX31_DMA_REQ_SSI2_TX1 23
202#define MX31_DMA_REQ_SSI2_RX0 24 197#define MX31_DMA_REQ_SSI2_RX0 24
@@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs,
208 203
209#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ 204#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
210 205
211/* silicon revisions specific to i.MX31 */
212#define MX31_CHIP_REV_1_0 0x10
213#define MX31_CHIP_REV_1_1 0x11
214#define MX31_CHIP_REV_1_2 0x12
215#define MX31_CHIP_REV_1_3 0x13
216#define MX31_CHIP_REV_2_0 0x20
217#define MX31_CHIP_REV_2_1 0x21
218#define MX31_CHIP_REV_2_2 0x22
219#define MX31_CHIP_REV_2_3 0x23
220#define MX31_CHIP_REV_3_0 0x30
221#define MX31_CHIP_REV_3_1 0x31
222#define MX31_CHIP_REV_3_2 0x32
223
224#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
225#define MX31_SYSTEM_REV_NUM 3
226
227#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
228/* these should go away */
229#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
230#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
231#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
232#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
233#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
234#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
235#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
236#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
237#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
238#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
239#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
240#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
241#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
242#define MXC_INT_FIRI MX31_INT_FIRI
243#define MXC_INT_MBX MX31_INT_MBX
244#define MXC_INT_CSPI3 MX31_INT_CSPI3
245#define MXC_INT_SIM2 MX31_INT_SIM2
246#define MXC_INT_SIM1 MX31_INT_SIM1
247#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
248#define MXC_INT_USB1 MX31_INT_USB1
249#define MXC_INT_USB2 MX31_INT_USB2
250#define MXC_INT_USB3 MX31_INT_USB3
251#define MXC_INT_USB4 MX31_INT_USB4
252#define MXC_INT_MSHC2 MX31_INT_MSHC2
253#define MXC_INT_UART4 MX31_INT_UART4
254#define MXC_INT_UART5 MX31_INT_UART5
255#define MXC_INT_CCM MX31_INT_CCM
256#define MXC_INT_PCMCIA MX31_INT_PCMCIA
257#endif
258
259#endif /* ifndef __MACH_MX31_H__ */ 206#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6267cff6035d..d13dbfeef08a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -11,7 +11,6 @@
11#define MX35_L2CC_SIZE SZ_1M 11#define MX35_L2CC_SIZE SZ_1M
12 12
13#define MX35_AIPS1_BASE_ADDR 0x43f00000 13#define MX35_AIPS1_BASE_ADDR 0x43f00000
14#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
15#define MX35_AIPS1_SIZE SZ_1M 14#define MX35_AIPS1_SIZE SZ_1M
16#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) 15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
17#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) 16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
@@ -33,7 +32,6 @@
33#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) 32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
34 33
35#define MX35_SPBA0_BASE_ADDR 0x50000000 34#define MX35_SPBA0_BASE_ADDR 0x50000000
36#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
37#define MX35_SPBA0_SIZE SZ_1M 35#define MX35_SPBA0_SIZE SZ_1M
38#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) 36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
39#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) 37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
@@ -44,7 +42,6 @@
44#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) 42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
45 43
46#define MX35_AIPS2_BASE_ADDR 0x53f00000 44#define MX35_AIPS2_BASE_ADDR 0x53f00000
47#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
48#define MX35_AIPS2_SIZE SZ_1M 45#define MX35_AIPS2_SIZE SZ_1M
49#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) 46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
50#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) 47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
@@ -68,15 +65,19 @@
68#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) 65#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
69#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) 66#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
70#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) 67#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
71 68#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
72#define MX35_OTG_BASE_ADDR 0x53ff4000 69#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
70/*
71 * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
72 * HS. When host support was implemented only a preliminary document was
73 * available, which told 0x400. This works fine.
74 */
75#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
73 76
74#define MX35_ROMP_BASE_ADDR 0x60000000 77#define MX35_ROMP_BASE_ADDR 0x60000000
75#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
76#define MX35_ROMP_SIZE SZ_1M 78#define MX35_ROMP_SIZE SZ_1M
77 79
78#define MX35_AVIC_BASE_ADDR 0x68000000 80#define MX35_AVIC_BASE_ADDR 0x68000000
79#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
80#define MX35_AVIC_SIZE SZ_1M 81#define MX35_AVIC_SIZE SZ_1M
81 82
82/* 83/*
@@ -92,18 +93,17 @@
92#define MX35_CS3_BASE_ADDR 0xb2000000 93#define MX35_CS3_BASE_ADDR 0xb2000000
93 94
94#define MX35_CS4_BASE_ADDR 0xb4000000 95#define MX35_CS4_BASE_ADDR 0xb4000000
95#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 96#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
96#define MX35_CS4_SIZE SZ_32M 97#define MX35_CS4_SIZE SZ_32M
97 98
98#define MX35_CS5_BASE_ADDR 0xb6000000 99#define MX35_CS5_BASE_ADDR 0xb6000000
99#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 100#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
100#define MX35_CS5_SIZE SZ_32M 101#define MX35_CS5_SIZE SZ_32M
101 102
102/* 103/*
103 * NAND, SDRAM, WEIM, M3IF, EMI controllers 104 * NAND, SDRAM, WEIM, M3IF, EMI controllers
104 */ 105 */
105#define MX35_X_MEMC_BASE_ADDR 0xb8000000 106#define MX35_X_MEMC_BASE_ADDR 0xb8000000
106#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
107#define MX35_X_MEMC_SIZE SZ_64K 107#define MX35_X_MEMC_SIZE SZ_64K
108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) 108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) 109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
@@ -114,12 +114,8 @@
114#define MX35_NFC_BASE_ADDR 0xbb000000 114#define MX35_NFC_BASE_ADDR 0xbb000000
115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
116 116
117#define MX35_IO_ADDRESS(x) ( \ 117#define MX35_IO_P2V(x) IMX_IO_P2V(x)
118 IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ 118#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
119 IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
120 IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
121 IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
122 IMX_IO_ADDRESS(x, MX35_SPBA0))
123 119
124/* 120/*
125 * Interrupt numbers 121 * Interrupt numbers
@@ -153,8 +149,8 @@
153#define MX35_INT_UART2 32 149#define MX35_INT_UART2 32
154#define MX35_INT_NFC 33 150#define MX35_INT_NFC 33
155#define MX35_INT_SDMA 34 151#define MX35_INT_SDMA 34
156#define MX35_INT_USBHS 35 152#define MX35_INT_USB_HS 35
157#define MX35_INT_USBOTG 37 153#define MX35_INT_USB_OTG 37
158#define MX35_INT_MSHC1 39 154#define MX35_INT_MSHC1 39
159#define MX35_INT_ESAI 40 155#define MX35_INT_ESAI 40
160#define MX35_INT_IPU_ERR 41 156#define MX35_INT_IPU_ERR 41
@@ -190,23 +186,4 @@
190 186
191#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ 187#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
192 188
193#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
194#define MX35_SYSTEM_REV_NUM 3
195
196#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
197/* these should go away */
198#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
199#define MXC_INT_OWIRE MX35_INT_OWIRE
200#define MXC_INT_GPU2D MX35_INT_GPU2D
201#define MXC_INT_ASRC MX35_INT_ASRC
202#define MXC_INT_USBHS MX35_INT_USBHS
203#define MXC_INT_USBOTG MX35_INT_USBOTG
204#define MXC_INT_ESAI MX35_INT_ESAI
205#define MXC_INT_CAN1 MX35_INT_CAN1
206#define MXC_INT_CAN2 MX35_INT_CAN2
207#define MXC_INT_MLB MX35_INT_MLB
208#define MXC_INT_SPDIF MX35_INT_SPDIF
209#define MXC_INT_FEC MX35_INT_FEC
210#endif
211
212#endif /* ifndef __MACH_MX35_H__ */ 189#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index d1bd26d7b8a6..388a407d72d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -44,7 +44,6 @@
44 * AIPS 1 44 * AIPS 1
45 */ 45 */
46#define MX3x_AIPS1_BASE_ADDR 0x43f00000 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
48#define MX3x_AIPS1_SIZE SZ_1M 47#define MX3x_AIPS1_SIZE SZ_1M
49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 48#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 49#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
@@ -69,7 +68,6 @@
69 * SPBA global module enabled #0 68 * SPBA global module enabled #0
70 */ 69 */
71#define MX3x_SPBA0_BASE_ADDR 0x50000000 70#define MX3x_SPBA0_BASE_ADDR 0x50000000
72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
73#define MX3x_SPBA0_SIZE SZ_1M 71#define MX3x_SPBA0_SIZE SZ_1M
74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 72#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 73#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
@@ -82,7 +80,6 @@
82 * AIPS 2 80 * AIPS 2
83 */ 81 */
84#define MX3x_AIPS2_BASE_ADDR 0x53f00000 82#define MX3x_AIPS2_BASE_ADDR 0x53f00000
85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
86#define MX3x_AIPS2_SIZE SZ_1M 83#define MX3x_AIPS2_SIZE SZ_1M
87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 84#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 85#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
@@ -105,11 +102,9 @@
105 * ROMP and AVIC 102 * ROMP and AVIC
106 */ 103 */
107#define MX3x_ROMP_BASE_ADDR 0x60000000 104#define MX3x_ROMP_BASE_ADDR 0x60000000
108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
109#define MX3x_ROMP_SIZE SZ_1M 105#define MX3x_ROMP_SIZE SZ_1M
110 106
111#define MX3x_AVIC_BASE_ADDR 0x68000000 107#define MX3x_AVIC_BASE_ADDR 0x68000000
112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
113#define MX3x_AVIC_SIZE SZ_1M 108#define MX3x_AVIC_SIZE SZ_1M
114 109
115/* 110/*
@@ -125,18 +120,17 @@
125#define MX3x_CS3_BASE_ADDR 0xb2000000 120#define MX3x_CS3_BASE_ADDR 0xb2000000
126 121
127#define MX3x_CS4_BASE_ADDR 0xb4000000 122#define MX3x_CS4_BASE_ADDR 0xb4000000
128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 123#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
129#define MX3x_CS4_SIZE SZ_32M 124#define MX3x_CS4_SIZE SZ_32M
130 125
131#define MX3x_CS5_BASE_ADDR 0xb6000000 126#define MX3x_CS5_BASE_ADDR 0xb6000000
132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 127#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
133#define MX3x_CS5_SIZE SZ_32M 128#define MX3x_CS5_SIZE SZ_32M
134 129
135/* 130/*
136 * NAND, SDRAM, WEIM, M3IF, EMI controllers 131 * NAND, SDRAM, WEIM, M3IF, EMI controllers
137 */ 132 */
138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 133#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
140#define MX3x_X_MEMC_SIZE SZ_64K 134#define MX3x_X_MEMC_SIZE SZ_64K
141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 135#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 136#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
@@ -146,56 +140,6 @@
146 140
147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 141#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
148 142
149/*!
150 * This macro defines the physical to virtual address mapping for all the
151 * peripheral modules. It is used by passing in the physical address as x
152 * and returning the virtual address. If the physical address is not mapped,
153 * it returns 0xDEADBEEF
154 */
155#define IO_ADDRESS(x) \
156 (void __force __iomem *) \
157 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
158 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
159 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
160 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
161 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
162 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
163 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
164 0xDEADBEEF)
165
166/*
167 * define the address mapping macros: in physical address order
168 */
169#define L2CC_IO_ADDRESS(x) \
170 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
171
172#define AIPS1_IO_ADDRESS(x) \
173 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
174
175#define SPBA0_IO_ADDRESS(x) \
176 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
177
178#define AIPS2_IO_ADDRESS(x) \
179 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
180
181#define ROMP_IO_ADDRESS(x) \
182 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
183
184#define AVIC_IO_ADDRESS(x) \
185 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
186
187#define CS4_IO_ADDRESS(x) \
188 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
189
190#define CS5_IO_ADDRESS(x) \
191 (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
192
193#define X_MEMC_IO_ADDRESS(x) \
194 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
195
196#define PCMCIA_IO_ADDRESS(x) \
197 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
198
199/* 143/*
200 * Interrupt numbers 144 * Interrupt numbers
201 */ 145 */
@@ -240,22 +184,6 @@
240 184
241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 185#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
242 186
243/* silicon revisions specific to i.MX31 and i.MX35 */
244#define MX3x_CHIP_REV_1_0 0x10
245#define MX3x_CHIP_REV_1_1 0x11
246#define MX3x_CHIP_REV_1_2 0x12
247#define MX3x_CHIP_REV_1_3 0x13
248#define MX3x_CHIP_REV_2_0 0x20
249#define MX3x_CHIP_REV_2_1 0x21
250#define MX3x_CHIP_REV_2_2 0x22
251#define MX3x_CHIP_REV_2_3 0x23
252#define MX3x_CHIP_REV_3_0 0x30
253#define MX3x_CHIP_REV_3_1 0x31
254#define MX3x_CHIP_REV_3_2 0x32
255
256#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
257#define MX3x_SYSTEM_REV_NUM 3
258
259/* Mandatory defines used globally */ 187/* Mandatory defines used globally */
260 188
261#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 189#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
@@ -277,126 +205,4 @@ static inline int mx35_revision(void)
277} 205}
278#endif 206#endif
279 207
280#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
281/* these should go away */
282#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
283#define L2CC_SIZE MX3x_L2CC_SIZE
284#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
285#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
286#define AIPS1_SIZE MX3x_AIPS1_SIZE
287#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
288#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
289#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
290#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
291#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
292#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
293#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
294#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
295#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
296#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
297#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
298#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
299#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
300#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
301#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
302#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
303#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
304#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
305#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
306#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
307#define SPBA0_SIZE MX3x_SPBA0_SIZE
308#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
309#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
310#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
311#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
312#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
313#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
314#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
315#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
316#define AIPS2_SIZE MX3x_AIPS2_SIZE
317#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
318#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
319#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
320#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
321#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
322#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
323#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
324#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
325#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
326#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
327#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
328#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
329#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
330#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
331#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
332#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
333#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
334#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
335#define ROMP_SIZE MX3x_ROMP_SIZE
336#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
337#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
338#define AVIC_SIZE MX3x_AVIC_SIZE
339#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
340#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
341#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
342#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
343#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
344#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
345#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
346#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
347#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
348#define CS4_SIZE MX3x_CS4_SIZE
349#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
350#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
351#define CS5_SIZE MX3x_CS5_SIZE
352#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
353#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
354#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
355#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
356#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
357#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
358#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
359#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
360#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
361#define MXC_INT_I2C3 MX3x_INT_I2C3
362#define MXC_INT_I2C2 MX3x_INT_I2C2
363#define MXC_INT_RTIC MX3x_INT_RTIC
364#define MXC_INT_I2C MX3x_INT_I2C
365#define MXC_INT_CSPI2 MX3x_INT_CSPI2
366#define MXC_INT_CSPI1 MX3x_INT_CSPI1
367#define MXC_INT_ATA MX3x_INT_ATA
368#define MXC_INT_UART3 MX3x_INT_UART3
369#define MXC_INT_IIM MX3x_INT_IIM
370#define MXC_INT_RNGA MX3x_INT_RNGA
371#define MXC_INT_EVTMON MX3x_INT_EVTMON
372#define MXC_INT_KPP MX3x_INT_KPP
373#define MXC_INT_RTC MX3x_INT_RTC
374#define MXC_INT_PWM MX3x_INT_PWM
375#define MXC_INT_EPIT2 MX3x_INT_EPIT2
376#define MXC_INT_EPIT1 MX3x_INT_EPIT1
377#define MXC_INT_GPT MX3x_INT_GPT
378#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
379#define MXC_INT_UART2 MX3x_INT_UART2
380#define MXC_INT_NANDFC MX3x_INT_NANDFC
381#define MXC_INT_SDMA MX3x_INT_SDMA
382#define MXC_INT_MSHC1 MX3x_INT_MSHC1
383#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
384#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
385#define MXC_INT_UART1 MX3x_INT_UART1
386#define MXC_INT_ECT MX3x_INT_ECT
387#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
388#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
389#define MXC_INT_GPIO2 MX3x_INT_GPIO2
390#define MXC_INT_GPIO1 MX3x_INT_GPIO1
391#define MXC_INT_WDOG MX3x_INT_WDOG
392#define MXC_INT_GPIO3 MX3x_INT_GPIO3
393#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
394#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
395#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
396#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
397#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
398#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
399#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
400#endif
401
402#endif /* ifndef __MACH_MX3x_H__ */ 208#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
new file mode 100644
index 000000000000..aaec2a6e7b3a
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -0,0 +1,285 @@
1#ifndef __MACH_MX50_H__
2#define __MACH_MX50_H__
3
4/*
5 * IROM
6 */
7#define MX50_IROM_BASE_ADDR 0x0
8#define MX50_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX50_TZIC_BASE_ADDR 0x0fffc000
12#define MX50_TZIC_SIZE SZ_16K
13
14/*
15 * IRAM
16 */
17#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
18#define MX50_IRAM_PARTITIONS 16
19#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
20
21/*
22 * Databahn
23 */
24#define MX50_DATABAHN_BASE_ADDR 0x14000000
25
26/*
27 * Graphics Memory of GPU
28 */
29#define MX50_GPU2D_BASE_ADDR 0x20000000
30
31#define MX50_DEBUG_BASE_ADDR 0x40000000
32#define MX50_DEBUG_SIZE SZ_1M
33#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
34#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
35#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
36#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
37#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
38#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
39#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
40#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
41
42#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
43#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
44#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
45#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
46#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
47#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
48#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
49#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
50#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
51#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
52#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
53#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
54#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
55#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
56
57/*
58 * SPBA global module enabled #0
59 */
60#define MX50_SPBA0_BASE_ADDR 0x50000000
61#define MX50_SPBA0_SIZE SZ_1M
62
63#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
64#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
65#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
66#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
67#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
68#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
69#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
70
71/*
72 * AIPS 1
73 */
74#define MX50_AIPS1_BASE_ADDR 0x53f00000
75#define MX50_AIPS1_SIZE SZ_1M
76
77#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
78#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
79#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
80#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
81#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
82#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
83#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
84#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
85#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
86#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
87#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
88#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
89#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
90#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
91#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
92#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
93#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
94#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
95#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
96#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
97#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
98#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
99
100#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
101#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
102
103/*
104 * AIPS 2
105 */
106#define MX50_AIPS2_BASE_ADDR 0x63f00000
107#define MX50_AIPS2_SIZE SZ_1M
108
109#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
110#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
111#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
112#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
113#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
114#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
115#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
116#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
117#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
118#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
119#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
120#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
121#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
122#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
123#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
124#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
125#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
126
127/*
128 * Memory regions and CS
129 */
130#define MX50_CSD0_BASE_ADDR 0x70000000
131#define MX50_CSD1_BASE_ADDR 0xb0000000
132#define MX50_CS0_BASE_ADDR 0xf0000000
133
134#define MX50_IO_P2V(x) IMX_IO_P2V(x)
135#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
136
137/*
138 * defines for SPBA modules
139 */
140#define MX50_SPBA_SDHC1 0x04
141#define MX50_SPBA_SDHC2 0x08
142#define MX50_SPBA_UART3 0x0c
143#define MX50_SPBA_CSPI1 0x10
144#define MX50_SPBA_SSI2 0x14
145#define MX50_SPBA_SDHC3 0x20
146#define MX50_SPBA_SDHC4 0x24
147#define MX50_SPBA_SPDIF 0x28
148#define MX50_SPBA_ATA 0x30
149#define MX50_SPBA_SLIM 0x34
150#define MX50_SPBA_HSI2C 0x38
151#define MX50_SPBA_CTRL 0x3c
152
153/*
154 * DMA request assignments
155 */
156#define MX50_DMA_REQ_GPC 1
157#define MX50_DMA_REQ_ATA_UART4_RX 2
158#define MX50_DMA_REQ_ATA_UART4_TX 3
159#define MX50_DMA_REQ_CSPI1_RX 6
160#define MX50_DMA_REQ_CSPI1_TX 7
161#define MX50_DMA_REQ_CSPI2_RX 8
162#define MX50_DMA_REQ_CSPI2_TX 9
163#define MX50_DMA_REQ_I2C3_SDHC3 10
164#define MX50_DMA_REQ_SDHC4 11
165#define MX50_DMA_REQ_UART2_FIRI_RX 12
166#define MX50_DMA_REQ_UART2_FIRI_TX 13
167#define MX50_DMA_REQ_EXT0 14
168#define MX50_DMA_REQ_EXT1 15
169#define MX50_DMA_REQ_UART5_RX 16
170#define MX50_DMA_REQ_UART5_TX 17
171#define MX50_DMA_REQ_UART1_RX 18
172#define MX50_DMA_REQ_UART1_TX 19
173#define MX50_DMA_REQ_I2C1_SDHC1 20
174#define MX50_DMA_REQ_I2C2_SDHC2 21
175#define MX50_DMA_REQ_SSI2_RX2 22
176#define MX50_DMA_REQ_SSI2_TX2 23
177#define MX50_DMA_REQ_SSI2_RX1 24
178#define MX50_DMA_REQ_SSI2_TX1 25
179#define MX50_DMA_REQ_SSI1_RX2 26
180#define MX50_DMA_REQ_SSI1_TX2 27
181#define MX50_DMA_REQ_SSI1_RX1 28
182#define MX50_DMA_REQ_SSI1_TX1 29
183#define MX50_DMA_REQ_CSPI_RX 38
184#define MX50_DMA_REQ_CSPI_TX 39
185#define MX50_DMA_REQ_UART3_RX 42
186#define MX50_DMA_REQ_UART3_TX 43
187
188/*
189 * Interrupt numbers
190 */
191#define MX50_INT_MMC_SDHC1 1
192#define MX50_INT_MMC_SDHC2 2
193#define MX50_INT_MMC_SDHC3 3
194#define MX50_INT_MMC_SDHC4 4
195#define MX50_INT_DAP 5
196#define MX50_INT_SDMA 6
197#define MX50_INT_IOMUX 7
198#define MX50_INT_UART4 13
199#define MX50_INT_USB_H1 14
200#define MX50_INT_USB_OTG 18
201#define MX50_INT_DATABAHN 19
202#define MX50_INT_ELCDIF 20
203#define MX50_INT_EPXP 21
204#define MX50_INT_SRTC_NTZ 24
205#define MX50_INT_SRTC_TZ 25
206#define MX50_INT_EPDC 27
207#define MX50_INT_NIC 28
208#define MX50_INT_SSI1 29
209#define MX50_INT_SSI2 30
210#define MX50_INT_UART1 31
211#define MX50_INT_UART2 32
212#define MX50_INT_UART3 33
213#define MX50_INT_RESV34 34
214#define MX50_INT_RESV35 35
215#define MX50_INT_CSPI1 36
216#define MX50_INT_CSPI2 37
217#define MX50_INT_CSPI 38
218#define MX50_INT_GPT 39
219#define MX50_INT_EPIT1 40
220#define MX50_INT_GPIO1_INT7 42
221#define MX50_INT_GPIO1_INT6 43
222#define MX50_INT_GPIO1_INT5 44
223#define MX50_INT_GPIO1_INT4 45
224#define MX50_INT_GPIO1_INT3 46
225#define MX50_INT_GPIO1_INT2 47
226#define MX50_INT_GPIO1_INT1 48
227#define MX50_INT_GPIO1_INT0 49
228#define MX50_INT_GPIO1_LOW 50
229#define MX50_INT_GPIO1_HIGH 51
230#define MX50_INT_GPIO2_LOW 52
231#define MX50_INT_GPIO2_HIGH 53
232#define MX50_INT_GPIO3_LOW 54
233#define MX50_INT_GPIO3_HIGH 55
234#define MX50_INT_GPIO4_LOW 56
235#define MX50_INT_GPIO4_HIGH 57
236#define MX50_INT_WDOG1 58
237#define MX50_INT_KPP 60
238#define MX50_INT_PWM1 61
239#define MX50_INT_I2C1 62
240#define MX50_INT_I2C2 63
241#define MX50_INT_I2C3 64
242#define MX50_INT_RESV65 65
243#define MX50_INT_DCDC 66
244#define MX50_INT_THERMAL_ALARM 67
245#define MX50_INT_ANA3 68
246#define MX50_INT_ANA4 69
247#define MX50_INT_CCM1 71
248#define MX50_INT_CCM2 72
249#define MX50_INT_GPC1 73
250#define MX50_INT_GPC2 74
251#define MX50_INT_SRC 75
252#define MX50_INT_NM 76
253#define MX50_INT_PMU 77
254#define MX50_INT_CTI_IRQ 78
255#define MX50_INT_CTI1_TG0 79
256#define MX50_INT_CTI1_TG1 80
257#define MX50_INT_GPU2_IRQ 84
258#define MX50_INT_GPU2_BUSY 85
259#define MX50_INT_UART5 86
260#define MX50_INT_FEC 87
261#define MX50_INT_OWIRE 88
262#define MX50_INT_CTI1_TG2 89
263#define MX50_INT_SJC 90
264#define MX50_INT_DCP_CHAN1_3 91
265#define MX50_INT_DCP_CHAN0 92
266#define MX50_INT_PWM2 94
267#define MX50_INT_RNGB 97
268#define MX50_INT_CTI1_TG3 98
269#define MX50_INT_RAWNAND_BCH 100
270#define MX50_INT_RAWNAND_GPMI 102
271#define MX50_INT_GPIO5_LOW 103
272#define MX50_INT_GPIO5_HIGH 104
273#define MX50_INT_GPIO6_LOW 105
274#define MX50_INT_GPIO6_HIGH 106
275#define MX50_INT_MSHC 109
276#define MX50_INT_APBHDMA_CHAN0 110
277#define MX50_INT_APBHDMA_CHAN1 111
278#define MX50_INT_APBHDMA_CHAN2 112
279#define MX50_INT_APBHDMA_CHAN3 113
280#define MX50_INT_APBHDMA_CHAN4 114
281#define MX50_INT_APBHDMA_CHAN5 115
282#define MX50_INT_APBHDMA_CHAN6 116
283#define MX50_INT_APBHDMA_CHAN7 117
284
285#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 2af7a1056fc1..873807f96d70 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -2,31 +2,6 @@
2#define __MACH_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * fa200000 60000000 1M DEBUG
14 * fb100000 70000000 1M SPBA 0
15 * fb000000 73f00000 1M AIPS 1
16 * fb200000 83f00000 1M AIPS 2
17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * a0000000 256M CSD1 SDRAM/DDR
20 * b0000000 128M CS0 Flash
21 * b8000000 128M CS1 Flash
22 * c0000000 128M CS2 Flash
23 * c8000000 64M CS3 Flash
24 * cc000000 32M CS4 SRAM
25 * ce000000 32M CS5 SRAM
26 * cfff0000 64K NFC (NAND Flash AXI)
27 */
28
29/*
30 * IROM 5 * IROM
31 */ 6 */
32#define MX51_IROM_BASE_ADDR 0x0 7#define MX51_IROM_BASE_ADDR 0x0
@@ -36,7 +11,6 @@
36 * IRAM 11 * IRAM
37 */ 12 */
38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ 13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
40#define MX51_IRAM_PARTITIONS 16 14#define MX51_IRAM_PARTITIONS 16
41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
42 16
@@ -45,7 +19,6 @@
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46 20
47#define MX51_DEBUG_BASE_ADDR 0x60000000 21#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M 22#define MX51_DEBUG_SIZE SZ_1M
50 23
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) 24#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
@@ -61,7 +34,6 @@
61 * SPBA global module enabled #0 34 * SPBA global module enabled #0
62 */ 35 */
63#define MX51_SPBA0_BASE_ADDR 0x70000000 36#define MX51_SPBA0_BASE_ADDR 0x70000000
64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M 37#define MX51_SPBA0_SIZE SZ_1M
66 38
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 39#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
@@ -81,7 +53,6 @@
81 * AIPS 1 53 * AIPS 1
82 */ 54 */
83#define MX51_AIPS1_BASE_ADDR 0x73f00000 55#define MX51_AIPS1_BASE_ADDR 0x73f00000
84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
85#define MX51_AIPS1_SIZE SZ_1M 56#define MX51_AIPS1_SIZE SZ_1M
86 57
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) 58#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
@@ -90,7 +61,7 @@
90#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) 61#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
91#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) 62#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
92#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) 63#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
93#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) 64#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
94#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) 65#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
95#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) 66#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
96#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) 67#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
@@ -109,7 +80,6 @@
109 * AIPS 2 80 * AIPS 2
110 */ 81 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000 82#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M 83#define MX51_AIPS2_SIZE SZ_1M
114 84
115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) 85#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
@@ -139,7 +109,7 @@
139#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) 109#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
140#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) 110#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
141#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) 111#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
142#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) 112#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
143#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) 113#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
144#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) 114#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
145#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) 115#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
@@ -163,16 +133,8 @@
163#define MX51_GPU2D_BASE_ADDR 0xd0000000 133#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000 134#define MX51_TZIC_BASE_ADDR 0xe0000000
165 135
166#define MX51_IO_ADDRESS(x) ( \ 136#define MX51_IO_P2V(x) IMX_IO_P2V(x)
167 IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ 137#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
168 IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
169 IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
170 IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
171 IMX_IO_ADDRESS(x, MX51_AIPS2))
172
173/* This is currently used in <mach/debug-macro.S>, but should go away */
174#define MX51_AIPS1_IO_ADDRESS(x) \
175 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
176 138
177/* 139/*
178 * defines for SPBA modules 140 * defines for SPBA modules
@@ -261,9 +223,9 @@
261#define MX51_DMA_REQ_EMI_WR 32 223#define MX51_DMA_REQ_EMI_WR 32
262#define MX51_DMA_REQ_CTI2_1 33 224#define MX51_DMA_REQ_CTI2_1 33
263#define MX51_DMA_REQ_EPIT2 34 225#define MX51_DMA_REQ_EPIT2 34
264#define MX51_DMA_REQ_SSI3_RX2 35 226#define MX51_DMA_REQ_SSI3_RX1 35
265#define MX51_DMA_REQ_IPU 36 227#define MX51_DMA_REQ_IPU 36
266#define MX51_DMA_REQ_SSI3_TX2 37 228#define MX51_DMA_REQ_SSI3_TX1 37
267#define MX51_DMA_REQ_CSPI_RX 38 229#define MX51_DMA_REQ_CSPI_RX 38
268#define MX51_DMA_REQ_CSPI_TX 39 230#define MX51_DMA_REQ_CSPI_TX 39
269#define MX51_DMA_REQ_SDHC3 40 231#define MX51_DMA_REQ_SDHC3 40
@@ -272,8 +234,8 @@
272#define MX51_DMA_REQ_UART3_RX 43 234#define MX51_DMA_REQ_UART3_RX 43
273#define MX51_DMA_REQ_UART3_TX 44 235#define MX51_DMA_REQ_UART3_TX 44
274#define MX51_DMA_REQ_SPDIF 45 236#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_SSI3_RX1 46 237#define MX51_DMA_REQ_SSI3_RX0 46
276#define MX51_DMA_REQ_SSI3_TX1 47 238#define MX51_DMA_REQ_SSI3_TX0 47
277 239
278/* 240/*
279 * Interrupt numbers 241 * Interrupt numbers
@@ -289,8 +251,8 @@
289#define MX51_MXC_INT_IOMUX 7 251#define MX51_MXC_INT_IOMUX 7
290#define MX51_INT_NFC 8 252#define MX51_INT_NFC 8
291#define MX51_MXC_INT_VPU 9 253#define MX51_MXC_INT_VPU 9
292#define MX51_MXC_INT_IPU_ERR 10 254#define MX51_INT_IPU_ERR 10
293#define MX51_MXC_INT_IPU_SYN 11 255#define MX51_INT_IPU_SYN 11
294#define MX51_MXC_INT_GPU 12 256#define MX51_MXC_INT_GPU 12
295#define MX51_MXC_INT_RESV13 13 257#define MX51_MXC_INT_RESV13 13
296#define MX51_MXC_INT_USB_H1 14 258#define MX51_MXC_INT_USB_H1 14
@@ -375,7 +337,7 @@
375#define MX51_MXC_INT_FIRI 93 337#define MX51_MXC_INT_FIRI 93
376#define MX51_MXC_INT_PWM2 94 338#define MX51_MXC_INT_PWM2 94
377#define MX51_MXC_INT_SLIM_EXP 95 339#define MX51_MXC_INT_SLIM_EXP 95
378#define MX51_MXC_INT_SSI3 96 340#define MX51_INT_SSI3 96
379#define MX51_MXC_INT_EMI_BOOT 97 341#define MX51_MXC_INT_EMI_BOOT 97
380#define MX51_MXC_INT_CTI1_TG3 98 342#define MX51_MXC_INT_CTI1_TG3 98
381#define MX51_MXC_INT_SMC_RX 99 343#define MX51_MXC_INT_SMC_RX 99
@@ -383,19 +345,6 @@
383#define MX51_MXC_INT_EMI_NFC 101 345#define MX51_MXC_INT_EMI_NFC 101
384#define MX51_MXC_INT_GPU_IDLE 102 346#define MX51_MXC_INT_GPU_IDLE 102
385 347
386/* silicon revisions specific to i.MX51 */
387#define MX51_CHIP_REV_1_0 0x10
388#define MX51_CHIP_REV_1_1 0x11
389#define MX51_CHIP_REV_1_2 0x12
390#define MX51_CHIP_REV_1_3 0x13
391#define MX51_CHIP_REV_2_0 0x20
392#define MX51_CHIP_REV_2_1 0x21
393#define MX51_CHIP_REV_2_2 0x22
394#define MX51_CHIP_REV_2_3 0x23
395#define MX51_CHIP_REV_3_0 0x30
396#define MX51_CHIP_REV_3_1 0x31
397#define MX51_CHIP_REV_3_2 0x32
398
399#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 348#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
400extern int mx51_revision(void); 349extern int mx51_revision(void);
401#endif 350#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
new file mode 100644
index 000000000000..9577cdbf7fad
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -0,0 +1,353 @@
1#ifndef __MACH_MX53_H__
2#define __MACH_MX53_H__
3
4/*
5 * IROM
6 */
7#define MX53_IROM_BASE_ADDR 0x0
8#define MX53_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX53_TZIC_BASE_ADDR 0x0FFFC000
12
13/*
14 * AHCI SATA
15 */
16#define MX53_SATA_BASE_ADDR 0x10000000
17
18/*
19 * NFC
20 */
21#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
22#define MX53_NFC_AXI_SIZE SZ_64K
23
24/*
25 * IRAM
26 */
27#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
28#define MX53_IRAM_PARTITIONS 16
29#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
30
31/*
32 * Graphics Memory of GPU
33 */
34#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
35#define MX53_GPU2D_BASE_ADDR 0x20000000
36#define MX53_GPU_BASE_ADDR 0x30000000
37#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
38
39#define MX53_DEBUG_BASE_ADDR 0x40000000
40#define MX53_DEBUG_SIZE SZ_1M
41#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
42#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
43#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
44#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
45#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
46#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
47#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
48#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
49
50/*
51 * SPBA global module enabled #0
52 */
53#define MX53_SPBA0_BASE_ADDR 0x50000000
54#define MX53_SPBA0_SIZE SZ_1M
55
56#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
57#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
58#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
59#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
60#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
61#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
62#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
63#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
64#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
65#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
66#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
67#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
68#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
69
70/*
71 * AIPS 1
72 */
73#define MX53_AIPS1_BASE_ADDR 0x53F00000
74#define MX53_AIPS1_SIZE SZ_1M
75
76#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
77#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
78#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
82#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
86#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
87#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
88#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
89#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
90#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
91#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
92#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
93#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
94#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
95#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
96#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
97#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
98#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
99#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
100#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
101#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
102
103/*
104 * AIPS 2
105 */
106#define MX53_AIPS2_BASE_ADDR 0x63F00000
107#define MX53_AIPS2_SIZE SZ_1M
108
109#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
110#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
111#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
112#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
113#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
114#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
115#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
116#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
117#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
118#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
119#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
120#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
121#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
122#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
123#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
124#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
125#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
126#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
127#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
128#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
129#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
130#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
131#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
132#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
133#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
134#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
135#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
136#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
137#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
138#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
139#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
140#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
141#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
142#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
143#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
144
145/*
146 * Memory regions and CS
147 */
148#define MX53_CSD0_BASE_ADDR 0x90000000
149#define MX53_CSD1_BASE_ADDR 0xA0000000
150#define MX53_CS0_BASE_ADDR 0xB0000000
151#define MX53_CS1_BASE_ADDR 0xB8000000
152#define MX53_CS2_BASE_ADDR 0xC0000000
153#define MX53_CS3_BASE_ADDR 0xC8000000
154#define MX53_CS4_BASE_ADDR 0xCC000000
155#define MX53_CS5_BASE_ADDR 0xCE000000
156
157#define MX53_IO_P2V(x) IMX_IO_P2V(x)
158#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
159
160/*
161 * defines for SPBA modules
162 */
163#define MX53_SPBA_SDHC1 0x04
164#define MX53_SPBA_SDHC2 0x08
165#define MX53_SPBA_UART3 0x0C
166#define MX53_SPBA_CSPI1 0x10
167#define MX53_SPBA_SSI2 0x14
168#define MX53_SPBA_SDHC3 0x20
169#define MX53_SPBA_SDHC4 0x24
170#define MX53_SPBA_SPDIF 0x28
171#define MX53_SPBA_ATA 0x30
172#define MX53_SPBA_SLIM 0x34
173#define MX53_SPBA_HSI2C 0x38
174#define MX53_SPBA_CTRL 0x3C
175
176/*
177 * DMA request assignments
178 */
179#define MX53_DMA_REQ_SSI3_TX1 47
180#define MX53_DMA_REQ_SSI3_RX1 46
181#define MX53_DMA_REQ_SSI3_TX2 45
182#define MX53_DMA_REQ_SSI3_RX2 44
183#define MX53_DMA_REQ_UART3_TX 43
184#define MX53_DMA_REQ_UART3_RX 42
185#define MX53_DMA_REQ_ESAI_TX 41
186#define MX53_DMA_REQ_ESAI_RX 40
187#define MX53_DMA_REQ_CSPI_TX 39
188#define MX53_DMA_REQ_CSPI_RX 38
189#define MX53_DMA_REQ_ASRC_DMA6 37
190#define MX53_DMA_REQ_ASRC_DMA5 36
191#define MX53_DMA_REQ_ASRC_DMA4 35
192#define MX53_DMA_REQ_ASRC_DMA3 34
193#define MX53_DMA_REQ_ASRC_DMA2 33
194#define MX53_DMA_REQ_ASRC_DMA1 32
195#define MX53_DMA_REQ_EMI_WR 31
196#define MX53_DMA_REQ_EMI_RD 30
197#define MX53_DMA_REQ_SSI1_TX1 29
198#define MX53_DMA_REQ_SSI1_RX1 28
199#define MX53_DMA_REQ_SSI1_TX2 27
200#define MX53_DMA_REQ_SSI1_RX2 26
201#define MX53_DMA_REQ_SSI2_TX1 25
202#define MX53_DMA_REQ_SSI2_RX1 24
203#define MX53_DMA_REQ_SSI2_TX2 23
204#define MX53_DMA_REQ_SSI2_RX2 22
205#define MX53_DMA_REQ_I2C2_SDHC2 21
206#define MX53_DMA_REQ_I2C1_SDHC1 20
207#define MX53_DMA_REQ_UART1_TX 19
208#define MX53_DMA_REQ_UART1_RX 18
209#define MX53_DMA_REQ_UART5_TX 17
210#define MX53_DMA_REQ_UART5_RX 16
211#define MX53_DMA_REQ_SPDIF_TX 15
212#define MX53_DMA_REQ_SPDIF_RX 14
213#define MX53_DMA_REQ_UART2_FIRI_TX 13
214#define MX53_DMA_REQ_UART2_FIRI_RX 12
215#define MX53_DMA_REQ_SDHC4 11
216#define MX53_DMA_REQ_I2C3_SDHC3 10
217#define MX53_DMA_REQ_CSPI2_TX 9
218#define MX53_DMA_REQ_CSPI2_RX 8
219#define MX53_DMA_REQ_CSPI1_TX 7
220#define MX53_DMA_REQ_CSPI1_RX 6
221#define MX53_DMA_REQ_IPU 5
222#define MX53_DMA_REQ_ATA_TX_END 4
223#define MX53_DMA_REQ_ATA_UART4_TX 3
224#define MX53_DMA_REQ_ATA_UART4_RX 2
225#define MX53_DMA_REQ_GPC 1
226#define MX53_DMA_REQ_VPU 0
227
228/*
229 * Interrupt numbers
230 */
231#define MX53_INT_RESV0 0
232#define MX53_INT_MMC_SDHC1 1
233#define MX53_INT_MMC_SDHC2 2
234#define MX53_INT_MMC_SDHC3 3
235#define MX53_INT_MMC_SDHC4 4
236#define MX53_INT_RESV5 5
237#define MX53_INT_SDMA 6
238#define MX53_INT_IOMUX 7
239#define MX53_INT_NFC 8
240#define MX53_INT_VPU 9
241#define MX53_INT_IPU_ERR 10
242#define MX53_INT_IPU_SYN 11
243#define MX53_INT_GPU 12
244#define MX53_INT_RESV13 13
245#define MX53_INT_USB_H1 14
246#define MX53_INT_EMI 15
247#define MX53_INT_USB_H2 16
248#define MX53_INT_USB_H3 17
249#define MX53_INT_USB_OTG 18
250#define MX53_INT_SAHARA_H0 19
251#define MX53_INT_SAHARA_H1 20
252#define MX53_INT_SCC_SMN 21
253#define MX53_INT_SCC_STZ 22
254#define MX53_INT_SCC_SCM 23
255#define MX53_INT_SRTC_NTZ 24
256#define MX53_INT_SRTC_TZ 25
257#define MX53_INT_RTIC 26
258#define MX53_INT_CSU 27
259#define MX53_INT_SATA 28
260#define MX53_INT_SSI1 29
261#define MX53_INT_SSI2 30
262#define MX53_INT_UART1 31
263#define MX53_INT_UART2 32
264#define MX53_INT_UART3 33
265#define MX53_INT_RESV34 34
266#define MX53_INT_RESV35 35
267#define MX53_INT_CSPI1 36
268#define MX53_INT_CSPI2 37
269#define MX53_INT_CSPI 38
270#define MX53_INT_GPT 39
271#define MX53_INT_EPIT1 40
272#define MX53_INT_EPIT2 41
273#define MX53_INT_GPIO1_INT7 42
274#define MX53_INT_GPIO1_INT6 43
275#define MX53_INT_GPIO1_INT5 44
276#define MX53_INT_GPIO1_INT4 45
277#define MX53_INT_GPIO1_INT3 46
278#define MX53_INT_GPIO1_INT2 47
279#define MX53_INT_GPIO1_INT1 48
280#define MX53_INT_GPIO1_INT0 49
281#define MX53_INT_GPIO1_LOW 50
282#define MX53_INT_GPIO1_HIGH 51
283#define MX53_INT_GPIO2_LOW 52
284#define MX53_INT_GPIO2_HIGH 53
285#define MX53_INT_GPIO3_LOW 54
286#define MX53_INT_GPIO3_HIGH 55
287#define MX53_INT_GPIO4_LOW 56
288#define MX53_INT_GPIO4_HIGH 57
289#define MX53_INT_WDOG1 58
290#define MX53_INT_WDOG2 59
291#define MX53_INT_KPP 60
292#define MX53_INT_PWM1 61
293#define MX53_INT_I2C1 62
294#define MX53_INT_I2C2 63
295#define MX53_INT_I2C3 64
296#define MX53_INT_RESV65 65
297#define MX53_INT_RESV66 66
298#define MX53_INT_SPDIF 67
299#define MX53_INT_SIM_DAT 68
300#define MX53_INT_IIM 69
301#define MX53_INT_ATA 70
302#define MX53_INT_CCM1 71
303#define MX53_INT_CCM2 72
304#define MX53_INT_GPC1 73
305#define MX53_INT_GPC2 74
306#define MX53_INT_SRC 75
307#define MX53_INT_NM 76
308#define MX53_INT_PMU 77
309#define MX53_INT_CTI_IRQ 78
310#define MX53_INT_CTI1_TG0 79
311#define MX53_INT_CTI1_TG1 80
312#define MX53_INT_ESAI 81
313#define MX53_INT_CAN1 82
314#define MX53_INT_CAN2 83
315#define MX53_INT_GPU2_IRQ 84
316#define MX53_INT_GPU2_BUSY 85
317#define MX53_INT_RESV86 86
318#define MX53_INT_FEC 87
319#define MX53_INT_OWIRE 88
320#define MX53_INT_CTI1_TG2 89
321#define MX53_INT_SJC 90
322#define MX53_INT_TVE 92
323#define MX53_INT_FIRI 93
324#define MX53_INT_PWM2 94
325#define MX53_INT_SLIM_EXP 95
326#define MX53_INT_SSI3 96
327#define MX53_INT_EMI_BOOT 97
328#define MX53_INT_CTI1_TG3 98
329#define MX53_INT_SMC_RX 99
330#define MX53_INT_VPU_IDLE 100
331#define MX53_INT_EMI_NFC 101
332#define MX53_INT_GPU_IDLE 102
333#define MX53_INT_GPIO5_LOW 103
334#define MX53_INT_GPIO5_HIGH 104
335#define MX53_INT_GPIO6_LOW 105
336#define MX53_INT_GPIO6_HIGH 106
337#define MX53_INT_GPIO7_LOW 107
338#define MX53_INT_GPIO7_HIGH 108
339
340/* silicon revisions specific to i.MX53 */
341#define MX53_CHIP_REV_1_0 0x10
342#define MX53_CHIP_REV_1_1 0x11
343#define MX53_CHIP_REV_1_2 0x12
344#define MX53_CHIP_REV_1_3 0x13
345#define MX53_CHIP_REV_2_0 0x20
346#define MX53_CHIP_REV_2_1 0x21
347#define MX53_CHIP_REV_2_2 0x22
348#define MX53_CHIP_REV_2_3 0x23
349#define MX53_CHIP_REV_3_0 0x30
350#define MX53_CHIP_REV_3_1 0x31
351#define MX53_CHIP_REV_3_2 0x32
352
353#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a42c7207082d..04c7a26b1f26 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -32,9 +32,25 @@
32#define MXC_CPU_MX27 27 32#define MXC_CPU_MX27 27
33#define MXC_CPU_MX31 31 33#define MXC_CPU_MX31 31
34#define MXC_CPU_MX35 35 34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX50 50
35#define MXC_CPU_MX51 51 36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53
36#define MXC_CPU_MXC91231 91231 38#define MXC_CPU_MXC91231 91231
37 39
40#define IMX_CHIP_REVISION_1_0 0x10
41#define IMX_CHIP_REVISION_1_1 0x11
42#define IMX_CHIP_REVISION_1_2 0x12
43#define IMX_CHIP_REVISION_1_3 0x13
44#define IMX_CHIP_REVISION_2_0 0x20
45#define IMX_CHIP_REVISION_2_1 0x21
46#define IMX_CHIP_REVISION_2_2 0x22
47#define IMX_CHIP_REVISION_2_3 0x23
48#define IMX_CHIP_REVISION_3_0 0x30
49#define IMX_CHIP_REVISION_3_1 0x31
50#define IMX_CHIP_REVISION_3_2 0x32
51#define IMX_CHIP_REVISION_3_3 0x33
52#define IMX_CHIP_REVISION_UNKNOWN 0xff
53
38#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
39extern unsigned int __mxc_cpu_type; 55extern unsigned int __mxc_cpu_type;
40#endif 56#endif
@@ -111,7 +127,19 @@ extern unsigned int __mxc_cpu_type;
111# define cpu_is_mx35() (0) 127# define cpu_is_mx35() (0)
112#endif 128#endif
113 129
114#ifdef CONFIG_ARCH_MX5 130#ifdef CONFIG_ARCH_MX50
131# ifdef mxc_cpu_type
132# undef mxc_cpu_type
133# define mxc_cpu_type __mxc_cpu_type
134# else
135# define mxc_cpu_type MXC_CPU_MX50
136# endif
137# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
138#else
139# define cpu_is_mx50() (0)
140#endif
141
142#ifdef CONFIG_ARCH_MX51
115# ifdef mxc_cpu_type 143# ifdef mxc_cpu_type
116# undef mxc_cpu_type 144# undef mxc_cpu_type
117# define mxc_cpu_type __mxc_cpu_type 145# define mxc_cpu_type __mxc_cpu_type
@@ -123,6 +151,18 @@ extern unsigned int __mxc_cpu_type;
123# define cpu_is_mx51() (0) 151# define cpu_is_mx51() (0)
124#endif 152#endif
125 153
154#ifdef CONFIG_ARCH_MX53
155# ifdef mxc_cpu_type
156# undef mxc_cpu_type
157# define mxc_cpu_type __mxc_cpu_type
158# else
159# define mxc_cpu_type MXC_CPU_MX53
160# endif
161# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
162#else
163# define cpu_is_mx53() (0)
164#endif
165
126#ifdef CONFIG_ARCH_MXC91231 166#ifdef CONFIG_ARCH_MXC91231
127# ifdef mxc_cpu_type 167# ifdef mxc_cpu_type
128# undef mxc_cpu_type 168# undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 0ca3101ebf36..765190fe6332 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -21,14 +21,12 @@
21 * L2CC 21 * L2CC
22 */ 22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000 23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
25#define MXC91231_L2CC_SIZE SZ_64K 24#define MXC91231_L2CC_SIZE SZ_64K
26 25
27/* 26/*
28 * AIPS 1 27 * AIPS 1
29 */ 28 */
30#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
31#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
32#define MXC91231_AIPS1_SIZE SZ_1M 30#define MXC91231_AIPS1_SIZE SZ_1M
33 31
34#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR 32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
@@ -53,7 +51,6 @@
53 * AIPS 2 51 * AIPS 2
54 */ 52 */
55#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
56#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
57#define MXC91231_AIPS2_SIZE SZ_1M 54#define MXC91231_AIPS2_SIZE SZ_1M
58 55
59#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) 56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
@@ -79,7 +76,6 @@
79 * SPBA global module 0 76 * SPBA global module 0
80 */ 77 */
81#define MXC91231_SPBA0_BASE_ADDR 0x50000000 78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
82#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
83#define MXC91231_SPBA0_SIZE SZ_1M 79#define MXC91231_SPBA0_SIZE SZ_1M
84 80
85#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) 81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
@@ -109,7 +105,6 @@
109 * SPBA global module 1 105 * SPBA global module 1
110 */ 106 */
111#define MXC91231_SPBA1_BASE_ADDR 0x52000000 107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
112#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
113#define MXC91231_SPBA1_SIZE SZ_1M 108#define MXC91231_SPBA1_SIZE SZ_1M
114 109
115#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) 110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
@@ -144,18 +139,15 @@
144 * ROMP and AVIC 139 * ROMP and AVIC
145 */ 140 */
146#define MXC91231_ROMP_BASE_ADDR 0x60000000 141#define MXC91231_ROMP_BASE_ADDR 0x60000000
147#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
148#define MXC91231_ROMP_SIZE SZ_64K 142#define MXC91231_ROMP_SIZE SZ_64K
149 143
150#define MXC91231_AVIC_BASE_ADDR 0x68000000 144#define MXC91231_AVIC_BASE_ADDR 0x68000000
151#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
152#define MXC91231_AVIC_SIZE SZ_64K 145#define MXC91231_AVIC_SIZE SZ_64K
153 146
154/* 147/*
155 * NAND, SDRAM, WEIM, M3IF, EMI controllers 148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
156 */ 149 */
157#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
158#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
159#define MXC91231_X_MEMC_SIZE SZ_64K 151#define MXC91231_X_MEMC_SIZE SZ_64K
160 152
161#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) 153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
@@ -183,19 +175,10 @@
183/* 175/*
184 * This macro defines the physical to virtual address mapping for all the 176 * This macro defines the physical to virtual address mapping for all the
185 * peripheral modules. It is used by passing in the physical address as x 177 * peripheral modules. It is used by passing in the physical address as x
186 * and returning the virtual address. If the physical address is not mapped, 178 * and returning the virtual address.
187 * it returns 0.
188 */ 179 */
189 180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
190#define MXC91231_IO_ADDRESS(x) ( \ 181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
191 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
192 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
193 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
194 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
195 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
196 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
197 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
198 IMX_IO_ADDRESS(x, MXC91231_AIPS2))
199 182
200/* 183/*
201 * Interrupt numbers 184 * Interrupt numbers
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 7fc5f9946199..a523a4079299 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -31,6 +31,7 @@
31#define MXC_USBCTRL_OFFSET 0 31#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
34#define MXC_USBH2CTRL_OFFSET 0x14
34 35
35#define MX5_USBOTHER_REGS_OFFSET 0x800 36#define MX5_USBOTHER_REGS_OFFSET 0x800
36 37
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 9be112227ac4..913e0432e40e 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -2,16 +2,62 @@
2#define __MACH_MXC_SDMA_H__ 2#define __MACH_MXC_SDMA_H__
3 3
4/** 4/**
5 * struct sdma_script_start_addrs - SDMA script start pointers
6 *
7 * start addresses of the different functions in the physical
8 * address space of the SDMA engine.
9 */
10struct sdma_script_start_addrs {
11 s32 ap_2_ap_addr;
12 s32 ap_2_bp_addr;
13 s32 ap_2_ap_fixed_addr;
14 s32 bp_2_ap_addr;
15 s32 loopback_on_dsp_side_addr;
16 s32 mcu_interrupt_only_addr;
17 s32 firi_2_per_addr;
18 s32 firi_2_mcu_addr;
19 s32 per_2_firi_addr;
20 s32 mcu_2_firi_addr;
21 s32 uart_2_per_addr;
22 s32 uart_2_mcu_addr;
23 s32 per_2_app_addr;
24 s32 mcu_2_app_addr;
25 s32 per_2_per_addr;
26 s32 uartsh_2_per_addr;
27 s32 uartsh_2_mcu_addr;
28 s32 per_2_shp_addr;
29 s32 mcu_2_shp_addr;
30 s32 ata_2_mcu_addr;
31 s32 mcu_2_ata_addr;
32 s32 app_2_per_addr;
33 s32 app_2_mcu_addr;
34 s32 shp_2_per_addr;
35 s32 shp_2_mcu_addr;
36 s32 mshc_2_mcu_addr;
37 s32 mcu_2_mshc_addr;
38 s32 spdif_2_mcu_addr;
39 s32 mcu_2_spdif_addr;
40 s32 asrc_2_mcu_addr;
41 s32 ext_mem_2_ipu_addr;
42 s32 descrambler_addr;
43 s32 dptc_dvfs_addr;
44 s32 utra_addr;
45 s32 ram_code_start_addr;
46};
47
48/**
5 * struct sdma_platform_data - platform specific data for SDMA engine 49 * struct sdma_platform_data - platform specific data for SDMA engine
6 * 50 *
7 * @sdma_version The version of this SDMA engine 51 * @sdma_version The version of this SDMA engine
8 * @cpu_name used to generate the firmware name 52 * @cpu_name used to generate the firmware name
9 * @to_version CPU Tape out version 53 * @to_version CPU Tape out version
54 * @script_addrs SDMA scripts addresses in SDMA ROM
10 */ 55 */
11struct sdma_platform_data { 56struct sdma_platform_data {
12 int sdma_version; 57 int sdma_version;
13 char *cpu_name; 58 char *cpu_name;
14 int to_version; 59 int to_version;
60 struct sdma_script_start_addrs *script_addrs;
15}; 61};
16 62
17#endif /* __MACH_MXC_SDMA_H__ */ 63#endif /* __MACH_MXC_SDMA_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 9dd9c2085aad..3a70ebf0477f 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -63,6 +63,8 @@ static inline void flush(void)
63#define MX3X_UART1_BASE_ADDR 0x43F90000 63#define MX3X_UART1_BASE_ADDR 0x43F90000
64#define MX3X_UART2_BASE_ADDR 0x43F94000 64#define MX3X_UART2_BASE_ADDR 0x43F94000
65#define MX51_UART1_BASE_ADDR 0x73fbc000 65#define MX51_UART1_BASE_ADDR 0x73fbc000
66#define MX50_UART1_BASE_ADDR 0x53fbc000
67#define MX53_UART1_BASE_ADDR 0x53fbc000
66 68
67static __inline__ void __arch_decomp_setup(unsigned long arch_id) 69static __inline__ void __arch_decomp_setup(unsigned long arch_id)
68{ 70{
@@ -102,6 +104,12 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
102 case MACH_TYPE_EUKREA_CPUIMX51SD: 104 case MACH_TYPE_EUKREA_CPUIMX51SD:
103 uart_base = MX51_UART1_BASE_ADDR; 105 uart_base = MX51_UART1_BASE_ADDR;
104 break; 106 break;
107 case MACH_TYPE_MX50_RDP:
108 uart_base = MX50_UART1_BASE_ADDR;
109 break;
110 case MACH_TYPE_MX53_EVK:
111 uart_base = MX53_UART1_BASE_ADDR;
112 break;
105 default: 113 default:
106 break; 114 break;
107 } 115 }
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index b318c6a222d5..99a9cdb9d6be 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -32,31 +32,38 @@
32static void __iomem *base; 32static void __iomem *base;
33 33
34/* 34/*
35 * setups a single pad in the iomuxer 35 * configures a single pad in the iomuxer
36 */ 36 */
37int mxc_iomux_v3_setup_pad(struct pad_desc *pad) 37int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
38{ 38{
39 if (pad->mux_ctrl_ofs) 39 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
40 __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); 40 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
41 u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
42 u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
43 u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
44 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
41 45
42 if (pad->select_input_ofs) 46 if (mux_ctrl_ofs)
43 __raw_writel(pad->select_input, 47 __raw_writel(mux_mode, base + mux_ctrl_ofs);
44 base + pad->select_input_ofs); 48
49 if (sel_input_ofs)
50 __raw_writel(sel_input, base + sel_input_ofs);
51
52 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
53 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
45 54
46 if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
47 __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
48 return 0; 55 return 0;
49} 56}
50EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); 57EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
51 58
52int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
53{ 60{
54 struct pad_desc *p = pad_list; 61 iomux_v3_cfg_t *p = pad_list;
55 int i; 62 int i;
56 int ret; 63 int ret;
57 64
58 for (i = 0; i < count; i++) { 65 for (i = 0; i < count; i++) {
59 ret = mxc_iomux_v3_setup_pad(p); 66 ret = mxc_iomux_v3_setup_pad(*p);
60 if (ret) 67 if (ret)
61 return ret; 68 return ret;
62 p++; 69 p++;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
new file mode 100644
index 000000000000..0c799ac27730
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/module.h>
20#include <linux/irq.h>
21
22#include "irq-common.h"
23
24int imx_irq_set_priority(unsigned char irq, unsigned char prio)
25{
26 struct mxc_irq_chip *chip;
27 struct irq_chip *base;
28 int ret;
29
30 ret = -ENOSYS;
31
32 base = get_irq_chip(irq);
33 if (base) {
34 chip = container_of(base, struct mxc_irq_chip, base);
35 if (chip->set_priority)
36 ret = chip->set_priority(irq, prio);
37 }
38
39 return ret;
40}
41EXPORT_SYMBOL(imx_irq_set_priority);
42
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{
45 struct mxc_irq_chip *chip;
46 struct irq_chip *base;
47 int ret;
48
49 ret = -ENOSYS;
50
51 base = get_irq_chip(irq);
52 if (base) {
53 chip = container_of(base, struct mxc_irq_chip, base);
54 if (chip->set_irq_fiq)
55 ret = chip->set_irq_fiq(irq, type);
56 }
57
58 return ret;
59}
60EXPORT_SYMBOL(mxc_set_irq_fiq);
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
new file mode 100644
index 000000000000..7203543fb1b3
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __PLAT_MXC_IRQ_COMMON_H__
20#define __PLAT_MXC_IRQ_COMMON_H__
21
22struct mxc_irq_chip
23{
24 struct irq_chip base;
25 int (*set_priority)(unsigned char irq, unsigned char prio);
26 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
27};
28
29#endif
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 925bce4607e7..3455fc0575a6 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -26,6 +26,7 @@
26#include <mach/common.h> 26#include <mach/common.h>
27#include <asm/proc-fns.h> 27#include <asm/proc-fns.h>
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/mach-types.h>
29 30
30static void __iomem *wdog_base; 31static void __iomem *wdog_base;
31 32
@@ -42,12 +43,19 @@ void arch_reset(char mode, const char *cmd)
42 return; 43 return;
43 } 44 }
44#endif 45#endif
46#ifdef CONFIG_MACH_MX51_EFIKAMX
47 if (machine_is_mx51_efikamx()) {
48 mx51_efikamx_reset();
49 return;
50 }
51#endif
52
45 if (cpu_is_mx1()) { 53 if (cpu_is_mx1()) {
46 wcr_enable = (1 << 0); 54 wcr_enable = (1 << 0);
47 } else { 55 } else {
48 struct clk *clk; 56 struct clk *clk;
49 57
50 clk = clk_get_sys("imx-wdt.0", NULL); 58 clk = clk_get_sys("imx2-wdt.0", NULL);
51 if (!IS_ERR(clk)) 59 if (!IS_ERR(clk))
52 clk_enable(clk); 60 clk_enable(clk);
53 wcr_enable = (1 << 2); 61 wcr_enable = (1 << 2);
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 3703ab28257f..e69ed8a8c203 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -21,6 +21,8 @@
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/common.h> 22#include <mach/common.h>
23 23
24#include "irq-common.h"
25
24/* 26/*
25 ***************************************** 27 *****************************************
26 * TZIC Registers * 28 * TZIC Registers *
@@ -47,6 +49,25 @@
47 49
48void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ 50void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
49 51
52#ifdef CONFIG_FIQ
53static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
54{
55 unsigned int index, mask, value;
56
57 index = irq >> 5;
58 if (unlikely(index >= 4))
59 return -EINVAL;
60 mask = 1U << (irq & 0x1F);
61
62 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
63 if (type)
64 value &= ~mask;
65 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
66
67 return 0;
68}
69#endif
70
50/** 71/**
51 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC 72 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
52 * 73 *
@@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
104 return 0; 125 return 0;
105} 126}
106 127
107static struct irq_chip mxc_tzic_chip = { 128static struct mxc_irq_chip mxc_tzic_chip = {
108 .name = "MXC_TZIC", 129 .base = {
109 .ack = tzic_mask_irq, 130 .name = "MXC_TZIC",
110 .mask = tzic_mask_irq, 131 .ack = tzic_mask_irq,
111 .unmask = tzic_unmask_irq, 132 .mask = tzic_mask_irq,
112 .set_wake = tzic_set_wake_irq, 133 .unmask = tzic_unmask_irq,
134 .set_wake = tzic_set_wake_irq,
135 },
136#ifdef CONFIG_FIQ
137 .set_irq_fiq = tzic_set_irq_fiq,
138#endif
113}; 139};
114 140
115/* 141/*
@@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase)
141 /* all IRQ no FIQ Warning :: No selection */ 167 /* all IRQ no FIQ Warning :: No selection */
142 168
143 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
144 set_irq_chip(i, &mxc_tzic_chip); 170 set_irq_chip(i, &mxc_tzic_chip.base);
145 set_irq_handler(i, handle_level_irq); 171 set_irq_handler(i, handle_level_irq);
146 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
147 } 173 }
174
175#ifdef CONFIG_FIQ
176 /* Initialize FIQ */
177 init_FIQ();
178#endif
179
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 180 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149} 181}
150 182
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 03:34:54 -0400