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-rw-r--r--arch/arm/plat-mxc/include/mach/audmux.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31_3ds.h (renamed from arch/arm/plat-mxc/include/mach/board-mx31pdk.h)6
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S14
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S34
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1.h313
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx21.h210
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h82
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx27.h372
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h425
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h112
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h326
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h103
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h25
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h127
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h25
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h54
-rw-r--r--arch/arm/plat-mxc/include/mach/mtd-xip.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h395
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21-usbhost.h38
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h220
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h347
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h351
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h270
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h214
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h424
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h445
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h20
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h58
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h41
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/ssi.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/ulpi.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/vmalloc.h2
46 files changed, 3740 insertions, 1616 deletions
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
new file mode 100644
index 000000000000..5cd6466964af
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -0,0 +1,52 @@
1#ifndef __MACH_AUDMUX_H
2#define __MACH_AUDMUX_H
3
4#define MX27_AUDMUX_HPCR1_SSI0 0
5#define MX27_AUDMUX_HPCR2_SSI1 1
6#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
7#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
8#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
9#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
10
11#define MX31_AUDMUX_PORT1_SSI0 0
12#define MX31_AUDMUX_PORT2_SSI1 1
13#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
14#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
15#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
16#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
17
18/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
19#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
20#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8)
21#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10)
22#define MXC_AUDMUX_V1_PCR_SYN (1 << 12)
23#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
24#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
25#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
26#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25)
27#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
28#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
29#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31)
30
31/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
32#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
33#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
34#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
35#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
36#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
37#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
38#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
39#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
40#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11)
41
42#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
43#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
44#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
45#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
46
47int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
48
49int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
50 unsigned int pdcr);
51
52#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
new file mode 100644
index 000000000000..93cc66f104c7
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
@@ -0,0 +1,39 @@
1/*
2 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
19#define __ARM_ARCH_BOARD_KZM_ARM11_H
20
21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */
24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32
33/*
34 * External UART for touch panel on FPGA
35 */
36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index 2bbd6ed17f50..da92933a233b 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
13 13
14/* Definitions for components on the Debug board */ 14/* Definitions for components on the Debug board */
15 15
@@ -56,4 +56,4 @@
56 56
57#define MXC_MAX_EXP_IO_LINES 16 57#define MXC_MAX_EXP_IO_LINES 16
58 58
59#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ 59#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 2cbfa35e82ff..095a199591c6 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16/* Base address of PBC controller */ 16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */ 18/* Offsets for the PBC Controller register */
19 19
20/* PBC Board status register offset */ 20/* PBC Board status register offset */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 8e64325d6905..2b2da0367578 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -1,15 +1,42 @@
1/* 1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * Based on code for mobots boards,
6 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
3 */ 21 */
4 22
23#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
24#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
25
26#ifndef __ASSEMBLY__
27
28enum mx31lite_boards {
29 MX31LITE_NOBOARD = 0,
30 MX31LITE_DB = 1,
31};
32
5/* 33/*
6 * This program is free software; you can redistribute it and/or modify 34 * This CPU module needs a baseboard to work. After basic initializing
7 * it under the terms of the GNU General Public License version 2 as 35 * its own devices, it calls baseboard's init function.
8 * published by the Free Software Foundation.
9 */ 36 */
10 37
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ 38extern void mx31lite_db_init(void);
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13 39
14#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ 40#endif
15 41
42#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index d5be6b5a6acf..fc5fec9b55f0 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -25,6 +25,7 @@ enum mx31moboard_boards {
25 MX31NOBOARD = 0, 25 MX31NOBOARD = 0,
26 MX31DEVBOARD = 1, 26 MX31DEVBOARD = 1,
27 MX31MARXBOT = 2, 27 MX31MARXBOT = 2,
28 MX31SMARTBOT = 3,
28}; 29};
29 30
30/* 31/*
@@ -34,6 +35,7 @@ enum mx31moboard_boards {
34 35
35extern void mx31moboard_devboard_init(void); 36extern void mx31moboard_devboard_init(void);
36extern void mx31moboard_marxbot_init(void); 37extern void mx31moboard_marxbot_init(void);
38extern void mx31moboard_smartbot_init(void);
37 39
38#endif 40#endif
39 41
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 43a82d0c534d..753a5988d85c 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,13 +26,6 @@
26struct module; 26struct module;
27 27
28struct clk { 28struct clk {
29#ifndef CONFIG_COMMON_CLKDEV
30 /* As soon as i.MX1 and i.MX31 switched to clkdev, this
31 * block can go away */
32 struct list_head node;
33 struct module *owner;
34 const char *name;
35#endif
36 int id; 29 int id;
37 /* Source clock this clk depends on */ 30 /* Source clock this clk depends on */
38 struct clk *parent; 31 struct clk *parent;
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 286cb9b0a25b..2941472582d2 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,22 +20,27 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx51_map_io(void);
23extern void mxc91231_map_io(void); 24extern void mxc91231_map_io(void);
24extern void mxc_init_irq(void __iomem *); 25extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *);
25extern void mx1_init_irq(void); 27extern void mx1_init_irq(void);
26extern void mx21_init_irq(void); 28extern void mx21_init_irq(void);
27extern void mx25_init_irq(void); 29extern void mx25_init_irq(void);
28extern void mx27_init_irq(void); 30extern void mx27_init_irq(void);
29extern void mx31_init_irq(void); 31extern void mx31_init_irq(void);
30extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void);
31extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 36extern int mx1_clocks_init(unsigned long fref);
34extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 37extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
35extern int mx25_clocks_init(unsigned long fref); 38extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 39extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 40extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 41extern int mx35_clocks_init(void);
42extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
43 unsigned long ckih1, unsigned long ckih2);
39extern int mxc91231_clocks_init(unsigned long fref); 44extern int mxc91231_clocks_init(unsigned long fref);
40extern int mxc_register_gpios(void); 45extern int mxc_register_gpios(void);
41extern int mxc_register_device(struct platform_device *pdev, void *data); 46extern int mxc_register_device(struct platform_device *pdev, void *data);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 15b2b148a105..0b6e11eaeb8c 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX_NEEDS_DEPRECATED_SYMBOLS
13 14
14#ifdef CONFIG_ARCH_MX1 15#ifdef CONFIG_ARCH_MX1
15#include <mach/mx1.h> 16#include <mach/mx1.h>
@@ -44,15 +45,24 @@
44#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
45#endif 46#endif
46 47
48#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif
56
47#ifdef CONFIG_ARCH_MXC91231 57#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR 58#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 59#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
50#endif 60#endif
51#include <mach/mxc91231.h> 61#include <mach/mxc91231.h>
52#define UART_PADDR MXC91231_UART2_BASE_ADDR 62#define UART_PADDR MXC91231_UART2_BASE_ADDR
53#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) 63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
54#endif 64#endif
55 .macro addruart,rx 65 .macro addruart, rx, tmp
56 mrc p15, 0, \rx, c1, c0 66 mrc p15, 0, \rx, c1, c0
57 tst \rx, #1 @ MMU enabled? 67 tst \rx, #1 @ MMU enabled?
58 ldreq \rx, =UART_PADDR @ physical 68 ldreq \rx, =UART_PADDR @ physical
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index b3876cc238ca..7c4870bd5a21 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -31,7 +31,13 @@
31#define DMA_MODE_WRITE 1 31#define DMA_MODE_WRITE 1
32#define DMA_MODE_MASK 1 32#define DMA_MODE_MASK 1
33 33
34#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) 34#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
35
36/* DMA Interrupt Mask Register */
37#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
38
39/* Channel Control Register */
40#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
35 41
36#define IMX_DMA_MEMSIZE_32 (0 << 4) 42#define IMX_DMA_MEMSIZE_32 (0 << 4)
37#define IMX_DMA_MEMSIZE_8 (1 << 4) 43#define IMX_DMA_MEMSIZE_8 (1 << 4)
@@ -58,6 +64,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
58 unsigned int dma_length, unsigned int dev_addr, 64 unsigned int dma_length, unsigned int dev_addr,
59 unsigned int dmamode); 65 unsigned int dmamode);
60 66
67
68/*
69 * Use this flag as the dma_length argument to imx_dma_setup_sg()
70 * to create an endless running dma loop. The end of the scatterlist
71 * must be linked to the beginning for this to work.
72 */
73#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
74
61int 75int
62imx_dma_setup_sg(int channel, struct scatterlist *sg, 76imx_dma_setup_sg(int channel, struct scatterlist *sg,
63 unsigned int sgcount, unsigned int dma_length, 77 unsigned int sgcount, unsigned int dma_length,
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 7cf290efe768..aeb08697726b 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 */ 4 */
5 5
6/* 6/*
@@ -18,11 +18,16 @@
18 .endm 18 .endm
19 19
20 .macro get_irqnr_preamble, base, tmp 20 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
21 ldr \base, =avic_base 22 ldr \base, =avic_base
22 ldr \base, [\base] 23 ldr \base, [\base]
23#ifdef CONFIG_MXC_IRQ_PRIOR 24#ifdef CONFIG_MXC_IRQ_PRIOR
24 ldr r4, [\base, #AVIC_NIMASK] 25 ldr r4, [\base, #AVIC_NIMASK]
25#endif 26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
26 .endm 31 .endm
27 32
28 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
@@ -32,6 +37,7 @@
32 @ and returns its number in irqnr 37 @ and returns its number in irqnr
33 @ and returns if an interrupt occured in irqstat 38 @ and returns if an interrupt occured in irqstat
34 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
35 @ Load offset & priority of the highest priority 41 @ Load offset & priority of the highest priority
36 @ interrupt pending from AVIC_NIVECSR 42 @ interrupt pending from AVIC_NIVECSR
37 ldr \irqstat, [\base, #0x40] 43 ldr \irqstat, [\base, #0x40]
@@ -45,6 +51,32 @@
45 strne \tmp, [\base, #AVIC_NIMASK] 51 strne \tmp, [\base, #AVIC_NIMASK]
46 streq r4, [\base, #AVIC_NIMASK] 52 streq r4, [\base, #AVIC_NIMASK]
47#endif 53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0
59 mov \irqstat, #0x0D80
601000:
61 ldr \tmp, [\irqstat, \base]
62 cmp \tmp, #0
63 bne 1001f
64 addeq \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
48 .endm 80 .endm
49 81
50 @ irq priority table (not used) 82 @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 78db75475f69..ebadf4ac43fc 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,6 +22,15 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#define IMX_IO_ADDRESS(addr, module) \
26 ((void __force __iomem *) \
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29
30#ifdef CONFIG_ARCH_MX5
31#include <mach/mx51.h>
32#endif
33
25#ifdef CONFIG_ARCH_MX3 34#ifdef CONFIG_ARCH_MX3
26#include <mach/mx3x.h> 35#include <mach/mx3x.h>
27#include <mach/mx31.h> 36#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
index bf23305c19cc..6b1507cf378e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -1,166 +1,155 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18#ifndef __MACH_IOMUX_MX1_H__
19#define __MACH_IOMUX_MX1_H__
18 20
19#ifndef _MXC_IOMUX_MX1_H 21#include <mach/iomux-v1.h>
20#define _MXC_IOMUX_MX1_H
21 22
22#ifndef GPIO_PORTA 23#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
23#error Please include mach/iomux.h 24#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
24#endif 25#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
26#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
27#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
28#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
29#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
30#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
31#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
32#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
33#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
34#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
35#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
36#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
37#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
38#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
39#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
40#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
43#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
44#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
45#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
46#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
47#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
48#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
49#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
50#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
51#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
52#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
53#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
54#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
55#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
56#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
57#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
58#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
59#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
60#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
61#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
62#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
63#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
64#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
65#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
66#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
67#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
68#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
69#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
70#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
71#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
72#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
73#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
74#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
75#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
76#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
77#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
78#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
79#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
80#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
81#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
82#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
83#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
84#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
85#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
86#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
87#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
88#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
89#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
90#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
91#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
92#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
93#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
94#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
95#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
96#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
97#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
98#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
99#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
100#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
101#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
102#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
103#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
104#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
105#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
106#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
107#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
108#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
109#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
110#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
111#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
112#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
113#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
114#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
115#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
116#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
117#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
118#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
119#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
120#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
121#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
122#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
123#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
124#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
125#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
126#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
127#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
128#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
129#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
130#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
131#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
132#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
133#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
134#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
135#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
136#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
137#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
138#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
139#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
140#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
141#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
142#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
143#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
144#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
145#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
146#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
147#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
148#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
149#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
150#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
151#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
152#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
153#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
25 154
26/* FIXME: This list is not completed. The correct directions are 155#endif /* ifndef __MACH_IOMUX_MX1_H__ */
27* missing on some (many) pins
28*/
29
30
31/* Primary GPIO pin functions */
32
33#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
34#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
35#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
36#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
37#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
38#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
39#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
40#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
41#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
42#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
43#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
44#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
45#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
46#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
47#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
48#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
49#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
50#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
51#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
52#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
53#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
54#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
55#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
56#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
57#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
58#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
59#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
60#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
61#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
62#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
63#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
64#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
65#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
66#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
67#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
68#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
69#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
70#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
71#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
72#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
73#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
74#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
75#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
76#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
77#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
78#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
79#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
80#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
81#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
82#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
83#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
84#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
85#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
86#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
87#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
88#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
89#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
90#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
91#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
92#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
93#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
94#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
95#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
96#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
97#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
98#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
99#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
100#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
101#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
102#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
103#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
104#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
105#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
106#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
107#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
108#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
109#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
110#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
111#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
112#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
113#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
114#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
115#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
116#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
117#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
118#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
119#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
120#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
121#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
122#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
123#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
124#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
125#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
126#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
127#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
128#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
129#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
130#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
131#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
132#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
133#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
134#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
135#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
136#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
137#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
138#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
139#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
140#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
141#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
142#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
143#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
144#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
145#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
146#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
147#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
148#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
149#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
150#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
151#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
152#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
153#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
154#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
155#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
156#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
157#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
158#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
159#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
160#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
161#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
162#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
163#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
164
165
166#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
index 63aaa972e275..1495dfda7834 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -1,126 +1,122 @@
1/* 1/*
2* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 2 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18 18#ifndef __MACH_IOMUX_MX21_H__
19#ifndef _MXC_IOMUX_MX21_H 19#define __MACH_IOMUX_MX21_H__
20#define _MXC_IOMUX_MX21_H 20
21 21#include <mach/iomux-mx2x.h>
22#ifndef GPIO_PORTA 22#include <mach/iomux-v1.h>
23#error Please include mach/iomux.h
24#endif
25
26 23
27/* Primary GPIO pin functions */ 24/* Primary GPIO pin functions */
28 25
29#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) 26#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
30#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) 27#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
31#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) 28#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
32#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) 29#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
33#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) 30#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
34#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) 31#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
35#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) 32#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
36#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) 33#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
37#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) 34#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
38#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) 35#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
39#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) 36#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
40#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) 37#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
41#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) 38#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
42#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) 39#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
43#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) 40#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
44#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) 41#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
45#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) 42#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
46#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) 43#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
47#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) 44#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
48#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) 45#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
49#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) 46#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
50#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) 47#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
51#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) 48#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
52#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) 49#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
53#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) 50#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
54#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) 51#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
55#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) 52#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
56#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) 53#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
57#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) 54#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
58 55
59/* Alternate GPIO pin functions */ 56/* Alternate GPIO pin functions */
60 57
61#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) 58#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
62#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) 59#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
63#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) 60#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
64#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) 61#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
65#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) 62#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
66#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) 63#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
67#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) 64#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
68#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) 65#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
69#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) 66#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
70#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) 67#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
71#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) 68#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
72#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) 69#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
73#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) 70#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
74#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) 71#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
75#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) 72#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
76#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) 73#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
77#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) 74#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
78#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) 75#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
79#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) 76#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
80#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) 77#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
81#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) 78#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
82 79
83/* AIN GPIO pin functions */ 80/* AIN GPIO pin functions */
84 81
85#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 82#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
86#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) 83#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
87#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) 84#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
88#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) 85#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
89#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) 86#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
90#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) 87#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
91#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) 88#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
92#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) 89#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
93#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) 90#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
94#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) 91#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
95#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) 92#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
96#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) 93#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
97 94
98/* BIN GPIO pin functions */ 95/* BIN GPIO pin functions */
99 96
100#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 97#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
101#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) 98#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
102 99
103/* CIN GPIO pin functions */ 100/* CIN GPIO pin functions */
104 101
105#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) 102#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
106 103
107/* AOUT GPIO pin functions */ 104/* AOUT GPIO pin functions */
108 105
109#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) 106#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
110#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) 107#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
111#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) 108#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
112#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) 109#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
113#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) 110#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
114#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) 111#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
115#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) 112#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
116#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) 113#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
117#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) 114#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
118#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) 115#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
119#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) 116#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
120#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) 117#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
121#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) 118#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
122#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) 119#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
123#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) 120#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
124 121
125 122#endif /* ifndef __MACH_IOMUX_MX21_H__ */
126#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 810c47f56e77..f39220d1b67a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -7,7 +7,7 @@
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * and 8 * and
9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h 9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h
10 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 10 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
11 * 11 *
12 * The code contained herein is licensed under the GNU General Public 12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License 13 * License. You may obtain a copy of the GNU General Public License
@@ -16,24 +16,11 @@
16 * http://www.opensource.org/licenses/gpl-license.html 16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html 17 * http://www.gnu.org/copyleft/gpl.html
18 */ 18 */
19#ifndef __IOMUX_MX25_H__ 19#ifndef __MACH_IOMUX_MX25_H__
20#define __IOMUX_MX25_H__ 20#define __MACH_IOMUX_MX25_H__
21 21
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24#ifndef GPIO_PORTA
25#error Please include mach/iomux.h
26#endif
27
28/*
29 *
30 * @brief MX25 I/O Pin List
31 *
32 * @ingroup GPIO_MX25
33 */
34
35#ifndef __ASSEMBLY__
36
37/* 24/*
38 * IOMUX/PAD Bit field definitions 25 * IOMUX/PAD Bit field definitions
39 */ 26 */
@@ -58,19 +45,19 @@
58 45
59#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL) 46#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
60#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL) 47#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
61#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL) 48#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
62 49
63#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL) 50#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
64#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL) 51#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
65#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL) 52#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
66 53
67#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL) 54#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
68#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL) 55#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
69#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL) 56#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
70 57
71#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL) 58#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
72#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL) 59#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
73#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL) 60#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
74 61
75#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL) 62#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
76#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL) 63#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
@@ -80,11 +67,11 @@
80 67
81#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL) 68#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
82#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL) 69#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
83#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL) 70#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
84 71
85#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL) 72#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
86#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL) 73#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
87#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL) 74#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
88 75
89#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL) 76#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
90#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL) 77#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
@@ -112,7 +99,7 @@
112#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) 99#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
113#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) 100#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
114 101
115#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL) 102#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
116#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL) 103#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
117 104
118#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL) 105#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
@@ -229,28 +216,28 @@
229#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) 216#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
230 217
231#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL) 218#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
232#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL) 219#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
233 220
234#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL) 221#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
235#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL) 222#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
236 223
237#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL) 224#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
238#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL) 225#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
239 226
240#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL) 227#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
241#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL) 228#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
242 229
243#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL) 230#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
244#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL) 231#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
245 232
246#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL) 233#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
247#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL) 234#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
248 235
249#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL) 236#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
250#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL) 237#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
251 238
252#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL) 239#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
253#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL) 240#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
254 241
255#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) 242#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
256#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL) 243#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
@@ -265,7 +252,7 @@
265#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) 252#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
266 253
267#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) 254#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
268#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL) 255#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
269 256
270#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) 257#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
271#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL) 258#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
@@ -354,19 +341,19 @@
354#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL) 341#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
355 342
356#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL) 343#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
357#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL) 344#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
358#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL) 345#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
359 346
360#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL) 347#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
361#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL) 348#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
362#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL) 349#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
363 350
364#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 351#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
365#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL) 352#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
366#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL) 353#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
367 354
368#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 355#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
369#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL) 356#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
370#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL) 357#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
371 358
372#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 359#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
@@ -377,11 +364,11 @@
377#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL) 364#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
378 365
379#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 366#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
380#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL) 367#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
381#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL) 368#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
382 369
383#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 370#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
384#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL) 371#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
385#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) 372#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
386 373
387#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) 374#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
@@ -410,7 +397,7 @@
410#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 397#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
411#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) 398#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
412 399
413#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL) 400#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
414#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL) 401#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
415#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL) 402#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
416 403
@@ -418,23 +405,23 @@
418#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL) 405#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
419#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL) 406#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
420 407
421#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL) 408#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
422#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL) 409#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
423 410
424#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL) 411#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
425#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL) 412#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
426#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL) 413#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
427 414
428#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL) 415#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
429#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL) 416#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
430 417
431#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 418#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
432#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL) 419#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
433 420
434#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 421#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
435#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL) 422#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
436 423
437#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 424#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
438#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP) 425#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
439#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL) 426#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
440 427
@@ -462,9 +449,11 @@
462#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) 449#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
463 450
464#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) 451#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
452#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
465#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) 453#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
466 454
467#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) 455#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
456#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
468#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) 457#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
469 458
470#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) 459#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
@@ -513,5 +502,4 @@
513#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) 502#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
514#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) 503#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
515 504
516#endif // __ASSEMBLY__ 505#endif /* __MACH_IOMUX_MX25_H__ */
517#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
index 5ac158b70f61..d9f9a6e32d80 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -1,207 +1,205 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX27_H__
20#ifndef _MXC_IOMUX_MX27_H 20#define __MACH_IOMUX_MX27_H__
21#define _MXC_IOMUX_MX27_H 21
22 22#include <mach/iomux-mx2x.h>
23#ifndef GPIO_PORTA 23#include <mach/iomux-v1.h>
24#error Please include mach/iomux.h
25#endif
26
27 24
28/* Primary GPIO pin functions */ 25/* Primary GPIO pin functions */
29 26
30#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) 27#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
31#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) 28#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
32#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) 29#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
33#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) 30#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
34#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) 31#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
35#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) 32#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
36#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) 33#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
37#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) 34#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
38#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) 35#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
39#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) 36#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
40#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) 37#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
41#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) 38#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
42#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) 39#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
43#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) 40#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
44#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) 41#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
45#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) 42#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
46#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) 43#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
47#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) 44#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
48#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) 45#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
49#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) 46#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
50#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) 47#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
51#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) 48#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
52#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) 49#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
53#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) 50#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
54#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) 51#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
55#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) 52#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
56#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) 53#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
57#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) 54#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
58#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) 55#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
59#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) 56#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
60#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) 57#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
61#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) 58#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
62#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) 59#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
63#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) 60#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
64#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) 61#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
65#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) 62#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
66#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) 63#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
67#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) 64#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
68#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) 65#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
69#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) 66#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
70#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) 67#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
71#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) 68#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
72#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) 69#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
73#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) 70#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
74#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) 71#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
75#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) 72#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
76#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) 73#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
77#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) 74#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
78#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) 75#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
79#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) 76#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
80#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) 77#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
81#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) 78#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
82#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) 79#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
83#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) 80#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
84#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) 81#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
85#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) 82#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
86#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) 83#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
87#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) 84#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
88#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
89#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
90 85
91/* Alternate GPIO pin functions */ 86/* Alternate GPIO pin functions */
92 87
93#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) 88#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
94#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) 89#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
95#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) 90#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
96#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) 91#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
97#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) 92#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
98#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) 93#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
99#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) 94#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
100#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) 95#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
101#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) 96#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
102#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) 97#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
103#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) 98#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
104#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) 99#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
105#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) 100#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
106#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) 101#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
107#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) 102#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
108#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) 103#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
109#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) 104#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
110#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) 105#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
111#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) 106#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
112#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) 107#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
113#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) 108#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
114#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) 109#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
115#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) 110#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
116#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) 111#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
117#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) 112#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
118#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) 113#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
119#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) 114#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
120#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) 115#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
121#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) 116#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
122#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) 117#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
123#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) 118#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
124#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) 119#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
125#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) 120#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
126#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) 121#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
127#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) 122#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
128#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) 123#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
129#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) 124#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
130#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) 125#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
131#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) 126#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
132#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) 127#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
133#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) 128#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
134#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) 129#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
135#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) 130#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
136#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) 131#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
137#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) 132#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
138#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) 133#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
139#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) 134#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
140#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) 135#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
141#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) 136#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
142#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) 137#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
143#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) 138#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
144#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) 139#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
140#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
141#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
145 142
146/* AIN GPIO pin functions */ 143/* AIN GPIO pin functions */
147 144
148#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 145#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
149#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) 146#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
150#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) 147#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
151#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) 148#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
152#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) 149#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
153#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) 150#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
154#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) 151#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
155#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) 152#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
156#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) 153#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
157#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) 154#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
158 155
159/* BIN GPIO pin functions */ 156/* BIN GPIO pin functions */
160 157
161#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 158#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
162 159
163/* CIN GPIO pin functions */ 160/* CIN GPIO pin functions */
164 161
165#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) 162#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
166#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) 163#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
167#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) 164#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
168#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) 165#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
169#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) 166#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
170#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) 167#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
171#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) 168#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
172#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) 169#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
173#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) 170#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
174#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) 171#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
175#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) 172#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
176#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) 173#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
177#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) 174#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
178#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) 175#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
179#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) 176#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
180#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) 177#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
181#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) 178#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
182/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ 179/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
183 180
184/* AOUT GPIO pin functions */ 181/* AOUT GPIO pin functions */
185 182
186#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) 183#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
187#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) 184#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
188#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) 185#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
189#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) 186#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
190#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) 187#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
191#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) 188#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
192#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) 189#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
193#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) 190#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
194#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) 191#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
195#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) 192#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
196#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) 193#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
197 194
198#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) 195/* BOUT GPIO pin functions */
199#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) 196
200#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) 197#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
201#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) 198#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
202#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) 199#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
203#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) 200#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
204#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) 201#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
205 202#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
206 203#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
207#endif /* _MXC_GPIO_MX1_MX2_H */ 204
205#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
index fb5ae638e79f..c4f116d214f2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -1,237 +1,230 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX2x_H__
20#ifndef _MXC_IOMUX_MX2x_H 20#define __MACH_IOMUX_MX2x_H__
21#define _MXC_IOMUX_MX2x_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27 21
28/* Primary GPIO pin functions */ 22/* Primary GPIO pin functions */
29 23
30#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) 24#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
31#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) 25#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
32#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) 26#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
33#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) 27#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
34#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) 28#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
35#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) 29#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
36#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) 30#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
37#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) 31#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
38#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) 32#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
39#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) 33#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
40#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) 34#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) 35#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) 36#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
43#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) 37#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
44#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) 38#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
45#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) 39#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
46#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) 40#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
47#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) 41#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
48#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) 42#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
49#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) 43#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
50#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) 44#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
51#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) 45#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
52#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) 46#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
53#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) 47#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
54#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) 48#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
55#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) 49#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
56#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) 50#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
57#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 51#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
58#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 52#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
59#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 53#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
60#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 54#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
61#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 55#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
62#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 56#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
63#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) 57#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
64#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) 58#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
65#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) 59#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
66#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) 60#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
67#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) 61#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
68#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) 62#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
69#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) 63#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
70#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) 64#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
71#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) 65#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
72#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) 66#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
73#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) 67#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
74#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) 68#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
75#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) 69#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
76#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) 70#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
77#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) 71#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
78#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) 72#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
79#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) 73#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
80#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) 74#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
81#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) 75#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
82#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) 76#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
83#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) 77#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
84#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) 78#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
85#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) 79#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
86#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) 80#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
87#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) 81#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
88#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) 82#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
89#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) 83#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
90#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) 84#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
91#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) 85#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
92#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) 86#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
93#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) 87#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
94#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) 88#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
95#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) 89#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
96#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) 90#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
97#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) 91#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
98#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) 92#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
99#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) 93#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
100#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) 94#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
101#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) 95#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
102#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) 96#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
103#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) 97#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
104#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) 98#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
105#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) 99#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
106#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) 100#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
107#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) 101#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
108#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) 102#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
109#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) 103#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
110#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) 104#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
111#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) 105#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
112#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) 106#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
113#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) 107#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
114#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) 108#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
115#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) 109#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
116#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) 110#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
117#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) 111#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
118#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) 112#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
119#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) 113#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
120#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) 114#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
121#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) 115#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
122#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) 116#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
123#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) 117#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
124#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) 118#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
125#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) 119#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
126#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) 120#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
127#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 121#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
128#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 122#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
129#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 123#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
130#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 124#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
131#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 125#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
132#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 126#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
133#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) 127#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
134#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) 128#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
135#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) 129#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
136#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) 130#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
137#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) 131#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
138#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) 132#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
139#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) 133#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
140#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) 134#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
141 135
142/* Alternate GPIO pin functions */ 136/* Alternate GPIO pin functions */
143 137
144#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) 138#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
145#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) 139#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
146#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) 140#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
147#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) 141#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
148#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) 142#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
149#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) 143#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
150#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) 144#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
151#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) 145#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
152#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) 146#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
153#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) 147#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
154#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) 148#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
155#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) 149#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
156#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) 150#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
157#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) 151#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
158#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) 152#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
159#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) 153#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
160#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) 154#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
161#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) 155#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
162#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) 156#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
163#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) 157#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
164#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) 158#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
165#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) 159#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
166#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) 160#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
167#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) 161#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
168#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) 162#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
169#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) 163#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
170#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) 164#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
171 165
172/* AIN GPIO pin functions */ 166/* AIN GPIO pin functions */
173 167
174#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) 168#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
175#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) 169#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
176#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) 170#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
177#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) 171#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
178#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) 172#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
179#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) 173#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
180#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) 174#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
181#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) 175#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
182#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) 176#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
183#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) 177#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
184#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) 178#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
185#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) 179#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
186#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) 180#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
187#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) 181#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
188#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) 182#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
189#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) 183#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
190#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) 184#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
191#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) 185#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
192#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) 186#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
193#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) 187#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
194#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) 188#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
195#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) 189#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
196#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) 190#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
197#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) 191#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
198#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) 192#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
199#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) 193#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
200#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) 194#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
201#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) 195#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
202#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) 196#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
203#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) 197#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
204#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) 198#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
205#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) 199#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
206#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) 200#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
207#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) 201#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
208#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) 202#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
209#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) 203#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
210 204
211/* BIN GPIO pin functions */ 205/* BIN GPIO pin functions */
212 206
213#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) 207#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
214 208
215/* CIN GPIO pin functions */ 209/* CIN GPIO pin functions */
216 210
217#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) 211#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
218#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) 212#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
219#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) 213#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
220#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) 214#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
221#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) 215#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
222#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) 216#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
223#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) 217#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
224#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) 218#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
225#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) 219#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
226#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) 220#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
227 221
228/* AOUT GPIO pin functions */ 222/* AOUT GPIO pin functions */
229 223
230#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) 224#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
231#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) 225#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
232#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) 226#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
233#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) 227#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
234#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) 228#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
235
236 229
237#endif 230#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 446f86763816..e51465d7b224 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -16,12 +16,10 @@
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18 */ 18 */
19 19#ifndef __MACH_IOMUX_MX3_H__
20#ifndef __MACH_MX31_IOMUX_H__ 20#define __MACH_IOMUX_MX3_H__
21#define __MACH_MX31_IOMUX_H__
22 21
23#include <linux/types.h> 22#include <linux/types.h>
24
25/* 23/*
26 * various IOMUX output functions 24 * various IOMUX output functions
27 */ 25 */
@@ -34,7 +32,7 @@
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ 32#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ 33#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ 34#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ 35#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ 36#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */ 37#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ 38#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
@@ -112,7 +110,7 @@ enum iomux_gp_func {
112 * setups a single pin: 110 * setups a single pin:
113 * - reserves the pin so that it is not claimed by another driver 111 * - reserves the pin so that it is not claimed by another driver
114 * - setups the iomux according to the configuration 112 * - setups the iomux according to the configuration
115 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib 113 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
116 */ 114 */
117int mxc_iomux_alloc_pin(const unsigned int pin, const char *label); 115int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
118/* 116/*
@@ -167,11 +165,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
167 MXC_GPIO_IRQ_START) 165 MXC_GPIO_IRQ_START)
168 166
169/* 167/*
170 * The number of gpio devices among the pads
171 */
172#define GPIO_PORT_MAX 3
173
174/*
175 * This enumeration is constructed based on the Section 168 * This enumeration is constructed based on the Section
176 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 169 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
177 * value is constructed based on the rules described above. 170 * value is constructed based on the rules described above.
@@ -524,10 +517,18 @@ enum iomux_pins {
524#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) 517#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
525#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) 518#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
526#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) 519#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
520#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
521#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
522#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
523#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) 524#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
528#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) 525#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
529#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) 526#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
530#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) 527#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
528#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
529#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
530#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
531#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
531#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) 532#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
532#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) 533#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
533#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) 534#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
@@ -623,31 +624,43 @@ enum iomux_pins {
623#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) 624#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
624#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) 625#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
625#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) 626#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
626#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) 627#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
627#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) 628#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
628#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) 629#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
629#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) 630#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
630#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) 631#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
631#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) 632#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
632#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) 633#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
633#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) 634#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
634#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) 635#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
635#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) 636#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
636#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) 637#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
637#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) 638#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
638#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) 639#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
639#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) 640#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
640#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) 641#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
641#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) 642#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
642#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) 643#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
643#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) 644#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
644#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) 645#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
645#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) 646#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
646#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) 647#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
647#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) 648#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
648#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) 649#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
649#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) 650#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
650#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) 651#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
652#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
653#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
654#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
655#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
656#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
657#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
658#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
659#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
660#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
661#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
662#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
663#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
651#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 664#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
652#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 665#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
653#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) 666#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -691,17 +704,30 @@ enum iomux_pins {
691#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) 704#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
692#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) 705#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
693#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) 706#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
694#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) 707#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
695#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) 708#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
709#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
710#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
711#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
712#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
713#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
714#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
715#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
716#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
717#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
718#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
719#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
696 722
697 723/*
698/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 724 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
699 * cspi1_ss1*/ 725 * cspi2_ss1, cspi1_ss0 cspi1_ss1
726 */
700 727
701/* 728/*
702 * This function configures the pad value for a IOMUX pin. 729 * This function configures the pad value for a IOMUX pin.
703 */ 730 */
704void mxc_iomux_set_pad(enum iomux_pins, u32); 731void mxc_iomux_set_pad(enum iomux_pins, u32);
705 732
706#endif 733#endif /* ifndef __MACH_IOMUX_MX3_H__ */
707
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 00b0ac1db225..2a24bae1b878 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 2 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -671,7 +671,7 @@
671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) 671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
672 672
673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) 673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) 674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) 675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
676 676
677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) 677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
new file mode 100644
index 000000000000..b4f975e6a665
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -0,0 +1,326 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __MACH_IOMUX_MX51_H__
13#define __MACH_IOMUX_MX51_H__
14
15#include <mach/iomux-v3.h>
16
17/*
18 * various IOMUX alternate output functions (1-7)
19 */
20typedef enum iomux_config {
21 IOMUX_CONFIG_ALT0,
22 IOMUX_CONFIG_ALT1,
23 IOMUX_CONFIG_ALT2,
24 IOMUX_CONFIG_ALT3,
25 IOMUX_CONFIG_ALT4,
26 IOMUX_CONFIG_ALT5,
27 IOMUX_CONFIG_ALT6,
28 IOMUX_CONFIG_ALT7,
29 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
30 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
31} iomux_pin_cfg_t;
32
33/* Pad control groupings */
34#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH)
36#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
37 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST)
40
41/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
43 * If <padname> or <padmode> refers to a GPIO, it is named
44 * GPIO_<unit>_<num> see also iomux-v3.h
45 */
46
47/*
48 * FIXME: This was converted using scripts from existing Freescale code to
49 * this form used upstream. Need to verify the name format.
50 */
51
52/* PAD MUX ALT INPSE PATH PADCTRL */
53
54#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
55#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
56#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62
63/* Babbage UART3 */
64#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
65#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
66#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
67#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
68
69#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
70#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
72#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
73
74#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
75#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
78#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
80#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
82
83#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
84#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
85#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
86#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
87#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
88#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
89#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
91
92#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
98#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
100
101#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
114/* REVISIT: Not sure of these values
115
116 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
117 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
118 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
119*/
120#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
122#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
124#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
125#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
126#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
187
188/* Babbage UART1 */
189#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
190#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
191#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
192#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
193
194/* Babbage UART2 */
195#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
196#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
197
198#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
199#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
200#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
201#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
202#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
203#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
204#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
205#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
227#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
229#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
231#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
233#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
235#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
306
307/* EIM */
308#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
312#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
313#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
314#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
315#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
316
317#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
319#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
321#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
324#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
325
326#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 9f13061192c8..3887f3fe29d4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -48,7 +48,7 @@
48 * setups a single pin: 48 * setups a single pin:
49 * - reserves the pin so that it is not claimed by another driver 49 * - reserves the pin so that it is not claimed by another driver
50 * - setups the iomux according to the configuration 50 * - setups the iomux according to the configuration
51 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib 51 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
52 */ 52 */
53int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); 53int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
54/* 54/*
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
new file mode 100644
index 000000000000..884f5753f279
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#ifndef __MACH_IOMUX_V1_H__
20#define __MACH_IOMUX_V1_H__
21
22/*
23* GPIO Module and I/O Multiplexer
24* x = 0..3 for reg_A, reg_B, reg_C, reg_D
25*/
26#define MXC_DDIR(x) (0x00 + ((x) << 8))
27#define MXC_OCR1(x) (0x04 + ((x) << 8))
28#define MXC_OCR2(x) (0x08 + ((x) << 8))
29#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
30#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
31#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
32#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
33#define MXC_DR(x) (0x1c + ((x) << 8))
34#define MXC_GIUS(x) (0x20 + ((x) << 8))
35#define MXC_SSR(x) (0x24 + ((x) << 8))
36#define MXC_ICR1(x) (0x28 + ((x) << 8))
37#define MXC_ICR2(x) (0x2c + ((x) << 8))
38#define MXC_IMR(x) (0x30 + ((x) << 8))
39#define MXC_ISR(x) (0x34 + ((x) << 8))
40#define MXC_GPR(x) (0x38 + ((x) << 8))
41#define MXC_SWR(x) (0x3c + ((x) << 8))
42#define MXC_PUEN(x) (0x40 + ((x) << 8))
43
44#define MX1_NUM_GPIO_PORT 4
45#define MX21_NUM_GPIO_PORT 6
46#define MX27_NUM_GPIO_PORT 6
47
48#define GPIO_PIN_MASK 0x1f
49
50#define GPIO_PORT_SHIFT 5
51#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
52
53#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
54#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
55#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
56#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
57#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
58#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
59
60#define GPIO_OUT (1 << 8)
61#define GPIO_IN (0 << 8)
62#define GPIO_PUEN (1 << 9)
63
64#define GPIO_PF (1 << 10)
65#define GPIO_AF (1 << 11)
66
67#define GPIO_OCR_SHIFT 12
68#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
69#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
70#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
71#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
72#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
73
74#define GPIO_AOUT_SHIFT 14
75#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
76#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
77#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
78#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
79#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
80
81#define GPIO_BOUT_SHIFT 16
82#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
83#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
84#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
87
88/* decode irq number to use with IMR(x), ISR(x) and friends */
89#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
90
91#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
92#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
93#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
94#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
95#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
96#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
97
98extern int mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102
103#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index a0fa40265468..f2f73d31d5ba 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -81,16 +81,16 @@ struct pad_desc {
81 81
82#define PAD_CTL_ODE (1 << 3) 82#define PAD_CTL_ODE (1 << 3)
83 83
84#define PAD_CTL_DSE_STANDARD (0 << 1) 84#define PAD_CTL_DSE_LOW (0 << 1)
85#define PAD_CTL_DSE_HIGH (1 << 1) 85#define PAD_CTL_DSE_MED (1 << 1)
86#define PAD_CTL_DSE_MAX (2 << 1) 86#define PAD_CTL_DSE_HIGH (2 << 1)
87#define PAD_CTL_DSE_MAX (3 << 1)
87 88
88#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0)
89 91
90/* 92/*
91 * setups a single pad: 93 * setups a single pad in the iomuxer
92 * - reserves the pad so that it is not claimed by another driver
93 * - setups the iomux according to the configuration
94 */ 94 */
95int mxc_iomux_v3_setup_pad(struct pad_desc *pad); 95int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
96 96
@@ -101,19 +101,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
101int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); 101int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
102 102
103/* 103/*
104 * releases a single pad:
105 * - make it available for a future use by another driver
106 * - DOES NOT reconfigure the IOMUX in its reset state
107 */
108void mxc_iomux_v3_release_pad(struct pad_desc *pad);
109
110/*
111 * releases multiple pads
112 * convenvient way to call the above function with tables
113 */
114void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
115
116/*
117 * Initialise the iomux controller 104 * Initialise the iomux controller
118 */ 105 */
119void mxc_iomux_v3_init(void __iomem *iomux_v3_base); 106void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 6d49f8ae3259..3d226d7e7be2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -1,102 +1,14 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 *
4* 4 * This program is free software; you can redistribute it and/or modify it
5* This program is free software; you can redistribute it and/or 5 * under the terms of the GNU General Public License version 2 as published by
6* modify it under the terms of the GNU General Public License 6 * the Free Software Foundation.
7* as published by the Free Software Foundation; either version 2 7 */
8* of the License, or (at your option) any later version. 8#ifndef __MACH_IOMUX_H__
9* This program is distributed in the hope that it will be useful, 9#define __MACH_IOMUX_H__
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_H
21#define _MXC_IOMUX_H
22
23/*
24* GPIO Module and I/O Multiplexer
25* x = 0..3 for reg_A, reg_B, reg_C, reg_D
26*/
27#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
28#define MXC_DDIR(x) (0x00 + ((x) << 8))
29#define MXC_OCR1(x) (0x04 + ((x) << 8))
30#define MXC_OCR2(x) (0x08 + ((x) << 8))
31#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
32#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
33#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
34#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
35#define MXC_DR(x) (0x1c + ((x) << 8))
36#define MXC_GIUS(x) (0x20 + ((x) << 8))
37#define MXC_SSR(x) (0x24 + ((x) << 8))
38#define MXC_ICR1(x) (0x28 + ((x) << 8))
39#define MXC_ICR2(x) (0x2c + ((x) << 8))
40#define MXC_IMR(x) (0x30 + ((x) << 8))
41#define MXC_ISR(x) (0x34 + ((x) << 8))
42#define MXC_GPR(x) (0x38 + ((x) << 8))
43#define MXC_SWR(x) (0x3c + ((x) << 8))
44#define MXC_PUEN(x) (0x40 + ((x) << 8))
45
46#ifdef CONFIG_ARCH_MX1
47# define GPIO_PORT_MAX 3
48#endif
49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5
51#endif
52#ifdef CONFIG_ARCH_MX25
53# define GPIO_PORT_MAX 3
54#endif
55
56#ifndef GPIO_PORT_MAX
57# error "GPIO config port count unknown!"
58#endif
59
60#define GPIO_PIN_MASK 0x1f
61
62#define GPIO_PORT_SHIFT 5
63#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
64
65#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
66#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
67#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
68#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
69#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
70#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
71
72#define GPIO_OUT (1 << 8)
73#define GPIO_IN (0 << 8)
74#define GPIO_PUEN (1 << 9)
75
76#define GPIO_PF (1 << 10)
77#define GPIO_AF (1 << 11)
78
79#define GPIO_OCR_SHIFT 12
80#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
81#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
82#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
83#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
84#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
85
86#define GPIO_AOUT_SHIFT 14
87#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
89#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
90#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
91#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
92
93#define GPIO_BOUT_SHIFT 16
94#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
96#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
97#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
98#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
99 10
11/* This file will go away, please include mach/iomux-mx... directly */
100 12
101#ifdef CONFIG_ARCH_MX1 13#ifdef CONFIG_ARCH_MX1
102#include <mach/iomux-mx1.h> 14#include <mach/iomux-mx1.h>
@@ -110,24 +22,5 @@
110#include <mach/iomux-mx27.h> 22#include <mach/iomux-mx27.h>
111#endif 23#endif
112#endif 24#endif
113#ifdef CONFIG_ARCH_MX25
114#include <mach/iomux-mx25.h>
115#endif
116 25
117 26#endif /* __MACH_IOMUX_H__ */
118/* decode irq number to use with IMR(x), ISR(x) and friends */
119#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
120
121#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
122#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
123#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
124#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
125#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
126
127
128extern void mxc_gpio_mode(int gpio_mode);
129extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
130 const char *label);
131extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
132
133#endif
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ead9d592168d..86781f7b0c0c 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,22 +12,29 @@
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14/* 14/*
15 * So far all i.MX SoCs have 64 internal interrupts 15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
16 */ 16 */
17#ifdef CONFIG_MXC_TZIC
18#define MXC_INTERNAL_IRQS 128
19#else
17#define MXC_INTERNAL_IRQS 64 20#define MXC_INTERNAL_IRQS 64
21#endif
18 22
19#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
20 24
21#if defined CONFIG_ARCH_MX1 25/* these are ordered by size to support multi-SoC kernels */
22#define MXC_GPIO_IRQS (32 * 4) 26#if defined CONFIG_ARCH_MX2
23#elif defined CONFIG_ARCH_MX2
24#define MXC_GPIO_IRQS (32 * 6) 27#define MXC_GPIO_IRQS (32 * 6)
25#elif defined CONFIG_ARCH_MX3 28#elif defined CONFIG_ARCH_MX1
26#define MXC_GPIO_IRQS (32 * 3) 29#define MXC_GPIO_IRQS (32 * 4)
27#elif defined CONFIG_ARCH_MX25 30#elif defined CONFIG_ARCH_MX25
28#define MXC_GPIO_IRQS (32 * 4) 31#define MXC_GPIO_IRQS (32 * 4)
32#elif defined CONFIG_ARCH_MX5
33#define MXC_GPIO_IRQS (32 * 4)
29#elif defined CONFIG_ARCH_MXC91231 34#elif defined CONFIG_ARCH_MXC91231
30#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_ARCH_MX3
37#define MXC_GPIO_IRQS (32 * 3)
31#endif 38#endif
32 39
33/* 40/*
@@ -37,7 +44,12 @@
37 * within sensible limits. 44 * within sensible limits.
38 */ 45 */
39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) 46#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
47
48#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
49#define MXC_BOARD_IRQS 80
50#else
40#define MXC_BOARD_IRQS 16 51#define MXC_BOARD_IRQS 16
52#endif
41 53
42#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) 54#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
43 55
@@ -46,6 +58,7 @@
46#else 58#else
47#define MX3_IPU_IRQS 0 59#define MX3_IPU_IRQS 0
48#endif 60#endif
61/* REVISIT: Add IPU irqs on IMX51 */
49 62
50#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 63#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
51 64
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index d3afafdcc0e5..c4b40c35a6a1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -11,37 +11,45 @@
11#ifndef __ASM_ARCH_MXC_MEMORY_H__ 11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__ 12#define __ASM_ARCH_MXC_MEMORY_H__
13 13
14#if defined CONFIG_ARCH_MX1 14#define MX1_PHYS_OFFSET UL(0x08000000)
15#define PHYS_OFFSET UL(0x08000000) 15#define MX21_PHYS_OFFSET UL(0xc0000000)
16#elif defined CONFIG_ARCH_MX2 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#ifdef CONFIG_MACH_MX21 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define PHYS_OFFSET UL(0xC0000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#endif 19#define MX51_PHYS_OFFSET UL(0x90000000)
20#ifdef CONFIG_MACH_MX27 20#define MXC91231_PHYS_OFFSET UL(0x90000000)
21#define PHYS_OFFSET UL(0xA0000000) 21
22#endif 22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
23#elif defined CONFIG_ARCH_MX3 23# if defined CONFIG_ARCH_MX1
24#define PHYS_OFFSET UL(0x80000000) 24# define PHYS_OFFSET MX1_PHYS_OFFSET
25#elif defined CONFIG_ARCH_MX25 25# elif defined CONFIG_MACH_MX21
26#define PHYS_OFFSET UL(0x80000000) 26# define PHYS_OFFSET MX21_PHYS_OFFSET
27#elif defined CONFIG_ARCH_MXC91231 27# elif defined CONFIG_ARCH_MX25
28#define PHYS_OFFSET UL(0x90000000) 28# define PHYS_OFFSET MX25_PHYS_OFFSET
29# elif defined CONFIG_MACH_MX27
30# define PHYS_OFFSET MX27_PHYS_OFFSET
31# elif defined CONFIG_ARCH_MX3
32# define PHYS_OFFSET MX3x_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MXC91231
34# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5
36# define PHYS_OFFSET MX51_PHYS_OFFSET
37# endif
29#endif 38#endif
30 39
31#if defined(CONFIG_MX1_VIDEO) 40#if defined(CONFIG_MX3_VIDEO)
32/* 41/*
33 * Increase size of DMA-consistent memory region. 42 * Increase size of DMA-consistent memory region.
34 * This is required for i.MX camera driver to capture at least four VGA frames. 43 * This is required for mx3 camera driver to capture at least two QXGA frames.
35 */ 44 */
36#define CONSISTENT_DMA_SIZE SZ_4M 45#define CONSISTENT_DMA_SIZE SZ_8M
37#endif /* CONFIG_MX1_VIDEO */
38 46
39#if defined(CONFIG_MX3_VIDEO) 47#elif defined(CONFIG_MX1_VIDEO)
40/* 48/*
41 * Increase size of DMA-consistent memory region. 49 * Increase size of DMA-consistent memory region.
42 * This is required for mx3 camera driver to capture at least two QXGA frames. 50 * This is required for i.MX camera driver to capture at least four VGA frames.
43 */ 51 */
44#define CONSISTENT_DMA_SIZE SZ_8M 52#define CONSISTENT_DMA_SIZE SZ_4M
45#endif /* CONFIG_MX3_VIDEO */ 53#endif /* CONFIG_MX1_VIDEO */
46 54
47#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 55#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h
deleted file mode 100644
index 1ab1bba5688d..000000000000
--- a/arch/arm/plat-mxc/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <mach/mxc_timer.h>
15
16#ifndef __ARCH_IMX_MTD_XIP_H__
17#define __ARCH_IMX_MTD_XIP_H__
18
19#ifdef CONFIG_ARCH_MX1
20/* AITC registers */
21#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
22#define NIPNDH (AITC_BASE + 0x58)
23#define NIPNDL (AITC_BASE + 0x5C)
24#define INTENABLEH (AITC_BASE + 0x10)
25#define INTENABLEL (AITC_BASE + 0x14)
26/* MTD macros */
27#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
28 || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
29#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
30#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
31#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
32#endif /* CONFIG_ARCH_MX1 */
33
34#endif /* __ARCH_IMX_MTD_XIP_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1b2890a5c452..5eba7e6785de 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -9,156 +9,289 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef __ASM_ARCH_MXC_MX1_H__ 12#ifndef __MACH_MX1_H__
13#define __ASM_ARCH_MXC_MX1_H__ 13#define __MACH_MX1_H__
14 14
15#include <mach/vmalloc.h> 15#include <mach/vmalloc.h>
16 16
17/* 17/*
18 * Memory map 18 * Memory map
19 */ 19 */
20#define IMX_IO_PHYS 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define IMX_IO_SIZE 0x00100000 21#define MX1_IO_SIZE SZ_1M
22#define IMX_IO_BASE VMALLOC_END 22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 23
24#define IMX_CS0_PHYS 0x10000000 24#define MX1_CS0_PHYS 0x10000000
25#define IMX_CS0_SIZE 0x02000000 25#define MX1_CS0_SIZE 0x02000000
26 26
27#define IMX_CS1_PHYS 0x12000000 27#define MX1_CS1_PHYS 0x12000000
28#define IMX_CS1_SIZE 0x01000000 28#define MX1_CS1_SIZE 0x01000000
29 29
30#define IMX_CS2_PHYS 0x13000000 30#define MX1_CS2_PHYS 0x13000000
31#define IMX_CS2_SIZE 0x01000000 31#define MX1_CS2_SIZE 0x01000000
32 32
33#define IMX_CS3_PHYS 0x14000000 33#define MX1_CS3_PHYS 0x14000000
34#define IMX_CS3_SIZE 0x01000000 34#define MX1_CS3_SIZE 0x01000000
35 35
36#define IMX_CS4_PHYS 0x15000000 36#define MX1_CS4_PHYS 0x15000000
37#define IMX_CS4_SIZE 0x01000000 37#define MX1_CS4_SIZE 0x01000000
38 38
39#define IMX_CS5_PHYS 0x16000000 39#define MX1_CS5_PHYS 0x16000000
40#define IMX_CS5_SIZE 0x01000000 40#define MX1_CS5_SIZE 0x01000000
41 41
42/* 42/*
43 * Register BASEs, based on OFFSETs 43 * Register BASEs, based on OFFSETs
44 */ 44 */
45#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) 45#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
46#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) 46#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
47#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) 47#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
48#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) 48#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
49#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) 49#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
50#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) 50#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
51#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) 51#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
52#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) 52#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
53#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) 53#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
54#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) 54#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
55#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) 55#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
56#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) 56#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
57#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) 57#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
58#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) 58#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
59#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) 59#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
60#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) 60#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
61#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) 61#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
62#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) 62#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
63#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) 63#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
64#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) 64#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
65#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) 65#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
66#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) 66#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
67#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) 67#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
68#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) 68#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) 69#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
70#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) 70#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
71#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) 71#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
72#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) 72#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
73#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) 73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 74
75/* macro to get at IO space when running virtually */ 75/* macro to get at IO space when running virtually */
76#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) 76#define MX1_IO_ADDRESS(x) ( \
77 77 IMX_IO_ADDRESS(x, MX1_IO))
78/* define macros needed for entry-macro.S */
79#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
80 78
81/* fixed interrput numbers */ 79/* fixed interrput numbers */
82#define INT_SOFTINT 0 80#define MX1_INT_SOFTINT 0
83#define CSI_INT 6 81#define MX1_CSI_INT 6
84#define DSPA_MAC_INT 7 82#define MX1_DSPA_MAC_INT 7
85#define DSPA_INT 8 83#define MX1_DSPA_INT 8
86#define COMP_INT 9 84#define MX1_COMP_INT 9
87#define MSHC_XINT 10 85#define MX1_MSHC_XINT 10
88#define GPIO_INT_PORTA 11 86#define MX1_GPIO_INT_PORTA 11
89#define GPIO_INT_PORTB 12 87#define MX1_GPIO_INT_PORTB 12
90#define GPIO_INT_PORTC 13 88#define MX1_GPIO_INT_PORTC 13
91#define LCDC_INT 14 89#define MX1_LCDC_INT 14
92#define SIM_INT 15 90#define MX1_SIM_INT 15
93#define SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
94#define RTC_INT 17 92#define MX1_RTC_INT 17
95#define RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
96#define UART2_MINT_PFERR 19 94#define MX1_UART2_MINT_PFERR 19
97#define UART2_MINT_RTS 20 95#define MX1_UART2_MINT_RTS 20
98#define UART2_MINT_DTR 21 96#define MX1_UART2_MINT_DTR 21
99#define UART2_MINT_UARTC 22 97#define MX1_UART2_MINT_UARTC 22
100#define UART2_MINT_TX 23 98#define MX1_UART2_MINT_TX 23
101#define UART2_MINT_RX 24 99#define MX1_UART2_MINT_RX 24
102#define UART1_MINT_PFERR 25 100#define MX1_UART1_MINT_PFERR 25
103#define UART1_MINT_RTS 26 101#define MX1_UART1_MINT_RTS 26
104#define UART1_MINT_DTR 27 102#define MX1_UART1_MINT_DTR 27
105#define UART1_MINT_UARTC 28 103#define MX1_UART1_MINT_UARTC 28
106#define UART1_MINT_TX 29 104#define MX1_UART1_MINT_TX 29
107#define UART1_MINT_RX 30 105#define MX1_UART1_MINT_RX 30
108#define VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
109#define VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
110#define PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
111#define PWM_INT 34 109#define MX1_PWM_INT 34
112#define SDHC_INT 35 110#define MX1_SDHC_INT 35
113#define I2C_INT 39 111#define MX1_I2C_INT 39
114#define CSPI_INT 41 112#define MX1_CSPI_INT 41
115#define SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
116#define SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
117#define SSI_RX_INT 44 115#define MX1_SSI_RX_INT 44
118#define SSI_RX_ERR_INT 45 116#define MX1_SSI_RX_ERR_INT 45
119#define TOUCH_INT 46 117#define MX1_TOUCH_INT 46
120#define USBD_INT0 47 118#define MX1_USBD_INT0 47
121#define USBD_INT1 48 119#define MX1_USBD_INT1 48
122#define USBD_INT2 49 120#define MX1_USBD_INT2 49
123#define USBD_INT3 50 121#define MX1_USBD_INT3 50
124#define USBD_INT4 51 122#define MX1_USBD_INT4 51
125#define USBD_INT5 52 123#define MX1_USBD_INT5 52
126#define USBD_INT6 53 124#define MX1_USBD_INT6 53
127#define BTSYS_INT 55 125#define MX1_BTSYS_INT 55
128#define BTTIM_INT 56 126#define MX1_BTTIM_INT 56
129#define BTWUI_INT 57 127#define MX1_BTWUI_INT 57
130#define TIM2_INT 58 128#define MX1_TIM2_INT 58
131#define TIM1_INT 59 129#define MX1_TIM1_INT 59
132#define DMA_ERR 60 130#define MX1_DMA_ERR 60
133#define DMA_INT 61 131#define MX1_DMA_INT 61
134#define GPIO_INT_PORTD 62 132#define MX1_GPIO_INT_PORTD 62
135#define WDT_INT 63 133#define MX1_WDT_INT 63
136 134
137/* DMA */ 135/* DMA */
138#define DMA_REQ_UART3_T 2 136#define MX1_DMA_REQ_UART3_T 2
139#define DMA_REQ_UART3_R 3 137#define MX1_DMA_REQ_UART3_R 3
140#define DMA_REQ_SSI2_T 4 138#define MX1_DMA_REQ_SSI2_T 4
141#define DMA_REQ_SSI2_R 5 139#define MX1_DMA_REQ_SSI2_R 5
142#define DMA_REQ_CSI_STAT 6 140#define MX1_DMA_REQ_CSI_STAT 6
143#define DMA_REQ_CSI_R 7 141#define MX1_DMA_REQ_CSI_R 7
144#define DMA_REQ_MSHC 8 142#define MX1_DMA_REQ_MSHC 8
145#define DMA_REQ_DSPA_DCT_DOUT 9 143#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
146#define DMA_REQ_DSPA_DCT_DIN 10 144#define MX1_DMA_REQ_DSPA_DCT_DIN 10
147#define DMA_REQ_DSPA_MAC 11 145#define MX1_DMA_REQ_DSPA_MAC 11
148#define DMA_REQ_EXT 12 146#define MX1_DMA_REQ_EXT 12
149#define DMA_REQ_SDHC 13 147#define MX1_DMA_REQ_SDHC 13
150#define DMA_REQ_SPI1_R 14 148#define MX1_DMA_REQ_SPI1_R 14
151#define DMA_REQ_SPI1_T 15 149#define MX1_DMA_REQ_SPI1_T 15
152#define DMA_REQ_SSI_T 16 150#define MX1_DMA_REQ_SSI_T 16
153#define DMA_REQ_SSI_R 17 151#define MX1_DMA_REQ_SSI_R 17
154#define DMA_REQ_ASP_DAC 18 152#define MX1_DMA_REQ_ASP_DAC 18
155#define DMA_REQ_ASP_ADC 19 153#define MX1_DMA_REQ_ASP_ADC 19
156#define DMA_REQ_USP_EP(x) (20 + (x)) 154#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
157#define DMA_REQ_SPI2_R 26 155#define MX1_DMA_REQ_SPI2_R 26
158#define DMA_REQ_SPI2_T 27 156#define MX1_DMA_REQ_SPI2_T 27
159#define DMA_REQ_UART2_T 28 157#define MX1_DMA_REQ_UART2_T 28
160#define DMA_REQ_UART2_R 29 158#define MX1_DMA_REQ_UART2_R 29
161#define DMA_REQ_UART1_T 30 159#define MX1_DMA_REQ_UART1_T 30
162#define DMA_REQ_UART1_R 31 160#define MX1_DMA_REQ_UART1_R 31
163 161
164#endif /* __ASM_ARCH_MXC_MX1_H__ */ 162/*
163 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
164 * to not break drivers/usb/gadget/imx_udc. Should go
165 * away after this driver uses the new name.
166 */
167#define USBD_INT0 MX1_USBD_INT0
168
169#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
170/* these should go away */
171#define IMX_IO_PHYS MX1_IO_BASE_ADDR
172#define IMX_IO_SIZE MX1_IO_SIZE
173#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
174#define IMX_CS0_PHYS MX1_CS0_PHYS
175#define IMX_CS0_SIZE MX1_CS0_SIZE
176#define IMX_CS1_PHYS MX1_CS1_PHYS
177#define IMX_CS1_SIZE MX1_CS1_SIZE
178#define IMX_CS2_PHYS MX1_CS2_PHYS
179#define IMX_CS2_SIZE MX1_CS2_SIZE
180#define IMX_CS3_PHYS MX1_CS3_PHYS
181#define IMX_CS3_SIZE MX1_CS3_SIZE
182#define IMX_CS4_PHYS MX1_CS4_PHYS
183#define IMX_CS4_SIZE MX1_CS4_SIZE
184#define IMX_CS5_PHYS MX1_CS5_PHYS
185#define IMX_CS5_SIZE MX1_CS5_SIZE
186#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
187#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
188#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
189#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
190#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
191#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
192#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
194#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
195#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
196#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
197#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
198#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
199#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
200#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
201#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
202#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
203#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
204#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
205#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
206#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
207#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
208#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
209#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
210#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
211#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
212#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
213#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
214#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
215#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
216#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
217#define INT_SOFTINT MX1_INT_SOFTINT
218#define CSI_INT MX1_CSI_INT
219#define DSPA_MAC_INT MX1_DSPA_MAC_INT
220#define DSPA_INT MX1_DSPA_INT
221#define COMP_INT MX1_COMP_INT
222#define MSHC_XINT MX1_MSHC_XINT
223#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
224#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
225#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
226#define LCDC_INT MX1_LCDC_INT
227#define SIM_INT MX1_SIM_INT
228#define SIM_DATA_INT MX1_SIM_DATA_INT
229#define RTC_INT MX1_RTC_INT
230#define RTC_SAMINT MX1_RTC_SAMINT
231#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
232#define UART2_MINT_RTS MX1_UART2_MINT_RTS
233#define UART2_MINT_DTR MX1_UART2_MINT_DTR
234#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
235#define UART2_MINT_TX MX1_UART2_MINT_TX
236#define UART2_MINT_RX MX1_UART2_MINT_RX
237#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
238#define UART1_MINT_RTS MX1_UART1_MINT_RTS
239#define UART1_MINT_DTR MX1_UART1_MINT_DTR
240#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
241#define UART1_MINT_TX MX1_UART1_MINT_TX
242#define UART1_MINT_RX MX1_UART1_MINT_RX
243#define VOICE_DAC_INT MX1_VOICE_DAC_INT
244#define VOICE_ADC_INT MX1_VOICE_ADC_INT
245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT
249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
252#define SSI_RX_INT MX1_SSI_RX_INT
253#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
254#define TOUCH_INT MX1_TOUCH_INT
255#define USBD_INT1 MX1_USBD_INT1
256#define USBD_INT2 MX1_USBD_INT2
257#define USBD_INT3 MX1_USBD_INT3
258#define USBD_INT4 MX1_USBD_INT4
259#define USBD_INT5 MX1_USBD_INT5
260#define USBD_INT6 MX1_USBD_INT6
261#define BTSYS_INT MX1_BTSYS_INT
262#define BTTIM_INT MX1_BTTIM_INT
263#define BTWUI_INT MX1_BTWUI_INT
264#define TIM2_INT MX1_TIM2_INT
265#define TIM1_INT MX1_TIM1_INT
266#define DMA_ERR MX1_DMA_ERR
267#define DMA_INT MX1_DMA_INT
268#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
269#define WDT_INT MX1_WDT_INT
270#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
271#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
272#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
273#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
274#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
275#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
276#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
277#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
278#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
279#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
280#define DMA_REQ_EXT MX1_DMA_REQ_EXT
281#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
282#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
283#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
284#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
285#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
286#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
287#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
288#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
289#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
290#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
291#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
292#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
293#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
294#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
295#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
296
297#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
new file mode 100644
index 000000000000..22d0b596262c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2009 Martin Fuzzey <mfuzzey@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __ASM_ARCH_MX21_USBH
16#define __ASM_ARCH_MX21_USBH
17
18enum mx21_usbh_xcvr {
19 /* Values below as used by hardware (HWMODE register) */
20 MX21_USBXCVR_TXDIF_RXDIF = 0,
21 MX21_USBXCVR_TXDIF_RXSE = 1,
22 MX21_USBXCVR_TXSE_RXDIF = 2,
23 MX21_USBXCVR_TXSE_RXSE = 3,
24};
25
26struct mx21_usbh_platform_data {
27 enum mx21_usbh_xcvr host_xcvr; /* tranceiver mode host 1,2 ports */
28 enum mx21_usbh_xcvr otg_xcvr; /* tranceiver mode otg (as host) port */
29 u16 enable_host1:1,
30 enable_host2:1,
31 enable_otg_host:1, /* enable "OTG" port (as host) */
32 host1_xcverless:1, /* traceiverless host1 port */
33 host1_txenoe:1, /* output enable host1 transmit enable */
34 otg_ext_xcvr:1, /* external tranceiver for OTG port */
35 unused:10;
36};
37
38#endif /* __ASM_ARCH_MX21_USBH */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 21112c695ec5..ed98b9c9f389 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -22,49 +22,201 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#ifndef __ASM_ARCH_MXC_MX21_H__ 25#ifndef __MACH_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__ 26#define __MACH_MX21_H__
27
28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30#define MX21_AIPI_SIZE SZ_1M
31#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
33#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
34#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
35#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
36#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
37#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
38#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
39#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
40#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
41#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
42#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
43#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
44#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
45#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
46#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
47#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
48#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
49#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
50#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
51#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
52#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
53#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
54#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
55#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
56#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
57#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
58#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
59#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
60#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
61#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
62#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
63
64#define MX21_AVIC_BASE_ADDR 0x10040000
65
66#define MX21_SAHB1_BASE_ADDR 0x80000000
67#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68#define MX21_SAHB1_SIZE SZ_1M
69#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
27 70
28/* Memory regions and CS */ 71/* Memory regions and CS */
29#define SDRAM_BASE_ADDR 0xC0000000 72#define MX21_SDRAM_BASE_ADDR 0xc0000000
30#define CSD1_BASE_ADDR 0xC4000000 73#define MX21_CSD1_BASE_ADDR 0xc4000000
31 74
32#define CS0_BASE_ADDR 0xC8000000 75#define MX21_CS0_BASE_ADDR 0xc8000000
33#define CS1_BASE_ADDR 0xCC000000 76#define MX21_CS1_BASE_ADDR 0xcc000000
34#define CS2_BASE_ADDR 0xD0000000 77#define MX21_CS2_BASE_ADDR 0xd0000000
35#define CS3_BASE_ADDR 0xD1000000 78#define MX21_CS3_BASE_ADDR 0xd1000000
36#define CS4_BASE_ADDR 0xD2000000 79#define MX21_CS4_BASE_ADDR 0xd2000000
37#define CS5_BASE_ADDR 0xDD000000 80#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
38#define PCMCIA_MEM_BASE_ADDR 0xD4000000 81#define MX21_CS5_BASE_ADDR 0xdd000000
39 82
40/* NAND, SDRAM, WEIM etc controllers */ 83/* NAND, SDRAM, WEIM etc controllers */
41#define X_MEMC_BASE_ADDR 0xDF000000 84#define MX21_X_MEMC_BASE_ADDR 0xdf000000
42#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 85#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
43#define X_MEMC_SIZE SZ_256K 86#define MX21_X_MEMC_SIZE SZ_256K
44 87
45#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 88#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
46#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 89#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
47#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 90#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
48#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 91#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
49 92
50#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ 93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94
95#define MX21_IO_ADDRESS(x) ( \
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
51 99
52/* fixed interrupt numbers */ 100/* fixed interrupt numbers */
53#define MXC_INT_USBCTRL 58 101#define MX21_INT_CSPI3 6
54#define MXC_INT_USBCTRL 58 102#define MX21_INT_GPIO 8
55#define MXC_INT_USBMNP 57 103#define MX21_INT_FIRI 9
56#define MXC_INT_USBFUNC 56 104#define MX21_INT_SDHC2 10
57#define MXC_INT_USBHOST 55 105#define MX21_INT_SDHC1 11
58#define MXC_INT_USBDMA 54 106#define MX21_INT_I2C 12
59#define MXC_INT_USBWKUP 53 107#define MX21_INT_SSI2 13
60#define MXC_INT_EMMADEC 50 108#define MX21_INT_SSI1 14
61#define MXC_INT_EMMAENC 49 109#define MX21_INT_CSPI2 15
62#define MXC_INT_BMI 30 110#define MX21_INT_CSPI1 16
63#define MXC_INT_FIRI 9 111#define MX21_INT_UART4 17
112#define MX21_INT_UART3 18
113#define MX21_INT_UART2 19
114#define MX21_INT_UART1 20
115#define MX21_INT_KPP 21
116#define MX21_INT_RTC 22
117#define MX21_INT_PWM 23
118#define MX21_INT_GPT3 24
119#define MX21_INT_GPT2 25
120#define MX21_INT_GPT1 26
121#define MX21_INT_WDOG 27
122#define MX21_INT_PCMCIA 28
123#define MX21_INT_NANDFC 29
124#define MX21_INT_BMI 30
125#define MX21_INT_CSI 31
126#define MX21_INT_DMACH0 32
127#define MX21_INT_DMACH1 33
128#define MX21_INT_DMACH2 34
129#define MX21_INT_DMACH3 35
130#define MX21_INT_DMACH4 36
131#define MX21_INT_DMACH5 37
132#define MX21_INT_DMACH6 38
133#define MX21_INT_DMACH7 39
134#define MX21_INT_DMACH8 40
135#define MX21_INT_DMACH9 41
136#define MX21_INT_DMACH10 42
137#define MX21_INT_DMACH11 43
138#define MX21_INT_DMACH12 44
139#define MX21_INT_DMACH13 45
140#define MX21_INT_DMACH14 46
141#define MX21_INT_DMACH15 47
142#define MX21_INT_EMMAENC 49
143#define MX21_INT_EMMADEC 50
144#define MX21_INT_EMMAPRP 51
145#define MX21_INT_EMMAPP 52
146#define MX21_INT_USBWKUP 53
147#define MX21_INT_USBDMA 54
148#define MX21_INT_USBHOST 55
149#define MX21_INT_USBFUNC 56
150#define MX21_INT_USBMNP 57
151#define MX21_INT_USBCTRL 58
152#define MX21_INT_SLCDC 60
153#define MX21_INT_LCDC 61
64 154
65/* fixed DMA request numbers */ 155/* fixed DMA request numbers */
66#define DMA_REQ_BMI_RX 29 156#define MX21_DMA_REQ_CSPI3_RX 1
67#define DMA_REQ_BMI_TX 28 157#define MX21_DMA_REQ_CSPI3_TX 2
68#define DMA_REQ_FIRI_RX 4 158#define MX21_DMA_REQ_EXT 3
159#define MX21_DMA_REQ_FIRI_RX 4
160#define MX21_DMA_REQ_SDHC2 6
161#define MX21_DMA_REQ_SDHC1 7
162#define MX21_DMA_REQ_SSI2_RX0 8
163#define MX21_DMA_REQ_SSI2_TX0 9
164#define MX21_DMA_REQ_SSI2_RX1 10
165#define MX21_DMA_REQ_SSI2_TX1 11
166#define MX21_DMA_REQ_SSI1_RX0 12
167#define MX21_DMA_REQ_SSI1_TX0 13
168#define MX21_DMA_REQ_SSI1_RX1 14
169#define MX21_DMA_REQ_SSI1_TX1 15
170#define MX21_DMA_REQ_CSPI2_RX 16
171#define MX21_DMA_REQ_CSPI2_TX 17
172#define MX21_DMA_REQ_CSPI1_RX 18
173#define MX21_DMA_REQ_CSPI1_TX 19
174#define MX21_DMA_REQ_UART4_RX 20
175#define MX21_DMA_REQ_UART4_TX 21
176#define MX21_DMA_REQ_UART3_RX 22
177#define MX21_DMA_REQ_UART3_TX 23
178#define MX21_DMA_REQ_UART2_RX 24
179#define MX21_DMA_REQ_UART2_TX 25
180#define MX21_DMA_REQ_UART1_RX 26
181#define MX21_DMA_REQ_UART1_TX 27
182#define MX21_DMA_REQ_BMI_TX 28
183#define MX21_DMA_REQ_BMI_RX 29
184#define MX21_DMA_REQ_CSI_STAT 30
185#define MX21_DMA_REQ_CSI_RX 31
186
187#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
188/* these should go away */
189#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
190#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
191#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
192#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
193#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
194#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
195#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
196#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
197#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
198#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
199#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
200#define X_MEMC_SIZE MX21_X_MEMC_SIZE
201#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
202#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
203#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
204#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
205#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
206#define MXC_INT_FIRI MX21_INT_FIRI
207#define MXC_INT_BMI MX21_INT_BMI
208#define MXC_INT_EMMAENC MX21_INT_EMMAENC
209#define MXC_INT_EMMADEC MX21_INT_EMMADEC
210#define MXC_INT_USBWKUP MX21_INT_USBWKUP
211#define MXC_INT_USBDMA MX21_INT_USBDMA
212#define MXC_INT_USBHOST MX21_INT_USBHOST
213#define MXC_INT_USBFUNC MX21_INT_USBFUNC
214#define MXC_INT_USBMNP MX21_INT_USBMNP
215#define MXC_INT_USBCTRL MX21_INT_USBCTRL
216#define MXC_INT_USBCTRL MX21_INT_USBCTRL
217#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
218#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
219#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220#endif
69 221
70#endif /* __ASM_ARCH_MXC_MX21_H__ */ 222#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ec64bd9a8ab1..4eb6e334bda5 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -1,14 +1,14 @@
1#ifndef __MACH_MX25_H__ 1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__ 2#define __MACH_MX25_H__
3 3
4#define MX25_AIPS1_BASE_ADDR 0x43F00000 4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000 5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
6#define MX25_AIPS1_SIZE SZ_1M 6#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53F00000 7#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000 8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9#define MX25_AIPS2_SIZE SZ_1M 9#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000 10#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 12#define MX25_AVIC_SIZE SZ_1M
13 13
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
@@ -22,23 +22,27 @@
22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) 22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) 23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
24 24
25#define MX25_AIPS1_IO_ADDRESS(x) \ 25#define MX25_IO_ADDRESS(x) ( \
26 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) 26 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
27#define MX25_AIPS2_IO_ADDRESS(x) \ 27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
28 (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) 28 IMX_IO_ADDRESS(x, MX25_AVIC))
29#define MX25_AVIC_IO_ADDRESS(x) \
30 (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
31 29
32#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) 30#define MX25_UART1_BASE_ADDR 0x43f90000
31#define MX25_UART2_BASE_ADDR 0x43f94000
33 32
34#define MX25_IO_ADDRESS(x) \ 33#define MX25_FEC_BASE_ADDR 0x50038000
35 (void __force __iomem *) \ 34#define MX25_NFC_BASE_ADDR 0xbb000000
36 (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \ 35#define MX25_DRYICE_BASE_ADDR 0x53ffc000
37 __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \ 36#define MX25_LCDC_BASE_ADDR 0x53fbc000
38 __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
39 0xDEADBEEF)
40 37
41#define UART1_BASE_ADDR 0x43f90000 38#define MX25_INT_DRYICE 25
42#define UART2_BASE_ADDR 0x43f94000 39#define MX25_INT_FEC 57
40#define MX25_INT_NANDFC 33
41#define MX25_INT_LCDC 39
43 42
44#endif /* __MACH_MX25_H__ */ 43#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
44#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
45#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR
46#endif
47
48#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index dc3ad9aa952a..bae9cd75beee 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -21,90 +21,225 @@
21 * MA 02110-1301, USA. 21 * MA 02110-1301, USA.
22 */ 22 */
23 23
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __MACH_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __MACH_MX27_H__
26 26
27/* IRAM */ 27#ifndef __ASSEMBLER__
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 28#include <linux/io.h>
29 29#endif
30#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) 30
31#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) 31#define MX27_AIPI_BASE_ADDR 0x10000000
32#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) 32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
33#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000) 33#define MX27_AIPI_SIZE SZ_1M
34#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000) 34#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
35#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) 35#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
36#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) 36#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
37#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) 37#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
38#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) 38#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
39#define OTG_BASE_ADDR USBOTG_BASE_ADDR 39#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
40#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 40#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
41#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 41#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
42#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) 42#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
43#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) 43#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
44#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) 44#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
45#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) 45#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
46#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) 46#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
47#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
51#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
55#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
56#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
57#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
58#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
59#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
60#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
61#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
62#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
63#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
64#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
65#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
66#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
67#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
68#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
69#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
70#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
71#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
72#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
73#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
74#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
75#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
76#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
77#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
78#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
79#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
80#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
81#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
82#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
83
84#define MX27_AVIC_BASE_ADDR 0x10040000
47 85
48/* ROM patch */ 86/* ROM patch */
49#define ROMP_BASE_ADDR 0x10041000 87#define MX27_ROMP_BASE_ADDR 0x10041000
50 88
51#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) 89#define MX27_SAHB1_BASE_ADDR 0x80000000
90#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
91#define MX27_SAHB1_SIZE SZ_1M
92#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
93#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
52 94
53/* Memory regions and CS */ 95/* Memory regions and CS */
54#define SDRAM_BASE_ADDR 0xA0000000 96#define MX27_SDRAM_BASE_ADDR 0xa0000000
55#define CSD1_BASE_ADDR 0xB0000000 97#define MX27_CSD1_BASE_ADDR 0xb0000000
56 98
57#define CS0_BASE_ADDR 0xC0000000 99#define MX27_CS0_BASE_ADDR 0xc0000000
58#define CS1_BASE_ADDR 0xC8000000 100#define MX27_CS1_BASE_ADDR 0xc8000000
59#define CS2_BASE_ADDR 0xD0000000 101#define MX27_CS2_BASE_ADDR 0xd0000000
60#define CS3_BASE_ADDR 0xD2000000 102#define MX27_CS3_BASE_ADDR 0xd2000000
61#define CS4_BASE_ADDR 0xD4000000 103#define MX27_CS4_BASE_ADDR 0xd4000000
62#define CS5_BASE_ADDR 0xD6000000 104#define MX27_CS5_BASE_ADDR 0xd6000000
63#define PCMCIA_MEM_BASE_ADDR 0xDC000000
64 105
65/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 106/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
66#define X_MEMC_BASE_ADDR 0xD8000000 107#define MX27_X_MEMC_BASE_ADDR 0xd8000000
67#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 108#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
68#define X_MEMC_SIZE SZ_1M 109#define MX27_X_MEMC_SIZE SZ_1M
110#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
112#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
113#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
114#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
115
116#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
69 120
70#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) 121#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
71#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 122
72#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 123/* IRAM */
73#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
74#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) 125
126#define MX27_IO_ADDRESS(x) ( \
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130
131#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
138}
139#endif
75 140
76/* fixed interrupt numbers */ 141/* fixed interrupt numbers */
77#define MXC_INT_CCM 63 142#define MX27_INT_I2C2 1
78#define MXC_INT_IIM 62 143#define MX27_INT_GPT6 2
79#define MXC_INT_SAHARA 59 144#define MX27_INT_GPT5 3
80#define MXC_INT_SCC_SCM 58 145#define MX27_INT_GPT4 4
81#define MXC_INT_SCC_SMN 57 146#define MX27_INT_RTIC 5
82#define MXC_INT_USB3 56 147#define MX27_INT_CSPI3 6
83#define MXC_INT_USB2 55 148#define MX27_INT_SDHC 7
84#define MXC_INT_USB1 54 149#define MX27_INT_GPIO 8
85#define MXC_INT_VPU 53 150#define MX27_INT_SDHC3 9
86#define MXC_INT_FEC 50 151#define MX27_INT_SDHC2 10
87#define MXC_INT_UART5 49 152#define MX27_INT_SDHC1 11
88#define MXC_INT_UART6 48 153#define MX27_INT_I2C 12
89#define MXC_INT_ATA 30 154#define MX27_INT_SSI2 13
90#define MXC_INT_SDHC3 9 155#define MX27_INT_SSI1 14
91#define MXC_INT_SDHC 7 156#define MX27_INT_CSPI2 15
92#define MXC_INT_RTIC 5 157#define MX27_INT_CSPI1 16
93#define MXC_INT_GPT4 4 158#define MX27_INT_UART4 17
94#define MXC_INT_GPT5 3 159#define MX27_INT_UART3 18
95#define MXC_INT_GPT6 2 160#define MX27_INT_UART2 19
96#define MXC_INT_I2C2 1 161#define MX27_INT_UART1 20
162#define MX27_INT_KPP 21
163#define MX27_INT_RTC 22
164#define MX27_INT_PWM 23
165#define MX27_INT_GPT3 24
166#define MX27_INT_GPT2 25
167#define MX27_INT_GPT1 26
168#define MX27_INT_WDOG 27
169#define MX27_INT_PCMCIA 28
170#define MX27_INT_NANDFC 29
171#define MX27_INT_ATA 30
172#define MX27_INT_CSI 31
173#define MX27_INT_DMACH0 32
174#define MX27_INT_DMACH1 33
175#define MX27_INT_DMACH2 34
176#define MX27_INT_DMACH3 35
177#define MX27_INT_DMACH4 36
178#define MX27_INT_DMACH5 37
179#define MX27_INT_DMACH6 38
180#define MX27_INT_DMACH7 39
181#define MX27_INT_DMACH8 40
182#define MX27_INT_DMACH9 41
183#define MX27_INT_DMACH10 42
184#define MX27_INT_DMACH11 43
185#define MX27_INT_DMACH12 44
186#define MX27_INT_DMACH13 45
187#define MX27_INT_DMACH14 46
188#define MX27_INT_DMACH15 47
189#define MX27_INT_UART6 48
190#define MX27_INT_UART5 49
191#define MX27_INT_FEC 50
192#define MX27_INT_EMMAPRP 51
193#define MX27_INT_EMMAPP 52
194#define MX27_INT_VPU 53
195#define MX27_INT_USB1 54
196#define MX27_INT_USB2 55
197#define MX27_INT_USB3 56
198#define MX27_INT_SCC_SMN 57
199#define MX27_INT_SCC_SCM 58
200#define MX27_INT_SAHARA 59
201#define MX27_INT_SLCDC 60
202#define MX27_INT_LCDC 61
203#define MX27_INT_IIM 62
204#define MX27_INT_CCM 63
97 205
98/* fixed DMA request numbers */ 206/* fixed DMA request numbers */
99#define DMA_REQ_NFC 37 207#define MX27_DMA_REQ_CSPI3_RX 1
100#define DMA_REQ_SDHC3 36 208#define MX27_DMA_REQ_CSPI3_TX 2
101#define DMA_REQ_UART6_RX 35 209#define MX27_DMA_REQ_EXT 3
102#define DMA_REQ_UART6_TX 34 210#define MX27_DMA_REQ_MSHC 4
103#define DMA_REQ_UART5_RX 33 211#define MX27_DMA_REQ_SDHC2 6
104#define DMA_REQ_UART5_TX 32 212#define MX27_DMA_REQ_SDHC1 7
105#define DMA_REQ_ATA_RCV 29 213#define MX27_DMA_REQ_SSI2_RX0 8
106#define DMA_REQ_ATA_TX 28 214#define MX27_DMA_REQ_SSI2_TX0 9
107#define DMA_REQ_MSHC 4 215#define MX27_DMA_REQ_SSI2_RX1 10
216#define MX27_DMA_REQ_SSI2_TX1 11
217#define MX27_DMA_REQ_SSI1_RX0 12
218#define MX27_DMA_REQ_SSI1_TX0 13
219#define MX27_DMA_REQ_SSI1_RX1 14
220#define MX27_DMA_REQ_SSI1_TX1 15
221#define MX27_DMA_REQ_CSPI2_RX 16
222#define MX27_DMA_REQ_CSPI2_TX 17
223#define MX27_DMA_REQ_CSPI1_RX 18
224#define MX27_DMA_REQ_CSPI1_TX 19
225#define MX27_DMA_REQ_UART4_RX 20
226#define MX27_DMA_REQ_UART4_TX 21
227#define MX27_DMA_REQ_UART3_RX 22
228#define MX27_DMA_REQ_UART3_TX 23
229#define MX27_DMA_REQ_UART2_RX 24
230#define MX27_DMA_REQ_UART2_TX 25
231#define MX27_DMA_REQ_UART1_RX 26
232#define MX27_DMA_REQ_UART1_TX 27
233#define MX27_DMA_REQ_ATA_TX 28
234#define MX27_DMA_REQ_ATA_RCV 29
235#define MX27_DMA_REQ_CSI_STAT 30
236#define MX27_DMA_REQ_CSI_RX 31
237#define MX27_DMA_REQ_UART5_TX 32
238#define MX27_DMA_REQ_UART5_RX 33
239#define MX27_DMA_REQ_UART6_TX 34
240#define MX27_DMA_REQ_UART6_RX 35
241#define MX27_DMA_REQ_SDHC3 36
242#define MX27_DMA_REQ_NFC 37
108 243
109/* silicon revisions specific to i.MX27 */ 244/* silicon revisions specific to i.MX27 */
110#define CHIP_REV_1_0 0x00 245#define CHIP_REV_1_0 0x00
@@ -114,6 +249,74 @@
114extern int mx27_revision(void); 249extern int mx27_revision(void);
115#endif 250#endif
116 251
117/* Mandatory defines used globally */ 252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
253/* these should go away */
254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
256#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
257#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
258#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
259#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
260#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
261#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
262#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
263#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
264#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
265#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
266#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
267#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
268#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
269#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
270#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
271#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
272#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
273#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
274#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
275#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
276#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
277#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
278#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
279#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
280#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
281#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
282#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
283#define X_MEMC_SIZE MX27_X_MEMC_SIZE
284#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
285#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
286#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
287#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
288#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
289#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
290#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
291#define MXC_INT_I2C2 MX27_INT_I2C2
292#define MXC_INT_GPT6 MX27_INT_GPT6
293#define MXC_INT_GPT5 MX27_INT_GPT5
294#define MXC_INT_GPT4 MX27_INT_GPT4
295#define MXC_INT_RTIC MX27_INT_RTIC
296#define MXC_INT_SDHC MX27_INT_SDHC
297#define MXC_INT_SDHC3 MX27_INT_SDHC3
298#define MXC_INT_ATA MX27_INT_ATA
299#define MXC_INT_UART6 MX27_INT_UART6
300#define MXC_INT_UART5 MX27_INT_UART5
301#define MXC_INT_FEC MX27_INT_FEC
302#define MXC_INT_VPU MX27_INT_VPU
303#define MXC_INT_USB1 MX27_INT_USB1
304#define MXC_INT_USB2 MX27_INT_USB2
305#define MXC_INT_USB3 MX27_INT_USB3
306#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
307#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
308#define MXC_INT_SAHARA MX27_INT_SAHARA
309#define MXC_INT_IIM MX27_INT_IIM
310#define MXC_INT_CCM MX27_INT_CCM
311#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
312#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
313#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
314#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
315#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
316#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
118 321
119#endif /* __ASM_ARCH_MXC_MX27_H__ */ 322#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921e0fe6..afb895a0b5b8 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -20,56 +20,54 @@
20 * MA 02110-1301, USA. 20 * MA 02110-1301, USA.
21 */ 21 */
22 22
23#ifndef __ASM_ARCH_MXC_MX2x_H__ 23#ifndef __MACH_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__ 24#define __MACH_MX2x_H__
25 25
26/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
27 27
28/* Register offests */ 28/* Register offsets */
29#define AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define AIPI_BASE_ADDR_VIRT 0xF4000000 30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
31#define AIPI_SIZE SZ_1M 31#define MX2x_AIPI_SIZE SZ_1M
32 32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) 33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
34#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) 34#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
35#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) 35#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
36#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) 36#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
37#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) 37#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
38#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) 38#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
39#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) 39#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
40#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) 40#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
41#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) 41#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
42#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) 42#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
43#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) 43#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
44#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) 44#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
45#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) 45#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
46#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) 46#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
47#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) 47#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
48#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) 48#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
49#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) 49#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
50#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) 50#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
51#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) 51#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
52#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) 52#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
53#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) 53#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
54#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) 54#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
55#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) 55#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
56#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) 56#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
57#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) 57#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
58#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) 58#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
59#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) 59#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
60#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) 60#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
61#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) 61#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
62#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) 62#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
63#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 63#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
64#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) 64
65 65#define MX2x_AVIC_BASE_ADDR 0x10040000
66#define AVIC_BASE_ADDR 0x10040000 66
67 67#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define SAHB1_BASE_ADDR 0x80000000 68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define SAHB1_BASE_ADDR_VIRT 0xF4100000 69#define MX2x_SAHB1_SIZE SZ_1M
70#define SAHB1_SIZE SZ_1M 70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71
72#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
73 71
74/* 72/*
75 * This macro defines the physical to virtual address mapping for all the 73 * This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,191 @@
105 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
106 104
107/* fixed interrupt numbers */ 105/* fixed interrupt numbers */
108#define MXC_INT_LCDC 61 106#define MX2x_INT_CSPI3 6
109#define MXC_INT_SLCDC 60 107#define MX2x_INT_GPIO 8
110#define MXC_INT_EMMAPP 52 108#define MX2x_INT_SDHC2 10
111#define MXC_INT_EMMAPRP 51 109#define MX2x_INT_SDHC1 11
112#define MXC_INT_DMACH15 47 110#define MX2x_INT_I2C 12
113#define MXC_INT_DMACH14 46 111#define MX2x_INT_SSI2 13
114#define MXC_INT_DMACH13 45 112#define MX2x_INT_SSI1 14
115#define MXC_INT_DMACH12 44 113#define MX2x_INT_CSPI2 15
116#define MXC_INT_DMACH11 43 114#define MX2x_INT_CSPI1 16
117#define MXC_INT_DMACH10 42 115#define MX2x_INT_UART4 17
118#define MXC_INT_DMACH9 41 116#define MX2x_INT_UART3 18
119#define MXC_INT_DMACH8 40 117#define MX2x_INT_UART2 19
120#define MXC_INT_DMACH7 39 118#define MX2x_INT_UART1 20
121#define MXC_INT_DMACH6 38 119#define MX2x_INT_KPP 21
122#define MXC_INT_DMACH5 37 120#define MX2x_INT_RTC 22
123#define MXC_INT_DMACH4 36 121#define MX2x_INT_PWM 23
124#define MXC_INT_DMACH3 35 122#define MX2x_INT_GPT3 24
125#define MXC_INT_DMACH2 34 123#define MX2x_INT_GPT2 25
126#define MXC_INT_DMACH1 33 124#define MX2x_INT_GPT1 26
127#define MXC_INT_DMACH0 32 125#define MX2x_INT_WDOG 27
128#define MXC_INT_CSI 31 126#define MX2x_INT_PCMCIA 28
129#define MXC_INT_NANDFC 29 127#define MX2x_INT_NANDFC 29
130#define MXC_INT_PCMCIA 28 128#define MX2x_INT_CSI 31
131#define MXC_INT_WDOG 27 129#define MX2x_INT_DMACH0 32
132#define MXC_INT_GPT1 26 130#define MX2x_INT_DMACH1 33
133#define MXC_INT_GPT2 25 131#define MX2x_INT_DMACH2 34
134#define MXC_INT_GPT3 24 132#define MX2x_INT_DMACH3 35
135#define MXC_INT_GPT INT_GPT1 133#define MX2x_INT_DMACH4 36
136#define MXC_INT_PWM 23 134#define MX2x_INT_DMACH5 37
137#define MXC_INT_RTC 22 135#define MX2x_INT_DMACH6 38
138#define MXC_INT_KPP 21 136#define MX2x_INT_DMACH7 39
139#define MXC_INT_UART1 20 137#define MX2x_INT_DMACH8 40
140#define MXC_INT_UART2 19 138#define MX2x_INT_DMACH9 41
141#define MXC_INT_UART3 18 139#define MX2x_INT_DMACH10 42
142#define MXC_INT_UART4 17 140#define MX2x_INT_DMACH11 43
143#define MXC_INT_CSPI1 16 141#define MX2x_INT_DMACH12 44
144#define MXC_INT_CSPI2 15 142#define MX2x_INT_DMACH13 45
145#define MXC_INT_SSI1 14 143#define MX2x_INT_DMACH14 46
146#define MXC_INT_SSI2 13 144#define MX2x_INT_DMACH15 47
147#define MXC_INT_I2C 12 145#define MX2x_INT_EMMAPRP 51
148#define MXC_INT_SDHC1 11 146#define MX2x_INT_EMMAPP 52
149#define MXC_INT_SDHC2 10 147#define MX2x_INT_SLCDC 60
150#define MXC_INT_GPIO 8 148#define MX2x_INT_LCDC 61
151#define MXC_INT_CSPI3 6
152 149
153/* fixed DMA request numbers */ 150/* fixed DMA request numbers */
154#define DMA_REQ_CSI_RX 31 151#define MX2x_DMA_REQ_CSPI3_RX 1
155#define DMA_REQ_CSI_STAT 30 152#define MX2x_DMA_REQ_CSPI3_TX 2
156#define DMA_REQ_UART1_TX 27 153#define MX2x_DMA_REQ_EXT 3
157#define DMA_REQ_UART1_RX 26 154#define MX2x_DMA_REQ_SDHC2 6
158#define DMA_REQ_UART2_TX 25 155#define MX2x_DMA_REQ_SDHC1 7
159#define DMA_REQ_UART2_RX 24 156#define MX2x_DMA_REQ_SSI2_RX0 8
160#define DMA_REQ_UART3_TX 23 157#define MX2x_DMA_REQ_SSI2_TX0 9
161#define DMA_REQ_UART3_RX 22 158#define MX2x_DMA_REQ_SSI2_RX1 10
162#define DMA_REQ_UART4_TX 21 159#define MX2x_DMA_REQ_SSI2_TX1 11
163#define DMA_REQ_UART4_RX 20 160#define MX2x_DMA_REQ_SSI1_RX0 12
164#define DMA_REQ_CSPI1_TX 19 161#define MX2x_DMA_REQ_SSI1_TX0 13
165#define DMA_REQ_CSPI1_RX 18 162#define MX2x_DMA_REQ_SSI1_RX1 14
166#define DMA_REQ_CSPI2_TX 17 163#define MX2x_DMA_REQ_SSI1_TX1 15
167#define DMA_REQ_CSPI2_RX 16 164#define MX2x_DMA_REQ_CSPI2_RX 16
168#define DMA_REQ_SSI1_TX1 15 165#define MX2x_DMA_REQ_CSPI2_TX 17
169#define DMA_REQ_SSI1_RX1 14 166#define MX2x_DMA_REQ_CSPI1_RX 18
170#define DMA_REQ_SSI1_TX0 13 167#define MX2x_DMA_REQ_CSPI1_TX 19
171#define DMA_REQ_SSI1_RX0 12 168#define MX2x_DMA_REQ_UART4_RX 20
172#define DMA_REQ_SSI2_TX1 11 169#define MX2x_DMA_REQ_UART4_TX 21
173#define DMA_REQ_SSI2_RX1 10 170#define MX2x_DMA_REQ_UART3_RX 22
174#define DMA_REQ_SSI2_TX0 9 171#define MX2x_DMA_REQ_UART3_TX 23
175#define DMA_REQ_SSI2_RX0 8 172#define MX2x_DMA_REQ_UART2_RX 24
176#define DMA_REQ_SDHC1 7 173#define MX2x_DMA_REQ_UART2_TX 25
177#define DMA_REQ_SDHC2 6 174#define MX2x_DMA_REQ_UART1_RX 26
178#define DMA_REQ_EXT 3 175#define MX2x_DMA_REQ_UART1_TX 27
179#define DMA_REQ_CSPI3_TX 2 176#define MX2x_DMA_REQ_CSI_STAT 30
180#define DMA_REQ_CSPI3_RX 1 177#define MX2x_DMA_REQ_CSI_RX 31
181 178
182#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 179#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
180/* these should go away */
181#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
182#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
183#define AIPI_SIZE MX2x_AIPI_SIZE
184#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
185#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
186#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
187#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
188#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
189#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
190#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
191#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
192#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
193#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
194#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
195#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
196#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
197#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
198#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
199#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
200#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
201#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
202#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
203#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
204#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
205#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
206#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
207#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
208#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
209#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
210#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
211#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
212#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
213#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
214#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
215#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
216#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
217#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
218#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
219#define SAHB1_SIZE MX2x_SAHB1_SIZE
220#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
221#define MXC_INT_CSPI3 MX2x_INT_CSPI3
222#define MXC_INT_GPIO MX2x_INT_GPIO
223#define MXC_INT_SDHC2 MX2x_INT_SDHC2
224#define MXC_INT_SDHC1 MX2x_INT_SDHC1
225#define MXC_INT_I2C MX2x_INT_I2C
226#define MXC_INT_SSI2 MX2x_INT_SSI2
227#define MXC_INT_SSI1 MX2x_INT_SSI1
228#define MXC_INT_CSPI2 MX2x_INT_CSPI2
229#define MXC_INT_CSPI1 MX2x_INT_CSPI1
230#define MXC_INT_UART4 MX2x_INT_UART4
231#define MXC_INT_UART3 MX2x_INT_UART3
232#define MXC_INT_UART2 MX2x_INT_UART2
233#define MXC_INT_UART1 MX2x_INT_UART1
234#define MXC_INT_KPP MX2x_INT_KPP
235#define MXC_INT_RTC MX2x_INT_RTC
236#define MXC_INT_PWM MX2x_INT_PWM
237#define MXC_INT_GPT3 MX2x_INT_GPT3
238#define MXC_INT_GPT2 MX2x_INT_GPT2
239#define MXC_INT_GPT1 MX2x_INT_GPT1
240#define MXC_INT_WDOG MX2x_INT_WDOG
241#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
242#define MXC_INT_NANDFC MX2x_INT_NANDFC
243#define MXC_INT_CSI MX2x_INT_CSI
244#define MXC_INT_DMACH0 MX2x_INT_DMACH0
245#define MXC_INT_DMACH1 MX2x_INT_DMACH1
246#define MXC_INT_DMACH2 MX2x_INT_DMACH2
247#define MXC_INT_DMACH3 MX2x_INT_DMACH3
248#define MXC_INT_DMACH4 MX2x_INT_DMACH4
249#define MXC_INT_DMACH5 MX2x_INT_DMACH5
250#define MXC_INT_DMACH6 MX2x_INT_DMACH6
251#define MXC_INT_DMACH7 MX2x_INT_DMACH7
252#define MXC_INT_DMACH8 MX2x_INT_DMACH8
253#define MXC_INT_DMACH9 MX2x_INT_DMACH9
254#define MXC_INT_DMACH10 MX2x_INT_DMACH10
255#define MXC_INT_DMACH11 MX2x_INT_DMACH11
256#define MXC_INT_DMACH12 MX2x_INT_DMACH12
257#define MXC_INT_DMACH13 MX2x_INT_DMACH13
258#define MXC_INT_DMACH14 MX2x_INT_DMACH14
259#define MXC_INT_DMACH15 MX2x_INT_DMACH15
260#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
261#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
262#define MXC_INT_SLCDC MX2x_INT_SLCDC
263#define MXC_INT_LCDC MX2x_INT_LCDC
264#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
265#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
266#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
267#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
268#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
269#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
270#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
271#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
272#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
273#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
274#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
275#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
276#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
277#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
278#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
279#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
280#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
281#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
282#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
283#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
284#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
285#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
286#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
287#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
288#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
289#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
290#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
291#endif
292
293#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 14ac0dcc82f4..fb90e119c2b5 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,45 +1,251 @@
1#ifndef __MACH_MX31_H__
2#define __MACH_MX31_H__
3
4#ifndef __ASSEMBLER__
5#include <linux/io.h>
6#endif
7
1/* 8/*
2 * IRAM 9 * IRAM
3 */ 10 */
4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 11#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
5#define MX31_IRAM_SIZE SZ_16K 12#define MX31_IRAM_SIZE SZ_16K
6 13
7#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 14#define MX31_L2CC_BASE_ADDR 0x30000000
8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 15#define MX31_L2CC_SIZE SZ_1M
9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 16
10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 17#define MX31_AIPS1_BASE_ADDR 0x43f00000
18#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
19#define MX31_AIPS1_SIZE SZ_1M
20#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
21#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
22#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
30#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
31#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
32#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
33#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
34#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
35#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
36#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
37#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
38#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
39#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
40#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
41#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
42
43#define MX31_SPBA0_BASE_ADDR 0x50000000
44#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
45#define MX31_SPBA0_SIZE SZ_1M
46#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
47#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
48#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
49#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
50#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
51#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
52#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
53#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
54#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
55#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
56
57#define MX31_AIPS2_BASE_ADDR 0x53f00000
58#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
59#define MX31_AIPS2_SIZE SZ_1M
60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
62#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
63#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
64#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
65#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
66#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
67#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
68#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
69#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
70#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
71#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
72#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
73#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
74#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
75#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
76#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
77#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
78#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
79#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
80#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
81
82#define MX31_ROMP_BASE_ADDR 0x60000000
83#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
84#define MX31_ROMP_SIZE SZ_1M
85
86#define MX31_AVIC_BASE_ADDR 0x68000000
87#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
88#define MX31_AVIC_SIZE SZ_1M
89
90#define MX31_IPU_MEM_BASE_ADDR 0x70000000
91#define MX31_CSD0_BASE_ADDR 0x80000000
92#define MX31_CSD1_BASE_ADDR 0x90000000
93
94#define MX31_CS0_BASE_ADDR 0xa0000000
95#define MX31_CS1_BASE_ADDR 0xa8000000
96#define MX31_CS2_BASE_ADDR 0xb0000000
97#define MX31_CS3_BASE_ADDR 0xb2000000
11 98
12#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 99#define MX31_CS4_BASE_ADDR 0xb4000000
13#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 100#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
14#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) 101#define MX31_CS4_SIZE SZ_32M
15#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
16 102
17#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 103#define MX31_CS5_BASE_ADDR 0xb6000000
18#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) 104#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
19#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) 105#define MX31_CS5_SIZE SZ_32M
20#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
21#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
22 106
23#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 107#define MX31_X_MEMC_BASE_ADDR 0xb8000000
108#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109#define MX31_X_MEMC_SIZE SZ_64K
110#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
112#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
113#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
114#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
115#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
24 116
25#define MXC_INT_MPEG4_ENCODER 5 117#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
26#define MXC_INT_FIRI 7 118#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
119#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121
122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
123
124#define MX31_IO_ADDRESS(x) ( \
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
130
131#ifndef __ASSEMBLER__
132static inline void mx31_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
138}
139#endif
140
141#define MX31_INT_I2C3 3
142#define MX31_INT_I2C2 4
143#define MX31_INT_MPEG4_ENCODER 5
144#define MX31_INT_RTIC 6
145#define MX31_INT_FIRI 7
27#define MX31_INT_MMC_SDHC2 8 146#define MX31_INT_MMC_SDHC2 8
28#define MXC_INT_MMC_SDHC1 9 147#define MX31_INT_MMC_SDHC1 9
148#define MX31_INT_I2C 10
29#define MX31_INT_SSI2 11 149#define MX31_INT_SSI2 11
30#define MX31_INT_SSI1 12 150#define MX31_INT_SSI1 12
31#define MXC_INT_MBX 16 151#define MX31_INT_CSPI2 13
32#define MXC_INT_CSPI3 17 152#define MX31_INT_CSPI1 14
33#define MXC_INT_SIM2 20 153#define MX31_INT_ATA 15
34#define MXC_INT_SIM1 21 154#define MX31_INT_MBX 16
35#define MXC_INT_CCM_DVFS 31 155#define MX31_INT_CSPI3 17
36#define MXC_INT_USB1 35 156#define MX31_INT_UART3 18
37#define MXC_INT_USB2 36 157#define MX31_INT_IIM 19
38#define MXC_INT_USB3 37 158#define MX31_INT_SIM2 20
39#define MXC_INT_USB4 38 159#define MX31_INT_SIM1 21
40#define MXC_INT_MSHC2 40 160#define MX31_INT_RNGA 22
41#define MXC_INT_UART4 46 161#define MX31_INT_EVTMON 23
42#define MXC_INT_UART5 47 162#define MX31_INT_KPP 24
43#define MXC_INT_CCM 53 163#define MX31_INT_RTC 25
44#define MXC_INT_PCMCIA 54 164#define MX31_INT_PWM 26
165#define MX31_INT_EPIT2 27
166#define MX31_INT_EPIT1 28
167#define MX31_INT_GPT 29
168#define MX31_INT_POWER_FAIL 30
169#define MX31_INT_CCM_DVFS 31
170#define MX31_INT_UART2 32
171#define MX31_INT_NANDFC 33
172#define MX31_INT_SDMA 34
173#define MX31_INT_USB1 35
174#define MX31_INT_USB2 36
175#define MX31_INT_USB3 37
176#define MX31_INT_USB4 38
177#define MX31_INT_MSHC1 39
178#define MX31_INT_MSHC2 40
179#define MX31_INT_IPU_ERR 41
180#define MX31_INT_IPU_SYN 42
181#define MX31_INT_UART1 45
182#define MX31_INT_UART4 46
183#define MX31_INT_UART5 47
184#define MX31_INT_ECT 48
185#define MX31_INT_SCC_SCM 49
186#define MX31_INT_SCC_SMN 50
187#define MX31_INT_GPIO2 51
188#define MX31_INT_GPIO1 52
189#define MX31_INT_CCM 53
190#define MX31_INT_PCMCIA 54
191#define MX31_INT_WDOG 55
192#define MX31_INT_GPIO3 56
193#define MX31_INT_EXT_POWER 58
194#define MX31_INT_EXT_TEMPER 59
195#define MX31_INT_EXT_SENSOR60 60
196#define MX31_INT_EXT_SENSOR61 61
197#define MX31_INT_EXT_WDOG 62
198#define MX31_INT_EXT_TV 63
199
200#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
201
202/* silicon revisions specific to i.MX31 */
203#define MX31_CHIP_REV_1_0 0x10
204#define MX31_CHIP_REV_1_1 0x11
205#define MX31_CHIP_REV_1_2 0x12
206#define MX31_CHIP_REV_1_3 0x13
207#define MX31_CHIP_REV_2_0 0x20
208#define MX31_CHIP_REV_2_1 0x21
209#define MX31_CHIP_REV_2_2 0x22
210#define MX31_CHIP_REV_2_3 0x23
211#define MX31_CHIP_REV_3_0 0x30
212#define MX31_CHIP_REV_3_1 0x31
213#define MX31_CHIP_REV_3_2 0x32
214
215#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
216#define MX31_SYSTEM_REV_NUM 3
217
218#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
219/* these should go away */
220#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
221#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
222#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
223#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
224#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
225#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
226#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
227#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
228#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
229#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
230#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
231#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
232#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
233#define MXC_INT_FIRI MX31_INT_FIRI
234#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
235#define MXC_INT_MBX MX31_INT_MBX
236#define MXC_INT_CSPI3 MX31_INT_CSPI3
237#define MXC_INT_SIM2 MX31_INT_SIM2
238#define MXC_INT_SIM1 MX31_INT_SIM1
239#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
240#define MXC_INT_USB1 MX31_INT_USB1
241#define MXC_INT_USB2 MX31_INT_USB2
242#define MXC_INT_USB3 MX31_INT_USB3
243#define MXC_INT_USB4 MX31_INT_USB4
244#define MXC_INT_MSHC2 MX31_INT_MSHC2
245#define MXC_INT_UART4 MX31_INT_UART4
246#define MXC_INT_UART5 MX31_INT_UART5
247#define MXC_INT_CCM MX31_INT_CCM
248#define MXC_INT_PCMCIA MX31_INT_PCMCIA
249#endif
45 250
251#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ab4cfec6c8ab..526a55842ae5 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,30 +1,210 @@
1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__
1/* 3/*
2 * IRAM 4 * IRAM
3 */ 5 */
4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ 6#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
5#define MX35_IRAM_SIZE SZ_128K 7#define MX35_IRAM_SIZE SZ_128K
6 8
7#define MXC_FEC_BASE_ADDR 0x50038000 9#define MX35_L2CC_BASE_ADDR 0x30000000
8#define MX35_OTG_BASE_ADDR 0x53ff4000 10#define MX35_L2CC_SIZE SZ_1M
9#define MX35_NFC_BASE_ADDR 0xBB000000 11
12#define MX35_AIPS1_BASE_ADDR 0x43f00000
13#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
14#define MX35_AIPS1_SIZE SZ_1M
15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
17#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
25#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
26#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
27#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
28#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
29#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
30#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
31#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
33
34#define MX35_SPBA0_BASE_ADDR 0x50000000
35#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
36#define MX35_SPBA0_SIZE SZ_1M
37#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
38#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
39#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
40#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
41#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
42#define MX35_FEC_BASE_ADDR 0x50038000
43#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
44
45#define MX35_AIPS2_BASE_ADDR 0x53f00000
46#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
47#define MX35_AIPS2_SIZE SZ_1M
48#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
49#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
50#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
51#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
52#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
53#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
54#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
55#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
56#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
57#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
58#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
59#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
60#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
61#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
62#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
63#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
64#define MX35_OTG_BASE_ADDR 0x53ff4000
65
66#define MX35_ROMP_BASE_ADDR 0x60000000
67#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
68#define MX35_ROMP_SIZE SZ_1M
69
70#define MX35_AVIC_BASE_ADDR 0x68000000
71#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
72#define MX35_AVIC_SIZE SZ_1M
73
74/*
75 * Memory regions and CS
76 */
77#define MX35_IPU_MEM_BASE_ADDR 0x70000000
78#define MX35_CSD0_BASE_ADDR 0x80000000
79#define MX35_CSD1_BASE_ADDR 0x90000000
80
81#define MX35_CS0_BASE_ADDR 0xa0000000
82#define MX35_CS1_BASE_ADDR 0xa8000000
83#define MX35_CS2_BASE_ADDR 0xb0000000
84#define MX35_CS3_BASE_ADDR 0xb2000000
85
86#define MX35_CS4_BASE_ADDR 0xb4000000
87#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
88#define MX35_CS4_SIZE SZ_32M
89
90#define MX35_CS5_BASE_ADDR 0xb6000000
91#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
92#define MX35_CS5_SIZE SZ_32M
93
94/*
95 * NAND, SDRAM, WEIM, M3IF, EMI controllers
96 */
97#define MX35_X_MEMC_BASE_ADDR 0xb8000000
98#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
99#define MX35_X_MEMC_SIZE SZ_64K
100#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
101#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
102#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
103#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
104#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
105
106#define MX35_NFC_BASE_ADDR 0xbb000000
107#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
108
109#define MX35_IO_ADDRESS(x) ( \
110 IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
111 IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
112 IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
113 IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
114 IMX_IO_ADDRESS(x, MX35_SPBA0))
10 115
11/* 116/*
12 * Interrupt numbers 117 * Interrupt numbers
13 */ 118 */
14#define MXC_INT_OWIRE 2 119#define MX35_INT_OWIRE 2
120#define MX35_INT_I2C3 3
121#define MX35_INT_I2C2 4
122#define MX35_INT_RTIC 6
15#define MX35_INT_MMC_SDHC1 7 123#define MX35_INT_MMC_SDHC1 7
16#define MXC_INT_MMC_SDHC2 8 124#define MX35_INT_MMC_SDHC2 8
17#define MXC_INT_MMC_SDHC3 9 125#define MX35_INT_MMC_SDHC3 9
126#define MX35_INT_I2C 10
18#define MX35_INT_SSI1 11 127#define MX35_INT_SSI1 11
19#define MX35_INT_SSI2 12 128#define MX35_INT_SSI2 12
20#define MXC_INT_GPU2D 16 129#define MX35_INT_CSPI2 13
21#define MXC_INT_ASRC 17 130#define MX35_INT_CSPI1 14
22#define MXC_INT_USBHS 35 131#define MX35_INT_ATA 15
23#define MXC_INT_USBOTG 37 132#define MX35_INT_GPU2D 16
24#define MXC_INT_ESAI 40 133#define MX35_INT_ASRC 17
25#define MXC_INT_CAN1 43 134#define MX35_INT_UART3 18
26#define MXC_INT_CAN2 44 135#define MX35_INT_IIM 19
27#define MXC_INT_MLB 46 136#define MX35_INT_RNGA 22
28#define MXC_INT_SPDIF 47 137#define MX35_INT_EVTMON 23
29#define MXC_INT_FEC 57 138#define MX35_INT_KPP 24
139#define MX35_INT_RTC 25
140#define MX35_INT_PWM 26
141#define MX35_INT_EPIT2 27
142#define MX35_INT_EPIT1 28
143#define MX35_INT_GPT 29
144#define MX35_INT_POWER_FAIL 30
145#define MX35_INT_UART2 32
146#define MX35_INT_NANDFC 33
147#define MX35_INT_SDMA 34
148#define MX35_INT_USBHS 35
149#define MX35_INT_USBOTG 37
150#define MX35_INT_MSHC1 39
151#define MX35_INT_ESAI 40
152#define MX35_INT_IPU_ERR 41
153#define MX35_INT_IPU_SYN 42
154#define MX35_INT_CAN1 43
155#define MX35_INT_CAN2 44
156#define MX35_INT_UART1 45
157#define MX35_INT_MLB 46
158#define MX35_INT_SPDIF 47
159#define MX35_INT_ECT 48
160#define MX35_INT_SCC_SCM 49
161#define MX35_INT_SCC_SMN 50
162#define MX35_INT_GPIO2 51
163#define MX35_INT_GPIO1 52
164#define MX35_INT_WDOG 55
165#define MX35_INT_GPIO3 56
166#define MX35_INT_FEC 57
167#define MX35_INT_EXT_POWER 58
168#define MX35_INT_EXT_TEMPER 59
169#define MX35_INT_EXT_SENSOR60 60
170#define MX35_INT_EXT_SENSOR61 61
171#define MX35_INT_EXT_WDOG 62
172#define MX35_INT_EXT_TV 63
173
174#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
175
176/* silicon revisions specific to i.MX31 */
177#define MX35_CHIP_REV_1_0 0x10
178#define MX35_CHIP_REV_1_1 0x11
179#define MX35_CHIP_REV_1_2 0x12
180#define MX35_CHIP_REV_1_3 0x13
181#define MX35_CHIP_REV_2_0 0x20
182#define MX35_CHIP_REV_2_1 0x21
183#define MX35_CHIP_REV_2_2 0x22
184#define MX35_CHIP_REV_2_3 0x23
185#define MX35_CHIP_REV_3_0 0x30
186#define MX35_CHIP_REV_3_1 0x31
187#define MX35_CHIP_REV_3_2 0x32
188
189#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
190#define MX35_SYSTEM_REV_NUM 3
191
192#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
193/* these should go away */
194#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
195#define MXC_INT_OWIRE MX35_INT_OWIRE
196#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
197#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
198#define MXC_INT_GPU2D MX35_INT_GPU2D
199#define MXC_INT_ASRC MX35_INT_ASRC
200#define MXC_INT_USBHS MX35_INT_USBHS
201#define MXC_INT_USBOTG MX35_INT_USBOTG
202#define MXC_INT_ESAI MX35_INT_ESAI
203#define MXC_INT_CAN1 MX35_INT_CAN1
204#define MXC_INT_CAN2 MX35_INT_CAN2
205#define MXC_INT_MLB MX35_INT_MLB
206#define MXC_INT_SPDIF MX35_INT_SPDIF
207#define MXC_INT_FEC MX35_INT_FEC
208#endif
30 209
210#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f4440276b..7a356de385f5 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARCH_MXC_MX31_H__ 11#ifndef __MACH_MX3x_H__
12#define __ASM_ARCH_MXC_MX31_H__ 12#define __MACH_MX3x_H__
13 13
14/* 14/*
15 * MX31 memory map: 15 * MX31 memory map:
@@ -34,120 +34,117 @@
34 * C0000000 64M PCMCIA/CF 34 * C0000000 64M PCMCIA/CF
35 */ 35 */
36 36
37#define CS0_BASE_ADDR 0xA0000000
38#define CS1_BASE_ADDR 0xA8000000
39#define CS2_BASE_ADDR 0xB0000000
40#define CS3_BASE_ADDR 0xB2000000
41
42#define CS4_BASE_ADDR 0xB4000000
43#define CS4_BASE_ADDR_VIRT 0xF4000000
44#define CS4_SIZE SZ_32M
45
46#define CS5_BASE_ADDR 0xB6000000
47#define CS5_BASE_ADDR_VIRT 0xF6000000
48#define CS5_SIZE SZ_32M
49
50#define PCMCIA_MEM_BASE_ADDR 0xBC000000
51
52/* 37/*
53 * L2CC 38 * L2CC
54 */ 39 */
55#define L2CC_BASE_ADDR 0x30000000 40#define MX3x_L2CC_BASE_ADDR 0x30000000
56#define L2CC_SIZE SZ_1M 41#define MX3x_L2CC_SIZE SZ_1M
57 42
58/* 43/*
59 * AIPS 1 44 * AIPS 1
60 */ 45 */
61#define AIPS1_BASE_ADDR 0x43F00000 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
62#define AIPS1_BASE_ADDR_VIRT 0xFC000000 47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
63#define AIPS1_SIZE SZ_1M 48#define MX3x_AIPS1_SIZE SZ_1M
64 49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
65#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) 50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
66#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) 51#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
67#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) 52#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
68#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) 53#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
69#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) 54#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
70#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) 55#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
71#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 56#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
72#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 57#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
73#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 58#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
74#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 59#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
75#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 60#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
76#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 61#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
77#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 62#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
78#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 63#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
79#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 64#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
80#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 65#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
81#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 66#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
82#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
83 67
84/* 68/*
85 * SPBA global module enabled #0 69 * SPBA global module enabled #0
86 */ 70 */
87#define SPBA0_BASE_ADDR 0x50000000 71#define MX3x_SPBA0_BASE_ADDR 0x50000000
88#define SPBA0_BASE_ADDR_VIRT 0xFC100000 72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
89#define SPBA0_SIZE SZ_1M 73#define MX3x_SPBA0_SIZE SZ_1M
90 74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
91#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) 75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
92#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 76#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
93#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 77#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
94#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 78#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
95#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 79#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
96#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
97 80
98/* 81/*
99 * AIPS 2 82 * AIPS 2
100 */ 83 */
101#define AIPS2_BASE_ADDR 0x53F00000 84#define MX3x_AIPS2_BASE_ADDR 0x53f00000
102#define AIPS2_BASE_ADDR_VIRT 0xFC200000 85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
103#define AIPS2_SIZE SZ_1M 86#define MX3x_AIPS2_SIZE SZ_1M
104#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
105#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) 88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
106#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 89#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
107#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 90#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
108#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 91#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
109#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 92#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
110#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 93#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
111#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 94#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
112#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 95#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
113#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 96#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
114#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 97#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
115#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) 98#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
116#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 99#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
117#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 100#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
118#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 101#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
119#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 102#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
120 103
121/* 104/*
122 * ROMP and AVIC 105 * ROMP and AVIC
123 */ 106 */
124#define ROMP_BASE_ADDR 0x60000000 107#define MX3x_ROMP_BASE_ADDR 0x60000000
125#define ROMP_BASE_ADDR_VIRT 0xFC500000 108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
126#define ROMP_SIZE SZ_1M 109#define MX3x_ROMP_SIZE SZ_1M
127 110
128#define AVIC_BASE_ADDR 0x68000000 111#define MX3x_AVIC_BASE_ADDR 0x68000000
129#define AVIC_BASE_ADDR_VIRT 0xFC400000 112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
130#define AVIC_SIZE SZ_1M 113#define MX3x_AVIC_SIZE SZ_1M
131 114
132/* 115/*
133 * NAND, SDRAM, WEIM, M3IF, EMI controllers 116 * Memory regions and CS
134 */ 117 */
135#define X_MEMC_BASE_ADDR 0xB8000000 118#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
136#define X_MEMC_BASE_ADDR_VIRT 0xFC320000 119#define MX3x_CSD0_BASE_ADDR 0x80000000
137#define X_MEMC_SIZE SZ_64K 120#define MX3x_CSD1_BASE_ADDR 0x90000000
138 121
139#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 122#define MX3x_CS0_BASE_ADDR 0xa0000000
140#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 123#define MX3x_CS1_BASE_ADDR 0xa8000000
141#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 124#define MX3x_CS2_BASE_ADDR 0xb0000000
142#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) 125#define MX3x_CS3_BASE_ADDR 0xb2000000
143#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR 126
127#define MX3x_CS4_BASE_ADDR 0xb4000000
128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
129#define MX3x_CS4_SIZE SZ_32M
130
131#define MX3x_CS5_BASE_ADDR 0xb6000000
132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
133#define MX3x_CS5_SIZE SZ_32M
144 134
145/* 135/*
146 * Memory regions and CS 136 * NAND, SDRAM, WEIM, M3IF, EMI controllers
147 */ 137 */
148#define IPU_MEM_BASE_ADDR 0x70000000 138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
149#define CSD0_BASE_ADDR 0x80000000 139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
150#define CSD1_BASE_ADDR 0x90000000 140#define MX3x_X_MEMC_SIZE SZ_64K
141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
143#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
144#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
145#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
146
147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
151 148
152/*! 149/*!
153 * This macro defines the physical to virtual address mapping for all the 150 * This macro defines the physical to virtual address mapping for all the
@@ -202,74 +199,209 @@
202/* 199/*
203 * Interrupt numbers 200 * Interrupt numbers
204 */ 201 */
205#define MXC_INT_I2C3 3 202#define MX3x_INT_I2C3 3
206#define MXC_INT_I2C2 4 203#define MX3x_INT_I2C2 4
207#define MXC_INT_RTIC 6 204#define MX3x_INT_RTIC 6
208#define MXC_INT_I2C 10 205#define MX3x_INT_I2C 10
209#define MXC_INT_CSPI2 13 206#define MX3x_INT_CSPI2 13
210#define MXC_INT_CSPI1 14 207#define MX3x_INT_CSPI1 14
211#define MXC_INT_ATA 15 208#define MX3x_INT_ATA 15
212#define MXC_INT_UART3 18 209#define MX3x_INT_UART3 18
213#define MXC_INT_IIM 19 210#define MX3x_INT_IIM 19
214#define MXC_INT_RNGA 22 211#define MX3x_INT_RNGA 22
215#define MXC_INT_EVTMON 23 212#define MX3x_INT_EVTMON 23
216#define MXC_INT_KPP 24 213#define MX3x_INT_KPP 24
217#define MXC_INT_RTC 25 214#define MX3x_INT_RTC 25
218#define MXC_INT_PWM 26 215#define MX3x_INT_PWM 26
219#define MXC_INT_EPIT2 27 216#define MX3x_INT_EPIT2 27
220#define MXC_INT_EPIT1 28 217#define MX3x_INT_EPIT1 28
221#define MXC_INT_GPT 29 218#define MX3x_INT_GPT 29
222#define MXC_INT_POWER_FAIL 30 219#define MX3x_INT_POWER_FAIL 30
223#define MXC_INT_UART2 32 220#define MX3x_INT_UART2 32
224#define MXC_INT_NANDFC 33 221#define MX3x_INT_NANDFC 33
225#define MXC_INT_SDMA 34 222#define MX3x_INT_SDMA 34
226#define MXC_INT_MSHC1 39 223#define MX3x_INT_MSHC1 39
227#define MXC_INT_IPU_ERR 41 224#define MX3x_INT_IPU_ERR 41
228#define MXC_INT_IPU_SYN 42 225#define MX3x_INT_IPU_SYN 42
229#define MXC_INT_UART1 45 226#define MX3x_INT_UART1 45
230#define MXC_INT_ECT 48 227#define MX3x_INT_ECT 48
231#define MXC_INT_SCC_SCM 49 228#define MX3x_INT_SCC_SCM 49
232#define MXC_INT_SCC_SMN 50 229#define MX3x_INT_SCC_SMN 50
233#define MXC_INT_GPIO2 51 230#define MX3x_INT_GPIO2 51
234#define MXC_INT_GPIO1 52 231#define MX3x_INT_GPIO1 52
235#define MXC_INT_WDOG 55 232#define MX3x_INT_WDOG 55
236#define MXC_INT_GPIO3 56 233#define MX3x_INT_GPIO3 56
237#define MXC_INT_EXT_POWER 58 234#define MX3x_INT_EXT_POWER 58
238#define MXC_INT_EXT_TEMPER 59 235#define MX3x_INT_EXT_TEMPER 59
239#define MXC_INT_EXT_SENSOR60 60 236#define MX3x_INT_EXT_SENSOR60 60
240#define MXC_INT_EXT_SENSOR61 61 237#define MX3x_INT_EXT_SENSOR61 61
241#define MXC_INT_EXT_WDOG 62 238#define MX3x_INT_EXT_WDOG 62
242#define MXC_INT_EXT_TV 63 239#define MX3x_INT_EXT_TV 63
243 240
244#define PROD_SIGNATURE 0x1 /* For MX31 */ 241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
245 242
246/* silicon revisions specific to i.MX31 */ 243/* silicon revisions specific to i.MX31 */
247#define CHIP_REV_1_0 0x10 244#define MX3x_CHIP_REV_1_0 0x10
248#define CHIP_REV_1_1 0x11 245#define MX3x_CHIP_REV_1_1 0x11
249#define CHIP_REV_1_2 0x12 246#define MX3x_CHIP_REV_1_2 0x12
250#define CHIP_REV_1_3 0x13 247#define MX3x_CHIP_REV_1_3 0x13
251#define CHIP_REV_2_0 0x20 248#define MX3x_CHIP_REV_2_0 0x20
252#define CHIP_REV_2_1 0x21 249#define MX3x_CHIP_REV_2_1 0x21
253#define CHIP_REV_2_2 0x22 250#define MX3x_CHIP_REV_2_2 0x22
254#define CHIP_REV_2_3 0x23 251#define MX3x_CHIP_REV_2_3 0x23
255#define CHIP_REV_3_0 0x30 252#define MX3x_CHIP_REV_3_0 0x30
256#define CHIP_REV_3_1 0x31 253#define MX3x_CHIP_REV_3_1 0x31
257#define CHIP_REV_3_2 0x32 254#define MX3x_CHIP_REV_3_2 0x32
258 255
259#define SYSTEM_REV_MIN CHIP_REV_1_0 256#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
260#define SYSTEM_REV_NUM 3 257#define MX3x_SYSTEM_REV_NUM 3
261 258
262/* Mandatory defines used globally */ 259/* Mandatory defines used globally */
263 260
264#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 261#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
265 262
266extern unsigned int system_rev; 263extern unsigned int mx31_cpu_rev;
264extern void mx31_read_cpu_rev(void);
267 265
268static inline int mx31_revision(void) 266static inline int mx31_revision(void)
269{ 267{
270 return system_rev; 268 return mx31_cpu_rev;
271} 269}
272#endif 270#endif
273 271
274#endif /* __ASM_ARCH_MXC_MX31_H__ */ 272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
273/* these should go away */
274#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
275#define L2CC_SIZE MX3x_L2CC_SIZE
276#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
277#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
278#define AIPS1_SIZE MX3x_AIPS1_SIZE
279#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
280#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
281#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
282#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
283#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
284#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
285#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
286#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
287#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
288#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
289#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
290#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
291#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
292#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
293#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
294#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
295#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
296#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
297#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
298#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
299#define SPBA0_SIZE MX3x_SPBA0_SIZE
300#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
301#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
302#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
303#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
304#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
305#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
306#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
307#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
308#define AIPS2_SIZE MX3x_AIPS2_SIZE
309#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
310#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
311#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
312#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
313#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
314#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
315#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
316#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
317#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
318#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
319#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
320#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
321#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
322#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
323#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
324#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
325#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
326#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
327#define ROMP_SIZE MX3x_ROMP_SIZE
328#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
329#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
330#define AVIC_SIZE MX3x_AVIC_SIZE
331#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
332#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
333#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
334#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
335#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
336#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
337#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
338#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
339#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
340#define CS4_SIZE MX3x_CS4_SIZE
341#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
342#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
343#define CS5_SIZE MX3x_CS5_SIZE
344#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
345#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
346#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
347#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
348#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
349#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
350#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
351#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
352#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
353#define MXC_INT_I2C3 MX3x_INT_I2C3
354#define MXC_INT_I2C2 MX3x_INT_I2C2
355#define MXC_INT_RTIC MX3x_INT_RTIC
356#define MXC_INT_I2C MX3x_INT_I2C
357#define MXC_INT_CSPI2 MX3x_INT_CSPI2
358#define MXC_INT_CSPI1 MX3x_INT_CSPI1
359#define MXC_INT_ATA MX3x_INT_ATA
360#define MXC_INT_UART3 MX3x_INT_UART3
361#define MXC_INT_IIM MX3x_INT_IIM
362#define MXC_INT_RNGA MX3x_INT_RNGA
363#define MXC_INT_EVTMON MX3x_INT_EVTMON
364#define MXC_INT_KPP MX3x_INT_KPP
365#define MXC_INT_RTC MX3x_INT_RTC
366#define MXC_INT_PWM MX3x_INT_PWM
367#define MXC_INT_EPIT2 MX3x_INT_EPIT2
368#define MXC_INT_EPIT1 MX3x_INT_EPIT1
369#define MXC_INT_GPT MX3x_INT_GPT
370#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
371#define MXC_INT_UART2 MX3x_INT_UART2
372#define MXC_INT_NANDFC MX3x_INT_NANDFC
373#define MXC_INT_SDMA MX3x_INT_SDMA
374#define MXC_INT_MSHC1 MX3x_INT_MSHC1
375#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
376#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
377#define MXC_INT_UART1 MX3x_INT_UART1
378#define MXC_INT_ECT MX3x_INT_ECT
379#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
380#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
381#define MXC_INT_GPIO2 MX3x_INT_GPIO2
382#define MXC_INT_GPIO1 MX3x_INT_GPIO1
383#define MXC_INT_WDOG MX3x_INT_WDOG
384#define MXC_INT_GPIO3 MX3x_INT_GPIO3
385#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
386#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
387#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
388#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
389#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
390#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
391#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
392#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
393#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
394#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
395#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
396#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
397#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
398#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
399#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
400#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
401#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
405#endif
275 406
407#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
new file mode 100644
index 000000000000..5aad344d5651
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -0,0 +1,445 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__
3
4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2
17 * 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM
26 * CFFF0000 64K NFC (NAND Flash AXI)
27 *
28 */
29
30/*
31 * IROM
32 */
33#define MX51_IROM_BASE_ADDR 0x0
34#define MX51_IROM_SIZE SZ_64K
35
36/*
37 * IRAM
38 */
39#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
40#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
41#define MX51_IRAM_PARTITIONS 16
42#define MX51_IRAM_PARTITIONS_TO1 12
43#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
44
45/*
46 * NFC
47 */
48#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
49#define MX51_NFC_AXI_SIZE SZ_64K
50
51/*
52 * Graphics Memory of GPU
53 */
54#define MX51_GPU_BASE_ADDR 0x20000000
55#define MX51_GPU2D_BASE_ADDR 0xD0000000
56
57#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
58#define MX51_TZIC_BASE_ADDR 0xE0000000
59
60#define MX51_DEBUG_BASE_ADDR 0x60000000
61#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
62#define MX51_DEBUG_SIZE SZ_1M
63#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
64#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
65#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
66#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
67#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
68#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
69#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
70#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
71
72/*
73 * SPBA global module enabled #0
74 */
75#define MX51_SPBA0_BASE_ADDR 0x70000000
76#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
77#define MX51_SPBA0_SIZE SZ_1M
78
79#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
80#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
81#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
82#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
83#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
84#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
85#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
86#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
87#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
88#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
89#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
90#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
91
92/*
93 * defines for SPBA modules
94 */
95#define MX51_SPBA_SDHC1 0x04
96#define MX51_SPBA_SDHC2 0x08
97#define MX51_SPBA_UART3 0x0C
98#define MX51_SPBA_CSPI1 0x10
99#define MX51_SPBA_SSI2 0x14
100#define MX51_SPBA_SDHC3 0x20
101#define MX51_SPBA_SDHC4 0x24
102#define MX51_SPBA_SPDIF 0x28
103#define MX51_SPBA_ATA 0x30
104#define MX51_SPBA_SLIM 0x34
105#define MX51_SPBA_HSI2C 0x38
106#define MX51_SPBA_CTRL 0x3C
107
108/*
109 * AIPS 1
110 */
111#define MX51_AIPS1_BASE_ADDR 0x73F00000
112#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
113#define MX51_AIPS1_SIZE SZ_1M
114
115#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
116#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
117#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
118#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
119#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
120#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
121#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
122#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
123#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
124#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
125#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
126#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
127#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
128#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
129#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
130#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
131#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
132#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
133#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
134#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
135
136/*
137 * Defines for modules using static and dynamic DMA channels
138 */
139#define MX51_MXC_DMA_CHANNEL_IRAM 30
140#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
141#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
142#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
143#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
144#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
145#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
146#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
147#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
148#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
149#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
150#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
151#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
152#ifdef CONFIG_SDMA_IRAM
153#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
154#else /*CONFIG_SDMA_IRAM */
155#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
156#endif /*CONFIG_SDMA_IRAM */
157#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
162#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
163#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
164#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
165#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
166
167/*
168 * AIPS 2
169 */
170#define MX51_AIPS2_BASE_ADDR 0x83F00000
171#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
172#define MX51_AIPS2_SIZE SZ_1M
173
174#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
175#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
176#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
177#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
178#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
179#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
180#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
181#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
182#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
183#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
184#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
185#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
186#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
187#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
188#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
189#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
190#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
191#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
192#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
193#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
194#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
195#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
196#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
197#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
198#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
199#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
200#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
201#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
202#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
203#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
204#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
205#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
206
207/*
208 * Memory regions and CS
209 */
210#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
211#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
212#define MX51_CSD0_BASE_ADDR 0x90000000
213#define MX51_CSD1_BASE_ADDR 0xA0000000
214#define MX51_CS0_BASE_ADDR 0xB0000000
215#define MX51_CS1_BASE_ADDR 0xB8000000
216#define MX51_CS2_BASE_ADDR 0xC0000000
217#define MX51_CS3_BASE_ADDR 0xC8000000
218#define MX51_CS4_BASE_ADDR 0xCC000000
219#define MX51_CS5_BASE_ADDR 0xCE000000
220
221/* Does given address belongs to the specified memory region? */
222#define ADDRESS_IN_REGION(addr, start, size) \
223 (((addr) >= (start)) && ((addr) < (start)+(size)))
224
225/* Does given address belongs to the specified named `module'? */
226#define MX51_IS_MODULE(addr, module) \
227 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
228 MX51_ ## module ## _SIZE)
229/*
230 * This macro defines the physical to virtual address mapping for all the
231 * peripheral modules. It is used by passing in the physical address as x
232 * and returning the virtual address. If the physical address is not mapped,
233 * it returns 0xDEADBEEF
234 */
235
236#define MX51_IO_ADDRESS(x) \
237 (void __iomem *) \
238 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
241 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
242 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
243 0xDEADBEEF)
244
245/*
246 * define the address mapping macros: in physical address order
247 */
248#define MX51_IRAM_IO_ADDRESS(x) \
249 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
250
251#define MX51_DEBUG_IO_ADDRESS(x) \
252 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
253
254#define MX51_SPBA0_IO_ADDRESS(x) \
255 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
256
257#define MX51_AIPS1_IO_ADDRESS(x) \
258 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
259
260#define MX51_AIPS2_IO_ADDRESS(x) \
261 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
262
263#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
264
265/*
266 * DMA request assignments
267 */
268#define MX51_DMA_REQ_SSI3_TX1 47
269#define MX51_DMA_REQ_SSI3_RX1 46
270#define MX51_DMA_REQ_SPDIF 45
271#define MX51_DMA_REQ_UART3_TX 44
272#define MX51_DMA_REQ_UART3_RX 43
273#define MX51_DMA_REQ_SLIM_B_TX 42
274#define MX51_DMA_REQ_SDHC4 41
275#define MX51_DMA_REQ_SDHC3 40
276#define MX51_DMA_REQ_CSPI_TX 39
277#define MX51_DMA_REQ_CSPI_RX 38
278#define MX51_DMA_REQ_SSI3_TX2 37
279#define MX51_DMA_REQ_IPU 36
280#define MX51_DMA_REQ_SSI3_RX2 35
281#define MX51_DMA_REQ_EPIT2 34
282#define MX51_DMA_REQ_CTI2_1 33
283#define MX51_DMA_REQ_EMI_WR 32
284#define MX51_DMA_REQ_CTI2_0 31
285#define MX51_DMA_REQ_EMI_RD 30
286#define MX51_DMA_REQ_SSI1_TX1 29
287#define MX51_DMA_REQ_SSI1_RX1 28
288#define MX51_DMA_REQ_SSI1_TX2 27
289#define MX51_DMA_REQ_SSI1_RX2 26
290#define MX51_DMA_REQ_SSI2_TX1 25
291#define MX51_DMA_REQ_SSI2_RX1 24
292#define MX51_DMA_REQ_SSI2_TX2 23
293#define MX51_DMA_REQ_SSI2_RX2 22
294#define MX51_DMA_REQ_SDHC2 21
295#define MX51_DMA_REQ_SDHC1 20
296#define MX51_DMA_REQ_UART1_TX 19
297#define MX51_DMA_REQ_UART1_RX 18
298#define MX51_DMA_REQ_UART2_TX 17
299#define MX51_DMA_REQ_UART2_RX 16
300#define MX51_DMA_REQ_GPU 15
301#define MX51_DMA_REQ_EXTREQ1 14
302#define MX51_DMA_REQ_FIRI_TX 13
303#define MX51_DMA_REQ_FIRI_RX 12
304#define MX51_DMA_REQ_HS_I2C_RX 11
305#define MX51_DMA_REQ_HS_I2C_TX 10
306#define MX51_DMA_REQ_CSPI2_TX 9
307#define MX51_DMA_REQ_CSPI2_RX 8
308#define MX51_DMA_REQ_CSPI1_TX 7
309#define MX51_DMA_REQ_CSPI1_RX 6
310#define MX51_DMA_REQ_SLIM_B 5
311#define MX51_DMA_REQ_ATA_TX_END 4
312#define MX51_DMA_REQ_ATA_TX 3
313#define MX51_DMA_REQ_ATA_RX 2
314#define MX51_DMA_REQ_GPC 1
315#define MX51_DMA_REQ_VPU 0
316
317/*
318 * Interrupt numbers
319 */
320#define MX51_MXC_INT_BASE 0
321#define MX51_MXC_INT_RESV0 0
322#define MX51_MXC_INT_MMC_SDHC1 1
323#define MX51_MXC_INT_MMC_SDHC2 2
324#define MX51_MXC_INT_MMC_SDHC3 3
325#define MX51_MXC_INT_MMC_SDHC4 4
326#define MX51_MXC_INT_RESV5 5
327#define MX51_MXC_INT_SDMA 6
328#define MX51_MXC_INT_IOMUX 7
329#define MX51_MXC_INT_NFC 8
330#define MX51_MXC_INT_VPU 9
331#define MX51_MXC_INT_IPU_ERR 10
332#define MX51_MXC_INT_IPU_SYN 11
333#define MX51_MXC_INT_GPU 12
334#define MX51_MXC_INT_RESV13 13
335#define MX51_MXC_INT_USB_H1 14
336#define MX51_MXC_INT_EMI 15
337#define MX51_MXC_INT_USB_H2 16
338#define MX51_MXC_INT_USB_H3 17
339#define MX51_MXC_INT_USB_OTG 18
340#define MX51_MXC_INT_SAHARA_H0 19
341#define MX51_MXC_INT_SAHARA_H1 20
342#define MX51_MXC_INT_SCC_SMN 21
343#define MX51_MXC_INT_SCC_STZ 22
344#define MX51_MXC_INT_SCC_SCM 23
345#define MX51_MXC_INT_SRTC_NTZ 24
346#define MX51_MXC_INT_SRTC_TZ 25
347#define MX51_MXC_INT_RTIC 26
348#define MX51_MXC_INT_CSU 27
349#define MX51_MXC_INT_SLIM_B 28
350#define MX51_MXC_INT_SSI1 29
351#define MX51_MXC_INT_SSI2 30
352#define MX51_MXC_INT_UART1 31
353#define MX51_MXC_INT_UART2 32
354#define MX51_MXC_INT_UART3 33
355#define MX51_MXC_INT_RESV34 34
356#define MX51_MXC_INT_RESV35 35
357#define MX51_MXC_INT_CSPI1 36
358#define MX51_MXC_INT_CSPI2 37
359#define MX51_MXC_INT_CSPI 38
360#define MX51_MXC_INT_GPT 39
361#define MX51_MXC_INT_EPIT1 40
362#define MX51_MXC_INT_EPIT2 41
363#define MX51_MXC_INT_GPIO1_INT7 42
364#define MX51_MXC_INT_GPIO1_INT6 43
365#define MX51_MXC_INT_GPIO1_INT5 44
366#define MX51_MXC_INT_GPIO1_INT4 45
367#define MX51_MXC_INT_GPIO1_INT3 46
368#define MX51_MXC_INT_GPIO1_INT2 47
369#define MX51_MXC_INT_GPIO1_INT1 48
370#define MX51_MXC_INT_GPIO1_INT0 49
371#define MX51_MXC_INT_GPIO1_LOW 50
372#define MX51_MXC_INT_GPIO1_HIGH 51
373#define MX51_MXC_INT_GPIO2_LOW 52
374#define MX51_MXC_INT_GPIO2_HIGH 53
375#define MX51_MXC_INT_GPIO3_LOW 54
376#define MX51_MXC_INT_GPIO3_HIGH 55
377#define MX51_MXC_INT_GPIO4_LOW 56
378#define MX51_MXC_INT_GPIO4_HIGH 57
379#define MX51_MXC_INT_WDOG1 58
380#define MX51_MXC_INT_WDOG2 59
381#define MX51_MXC_INT_KPP 60
382#define MX51_MXC_INT_PWM1 61
383#define MX51_MXC_INT_I2C1 62
384#define MX51_MXC_INT_I2C2 63
385#define MX51_MXC_INT_HS_I2C 64
386#define MX51_MXC_INT_RESV65 65
387#define MX51_MXC_INT_RESV66 66
388#define MX51_MXC_INT_SIM_IPB 67
389#define MX51_MXC_INT_SIM_DAT 68
390#define MX51_MXC_INT_IIM 69
391#define MX51_MXC_INT_ATA 70
392#define MX51_MXC_INT_CCM1 71
393#define MX51_MXC_INT_CCM2 72
394#define MX51_MXC_INT_GPC1 73
395#define MX51_MXC_INT_GPC2 74
396#define MX51_MXC_INT_SRC 75
397#define MX51_MXC_INT_NM 76
398#define MX51_MXC_INT_PMU 77
399#define MX51_MXC_INT_CTI_IRQ 78
400#define MX51_MXC_INT_CTI1_TG0 79
401#define MX51_MXC_INT_CTI1_TG1 80
402#define MX51_MXC_INT_MCG_ERR 81
403#define MX51_MXC_INT_MCG_TMR 82
404#define MX51_MXC_INT_MCG_FUNC 83
405#define MX51_MXC_INT_GPU2_IRQ 84
406#define MX51_MXC_INT_GPU2_BUSY 85
407#define MX51_MXC_INT_RESV86 86
408#define MX51_MXC_INT_FEC 87
409#define MX51_MXC_INT_OWIRE 88
410#define MX51_MXC_INT_CTI1_TG2 89
411#define MX51_MXC_INT_SJC 90
412#define MX51_MXC_INT_SPDIF 91
413#define MX51_MXC_INT_TVE 92
414#define MX51_MXC_INT_FIRI 93
415#define MX51_MXC_INT_PWM2 94
416#define MX51_MXC_INT_SLIM_EXP 95
417#define MX51_MXC_INT_SSI3 96
418#define MX51_MXC_INT_EMI_BOOT 97
419#define MX51_MXC_INT_CTI1_TG3 98
420#define MX51_MXC_INT_SMC_RX 99
421#define MX51_MXC_INT_VPU_IDLE 100
422#define MX51_MXC_INT_EMI_NFC 101
423#define MX51_MXC_INT_GPU_IDLE 102
424
425/* silicon revisions specific to i.MX51 */
426#define MX51_CHIP_REV_1_0 0x10
427#define MX51_CHIP_REV_1_1 0x11
428#define MX51_CHIP_REV_1_2 0x12
429#define MX51_CHIP_REV_1_3 0x13
430#define MX51_CHIP_REV_2_0 0x20
431#define MX51_CHIP_REV_2_1 0x21
432#define MX51_CHIP_REV_2_2 0x22
433#define MX51_CHIP_REV_2_3 0x23
434#define MX51_CHIP_REV_3_0 0x30
435#define MX51_CHIP_REV_3_1 0x31
436#define MX51_CHIP_REV_3_2 0x32
437
438/* Mandatory defines used globally */
439
440#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
441
442extern int mx51_revision(void);
443#endif
444
445#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 51990536b845..a790bf212972 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
30#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
31#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
32#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MX51 51
33#define MXC_CPU_MXC91231 91231 34#define MXC_CPU_MXC91231 91231
34 35
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
108# define cpu_is_mx35() (0) 109# define cpu_is_mx35() (0)
109#endif 110#endif
110 111
112#ifdef CONFIG_ARCH_MX5
113# ifdef mxc_cpu_type
114# undef mxc_cpu_type
115# define mxc_cpu_type __mxc_cpu_type
116# else
117# define mxc_cpu_type MXC_CPU_MX51
118# endif
119# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
120#else
121# define cpu_is_mx51() (0)
122#endif
123
111#ifdef CONFIG_ARCH_MXC91231 124#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type 125# ifdef mxc_cpu_type
113# undef mxc_cpu_type 126# undef mxc_cpu_type
@@ -121,9 +134,10 @@ extern unsigned int __mxc_cpu_type;
121#endif 134#endif
122 135
123#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 136#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
124#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) 137/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
125#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) 138#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
126#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 139#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
140#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
127#endif 141#endif
128 142
129#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) 143#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 81484d1ef232..5182b986b785 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -184,60 +184,22 @@
184#define MXC91231_CS4_BASE_ADDR 0xB4000000 184#define MXC91231_CS4_BASE_ADDR 0xB4000000
185#define MXC91231_CS5_BASE_ADDR 0xB6000000 185#define MXC91231_CS5_BASE_ADDR 0xB6000000
186 186
187/* Is given address belongs to the specified memory region? */
188#define ADDRESS_IN_REGION(addr, start, size) \
189 (((addr) >= (start)) && ((addr) < (start)+(size)))
190
191/* Is given address belongs to the specified named `module'? */
192#define MXC91231_IS_MODULE(addr, module) \
193 ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
194 MXC91231_ ## module ## _SIZE)
195/* 187/*
196 * This macro defines the physical to virtual address mapping for all the 188 * This macro defines the physical to virtual address mapping for all the
197 * peripheral modules. It is used by passing in the physical address as x 189 * peripheral modules. It is used by passing in the physical address as x
198 * and returning the virtual address. If the physical address is not mapped, 190 * and returning the virtual address. If the physical address is not mapped,
199 * it returns 0xDEADBEEF 191 * it returns 0.
200 */
201
202#define MXC91231_IO_ADDRESS(x) \
203 (void __iomem *) \
204 (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
205 MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
206 MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
207 MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
208 MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
209 MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
210 MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
211 MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
212 0xDEADBEEF)
213
214
215/*
216 * define the address mapping macros: in physical address order
217 */ 192 */
218#define MXC91231_L2CC_IO_ADDRESS(x) \
219 (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
220
221#define MXC91231_AIPS1_IO_ADDRESS(x) \
222 (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
223
224#define MXC91231_SPBA0_IO_ADDRESS(x) \
225 (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
226
227#define MXC91231_SPBA1_IO_ADDRESS(x) \
228 (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
229
230#define MXC91231_AIPS2_IO_ADDRESS(x) \
231 (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
232
233#define MXC91231_ROMP_IO_ADDRESS(x) \
234 (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
235
236#define MXC91231_AVIC_IO_ADDRESS(x) \
237 (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
238 193
239#define MXC91231_X_MEMC_IO_ADDRESS(x) \ 194#define MXC91231_IO_ADDRESS(x) ( \
240 (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) 195 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
196 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
197 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
198 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
199 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
200 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
201 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
202 IMX_IO_ADDRESS(x, MXC91231_AIPS2))
241 203
242/* 204/*
243 * Interrupt numbers 205 * Interrupt numbers
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
new file mode 100644
index 000000000000..4b9b8368c0c0
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -0,0 +1,41 @@
1#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H
2#define __INCLUDE_ASM_ARCH_MXC_EHCI_H
3
4/* values for portsc field */
5#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
6#define MXC_EHCI_FORCE_FS (1 << 24)
7#define MXC_EHCI_UTMI_8BIT (0 << 28)
8#define MXC_EHCI_UTMI_16BIT (1 << 28)
9#define MXC_EHCI_SERIAL (1 << 29)
10#define MXC_EHCI_MODE_UTMI (0 << 30)
11#define MXC_EHCI_MODE_PHILIPS (1 << 30)
12#define MXC_EHCI_MODE_ULPI (2 << 30)
13#define MXC_EHCI_MODE_SERIAL (3 << 30)
14
15/* values for flags field */
16#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
17#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
18#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
19#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
20#define MXC_EHCI_INTERFACE_MASK (0xf)
21
22#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
23#define MXC_EHCI_TTL_ENABLED (1 << 6)
24
25#define MXC_EHCI_INTERNAL_PHY (1 << 7)
26#define MXC_EHCI_IPPUE_DOWN (1 << 8)
27#define MXC_EHCI_IPPUE_UP (1 << 9)
28
29struct mxc_usbh_platform_data {
30 int (*init)(struct platform_device *pdev);
31 int (*exit)(struct platform_device *pdev);
32
33 unsigned int portsc;
34 unsigned int flags;
35 struct otg_transceiver *otg;
36};
37
38int mxc_set_usbcontrol(int port, unsigned int flags);
39
40#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
41
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 2b972df22d12..5d2d21d414e0 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -22,6 +22,7 @@
22 22
23struct mxc_nand_platform_data { 23struct mxc_nand_platform_data {
24 int width; /* data bus width in bytes */ 24 int width; /* data bus width in bytes */
25 int hw_ecc; /* 0 if supress hardware ECC */ 25 int hw_ecc:1; /* 0 if supress hardware ECC */
26 int flash_bbt:1; /* set to 1 to use a flash based bbt */
26}; 27};
27#endif /* __ASM_ARCH_NAND_H */ 28#endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h
new file mode 100644
index 000000000000..c34ded523f10
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ssi.h
@@ -0,0 +1,18 @@
1#ifndef __MACH_SSI_H
2#define __MACH_SSI_H
3
4struct snd_ac97;
5
6extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
7extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
8
9struct imx_ssi_platform_data {
10 unsigned int flags;
11#define IMX_SSI_DMA (1 << 0)
12#define IMX_SSI_USE_AC97 (1 << 1)
13 void (*ac97_reset) (struct snd_ac97 *ac97);
14 void (*ac97_warm_reset)(struct snd_ac97 *ac97);
15};
16
17#endif /* __MACH_SSI_H */
18
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 527a6c24788e..024416ed11cd 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25 29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000 30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MX5
32#define CLOCK_TICK_RATE 8000000
31#elif defined CONFIG_ARCH_MXC91231 33#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000 34#define CLOCK_TICK_RATE 13000000
33#endif 35#endif
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
new file mode 100644
index 000000000000..96b6ab4c40c3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H
3
4extern struct otg_io_access_ops mxc_ulpi_access_ops;
5
6#endif /* __MACH_ULPI_H */
7
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 082a3908256b..b6d3d0fddc48 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -1,8 +1,6 @@
1/* 1/*
2 * arch/arm/plat-mxc/include/mach/uncompress.h 2 * arch/arm/plat-mxc/include/mach/uncompress.h
3 * 3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited 4 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com) 5 * Copyright (C) Shane Nay (shane@minirl.com)
8 * 6 *
@@ -25,7 +23,6 @@
25 23
26#define __MXC_BOOT_UNCOMPRESS 24#define __MXC_BOOT_UNCOMPRESS
27 25
28#include <mach/hardware.h>
29#include <asm/mach-types.h> 26#include <asm/mach-types.h>
30 27
31static unsigned long uart_base; 28static unsigned long uart_base;
@@ -60,13 +57,16 @@ static void putc(int ch)
60 UART(TXR) = ch; 57 UART(TXR) = ch;
61} 58}
62 59
63#define flush() do { } while (0) 60static inline void flush(void)
61{
62}
64 63
65#define MX1_UART1_BASE_ADDR 0x00206000 64#define MX1_UART1_BASE_ADDR 0x00206000
66#define MX25_UART1_BASE_ADDR 0x43f90000 65#define MX25_UART1_BASE_ADDR 0x43f90000
67#define MX2X_UART1_BASE_ADDR 0x1000a000 66#define MX2X_UART1_BASE_ADDR 0x1000a000
68#define MX3X_UART1_BASE_ADDR 0x43F90000 67#define MX3X_UART1_BASE_ADDR 0x43F90000
69#define MX3X_UART2_BASE_ADDR 0x43F94000 68#define MX3X_UART2_BASE_ADDR 0x43F94000
69#define MX51_UART1_BASE_ADDR 0x73fbc000
70 70
71static __inline__ void __arch_decomp_setup(unsigned long arch_id) 71static __inline__ void __arch_decomp_setup(unsigned long arch_id)
72{ 72{
@@ -83,6 +83,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
83 case MACH_TYPE_MX27ADS: 83 case MACH_TYPE_MX27ADS:
84 case MACH_TYPE_PCM038: 84 case MACH_TYPE_PCM038:
85 case MACH_TYPE_MX21ADS: 85 case MACH_TYPE_MX21ADS:
86 case MACH_TYPE_PCA100:
87 case MACH_TYPE_MXT_TD60:
86 uart_base = MX2X_UART1_BASE_ADDR; 88 uart_base = MX2X_UART1_BASE_ADDR;
87 break; 89 break;
88 case MACH_TYPE_MX31LITE: 90 case MACH_TYPE_MX31LITE:
@@ -94,11 +96,15 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
94 case MACH_TYPE_MX31ADS: 96 case MACH_TYPE_MX31ADS:
95 case MACH_TYPE_MX35_3DS: 97 case MACH_TYPE_MX35_3DS:
96 case MACH_TYPE_PCM043: 98 case MACH_TYPE_PCM043:
99 case MACH_TYPE_LILLY1131:
97 uart_base = MX3X_UART1_BASE_ADDR; 100 uart_base = MX3X_UART1_BASE_ADDR;
98 break; 101 break;
99 case MACH_TYPE_MAGX_ZN5: 102 case MACH_TYPE_MAGX_ZN5:
100 uart_base = MX3X_UART2_BASE_ADDR; 103 uart_base = MX3X_UART2_BASE_ADDR;
101 break; 104 break;
105 case MACH_TYPE_MX51_BABBAGE:
106 uart_base = MX51_UART1_BASE_ADDR;
107 break;
102 default: 108 default:
103 break; 109 break;
104 } 110 }
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 62d97623412f..44243a278434 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -21,6 +21,6 @@
21#define __ASM_ARCH_MXC_VMALLOC_H__ 21#define __ASM_ARCH_MXC_VMALLOC_H__
22 22
23/* vmalloc ending address */ 23/* vmalloc ending address */
24#define VMALLOC_END 0xF4000000 24#define VMALLOC_END 0xf4000000UL
25 25
26#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ 26#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 14:44:41 -0500