1 files changed, 94 insertions, 93 deletions

diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a47f4..09ac19c1570c 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -188,99 +188,100 @@
 /*
  * Interrupt numbers
  */
-#define MX50_INT_MMC_SDHC1      1
-#define MX50_INT_MMC_SDHC2      2
-#define MX50_INT_MMC_SDHC3      3
-#define MX50_INT_MMC_SDHC4      4
-#define MX50_INT_DAP            5
-#define MX50_INT_SDMA           6
-#define MX50_INT_IOMUX          7
-#define MX50_INT_UART4          13
-#define MX50_INT_USB_H1         14
-#define MX50_INT_USB_OTG        18
-#define MX50_INT_DATABAHN       19
-#define MX50_INT_ELCDIF         20
-#define MX50_INT_EPXP           21
-#define MX50_INT_SRTC_NTZ       24
-#define MX50_INT_SRTC_TZ        25
-#define MX50_INT_EPDC           27
-#define MX50_INT_NIC            28
-#define MX50_INT_SSI1           29
-#define MX50_INT_SSI2           30
-#define MX50_INT_UART1          31
-#define MX50_INT_UART2          32
-#define MX50_INT_UART3          33
-#define MX50_INT_RESV34         34
-#define MX50_INT_RESV35         35
-#define MX50_INT_CSPI1          36
-#define MX50_INT_CSPI2          37
-#define MX50_INT_CSPI           38
-#define MX50_INT_GPT            39
-#define MX50_INT_EPIT1          40
-#define MX50_INT_GPIO1_INT7     42
-#define MX50_INT_GPIO1_INT6     43
-#define MX50_INT_GPIO1_INT5     44
-#define MX50_INT_GPIO1_INT4     45
-#define MX50_INT_GPIO1_INT3     46
-#define MX50_INT_GPIO1_INT2     47
-#define MX50_INT_GPIO1_INT1     48
-#define MX50_INT_GPIO1_INT0     49
-#define MX50_INT_GPIO1_LOW      50
-#define MX50_INT_GPIO1_HIGH     51
-#define MX50_INT_GPIO2_LOW      52
-#define MX50_INT_GPIO2_HIGH     53
-#define MX50_INT_GPIO3_LOW      54
-#define MX50_INT_GPIO3_HIGH     55
-#define MX50_INT_GPIO4_LOW      56
-#define MX50_INT_GPIO4_HIGH     57
-#define MX50_INT_WDOG1          58
-#define MX50_INT_KPP            60
-#define MX50_INT_PWM1           61
-#define MX50_INT_I2C1           62
-#define MX50_INT_I2C2           63
-#define MX50_INT_I2C3           64
-#define MX50_INT_RESV65         65
-#define MX50_INT_DCDC           66
-#define MX50_INT_THERMAL_ALARM  67
-#define MX50_INT_ANA3           68
-#define MX50_INT_ANA4           69
-#define MX50_INT_CCM1           71
-#define MX50_INT_CCM2           72
-#define MX50_INT_GPC1           73
-#define MX50_INT_GPC2           74
-#define MX50_INT_SRC            75
-#define MX50_INT_NM             76
-#define MX50_INT_PMU            77
-#define MX50_INT_CTI_IRQ        78
-#define MX50_INT_CTI1_TG0       79
-#define MX50_INT_CTI1_TG1       80
-#define MX50_INT_GPU2_IRQ       84
-#define MX50_INT_GPU2_BUSY      85
-#define MX50_INT_UART5          86
-#define MX50_INT_FEC            87
-#define MX50_INT_OWIRE          88
-#define MX50_INT_CTI1_TG2       89
-#define MX50_INT_SJC            90
-#define MX50_INT_DCP_CHAN1_3    91
-#define MX50_INT_DCP_CHAN0      92
-#define MX50_INT_PWM2           94
-#define MX50_INT_RNGB           97
-#define MX50_INT_CTI1_TG3       98
-#define MX50_INT_RAWNAND_BCH    100
-#define MX50_INT_RAWNAND_GPMI   102
-#define MX50_INT_GPIO5_LOW      103
-#define MX50_INT_GPIO5_HIGH     104
-#define MX50_INT_GPIO6_LOW      105
-#define MX50_INT_GPIO6_HIGH     106
-#define MX50_INT_MSHC           109
-#define MX50_INT_APBHDMA_CHAN0  110
-#define MX50_INT_APBHDMA_CHAN1  111
-#define MX50_INT_APBHDMA_CHAN2  112
-#define MX50_INT_APBHDMA_CHAN3  113
-#define MX50_INT_APBHDMA_CHAN4  114
-#define MX50_INT_APBHDMA_CHAN5  115
-#define MX50_INT_APBHDMA_CHAN6  116
-#define MX50_INT_APBHDMA_CHAN7  117
+#include <asm/irq.h>
+#define MX50_INT_MMC_SDHC1      (NR_IRQS_LEGACY + 1)
+#define MX50_INT_MMC_SDHC2      (NR_IRQS_LEGACY + 2)
+#define MX50_INT_MMC_SDHC3      (NR_IRQS_LEGACY + 3)
+#define MX50_INT_MMC_SDHC4      (NR_IRQS_LEGACY + 4)
+#define MX50_INT_DAP            (NR_IRQS_LEGACY + 5)
+#define MX50_INT_SDMA           (NR_IRQS_LEGACY + 6)
+#define MX50_INT_IOMUX          (NR_IRQS_LEGACY + 7)
+#define MX50_INT_UART4          (NR_IRQS_LEGACY + 13)
+#define MX50_INT_USB_H1         (NR_IRQS_LEGACY + 14)
+#define MX50_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
+#define MX50_INT_DATABAHN       (NR_IRQS_LEGACY + 19)
+#define MX50_INT_ELCDIF         (NR_IRQS_LEGACY + 20)
+#define MX50_INT_EPXP           (NR_IRQS_LEGACY + 21)
+#define MX50_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
+#define MX50_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
+#define MX50_INT_EPDC           (NR_IRQS_LEGACY + 27)
+#define MX50_INT_NIC            (NR_IRQS_LEGACY + 28)
+#define MX50_INT_SSI1           (NR_IRQS_LEGACY + 29)
+#define MX50_INT_SSI2           (NR_IRQS_LEGACY + 30)
+#define MX50_INT_UART1          (NR_IRQS_LEGACY + 31)
+#define MX50_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX50_INT_UART3          (NR_IRQS_LEGACY + 33)
+#define MX50_INT_RESV34         (NR_IRQS_LEGACY + 34)
+#define MX50_INT_RESV35         (NR_IRQS_LEGACY + 35)
+#define MX50_INT_CSPI1          (NR_IRQS_LEGACY + 36)
+#define MX50_INT_CSPI2          (NR_IRQS_LEGACY + 37)
+#define MX50_INT_CSPI           (NR_IRQS_LEGACY + 38)
+#define MX50_INT_GPT            (NR_IRQS_LEGACY + 39)
+#define MX50_INT_EPIT1          (NR_IRQS_LEGACY + 40)
+#define MX50_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
+#define MX50_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
+#define MX50_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
+#define MX50_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
+#define MX50_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
+#define MX50_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
+#define MX50_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
+#define MX50_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
+#define MX50_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
+#define MX50_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
+#define MX50_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
+#define MX50_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
+#define MX50_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
+#define MX50_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
+#define MX50_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
+#define MX50_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
+#define MX50_INT_WDOG1          (NR_IRQS_LEGACY + 58)
+#define MX50_INT_KPP            (NR_IRQS_LEGACY + 60)
+#define MX50_INT_PWM1           (NR_IRQS_LEGACY + 61)
+#define MX50_INT_I2C1           (NR_IRQS_LEGACY + 62)
+#define MX50_INT_I2C2           (NR_IRQS_LEGACY + 63)
+#define MX50_INT_I2C3           (NR_IRQS_LEGACY + 64)
+#define MX50_INT_RESV65         (NR_IRQS_LEGACY + 65)
+#define MX50_INT_DCDC           (NR_IRQS_LEGACY + 66)
+#define MX50_INT_THERMAL_ALARM  (NR_IRQS_LEGACY + 67)
+#define MX50_INT_ANA3           (NR_IRQS_LEGACY + 68)
+#define MX50_INT_ANA4           (NR_IRQS_LEGACY + 69)
+#define MX50_INT_CCM1           (NR_IRQS_LEGACY + 71)
+#define MX50_INT_CCM2           (NR_IRQS_LEGACY + 72)
+#define MX50_INT_GPC1           (NR_IRQS_LEGACY + 73)
+#define MX50_INT_GPC2           (NR_IRQS_LEGACY + 74)
+#define MX50_INT_SRC            (NR_IRQS_LEGACY + 75)
+#define MX50_INT_NM             (NR_IRQS_LEGACY + 76)
+#define MX50_INT_PMU            (NR_IRQS_LEGACY + 77)
+#define MX50_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
+#define MX50_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
+#define MX50_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
+#define MX50_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
+#define MX50_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
+#define MX50_INT_UART5          (NR_IRQS_LEGACY + 86)
+#define MX50_INT_FEC            (NR_IRQS_LEGACY + 87)
+#define MX50_INT_OWIRE          (NR_IRQS_LEGACY + 88)
+#define MX50_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
+#define MX50_INT_SJC            (NR_IRQS_LEGACY + 90)
+#define MX50_INT_DCP_CHAN1_3    (NR_IRQS_LEGACY + 91)
+#define MX50_INT_DCP_CHAN0      (NR_IRQS_LEGACY + 92)
+#define MX50_INT_PWM2           (NR_IRQS_LEGACY + 94)
+#define MX50_INT_RNGB           (NR_IRQS_LEGACY + 97)
+#define MX50_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
+#define MX50_INT_RAWNAND_BCH    (NR_IRQS_LEGACY + 100)
+#define MX50_INT_RAWNAND_GPMI   (NR_IRQS_LEGACY + 102)
+#define MX50_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
+#define MX50_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
+#define MX50_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
+#define MX50_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
+#define MX50_INT_MSHC           (NR_IRQS_LEGACY + 109)
+#define MX50_INT_APBHDMA_CHAN0  (NR_IRQS_LEGACY + 110)
+#define MX50_INT_APBHDMA_CHAN1  (NR_IRQS_LEGACY + 111)
+#define MX50_INT_APBHDMA_CHAN2  (NR_IRQS_LEGACY + 112)
+#define MX50_INT_APBHDMA_CHAN3  (NR_IRQS_LEGACY + 113)
+#define MX50_INT_APBHDMA_CHAN4  (NR_IRQS_LEGACY + 114)
+#define MX50_INT_APBHDMA_CHAN5  (NR_IRQS_LEGACY + 115)
+#define MX50_INT_APBHDMA_CHAN6  (NR_IRQS_LEGACY + 116)
+#define MX50_INT_APBHDMA_CHAN7  (NR_IRQS_LEGACY + 117)
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx50_revision(void);