diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx31.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 118 |
1 files changed, 61 insertions, 57 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index e27619e442c0..dbced61d9fda 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -118,63 +118,67 @@ | |||
118 | #define MX31_IO_P2V(x) IMX_IO_P2V(x) | 118 | #define MX31_IO_P2V(x) IMX_IO_P2V(x) |
119 | #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) | 119 | #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) |
120 | 120 | ||
121 | #define MX31_INT_I2C3 3 | 121 | /* |
122 | #define MX31_INT_I2C2 4 | 122 | * Interrupt numbers |
123 | #define MX31_INT_MPEG4_ENCODER 5 | 123 | */ |
124 | #define MX31_INT_RTIC 6 | 124 | #include <asm/irq.h> |
125 | #define MX31_INT_FIRI 7 | 125 | #define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) |
126 | #define MX31_INT_SDHC2 8 | 126 | #define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) |
127 | #define MX31_INT_SDHC1 9 | 127 | #define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) |
128 | #define MX31_INT_I2C1 10 | 128 | #define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) |
129 | #define MX31_INT_SSI2 11 | 129 | #define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) |
130 | #define MX31_INT_SSI1 12 | 130 | #define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) |
131 | #define MX31_INT_CSPI2 13 | 131 | #define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) |
132 | #define MX31_INT_CSPI1 14 | 132 | #define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) |
133 | #define MX31_INT_ATA 15 | 133 | #define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) |
134 | #define MX31_INT_MBX 16 | 134 | #define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) |
135 | #define MX31_INT_CSPI3 17 | 135 | #define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) |
136 | #define MX31_INT_UART3 18 | 136 | #define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) |
137 | #define MX31_INT_IIM 19 | 137 | #define MX31_INT_ATA (NR_IRQS_LEGACY + 15) |
138 | #define MX31_INT_SIM2 20 | 138 | #define MX31_INT_MBX (NR_IRQS_LEGACY + 16) |
139 | #define MX31_INT_SIM1 21 | 139 | #define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) |
140 | #define MX31_INT_RNGA 22 | 140 | #define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) |
141 | #define MX31_INT_EVTMON 23 | 141 | #define MX31_INT_IIM (NR_IRQS_LEGACY + 19) |
142 | #define MX31_INT_KPP 24 | 142 | #define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) |
143 | #define MX31_INT_RTC 25 | 143 | #define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) |
144 | #define MX31_INT_PWM 26 | 144 | #define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) |
145 | #define MX31_INT_EPIT2 27 | 145 | #define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) |
146 | #define MX31_INT_EPIT1 28 | 146 | #define MX31_INT_KPP (NR_IRQS_LEGACY + 24) |
147 | #define MX31_INT_GPT 29 | 147 | #define MX31_INT_RTC (NR_IRQS_LEGACY + 25) |
148 | #define MX31_INT_POWER_FAIL 30 | 148 | #define MX31_INT_PWM (NR_IRQS_LEGACY + 26) |
149 | #define MX31_INT_CCM_DVFS 31 | 149 | #define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) |
150 | #define MX31_INT_UART2 32 | 150 | #define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) |
151 | #define MX31_INT_NFC 33 | 151 | #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) |
152 | #define MX31_INT_SDMA 34 | 152 | #define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) |
153 | #define MX31_INT_USB_HS1 35 | 153 | #define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) |
154 | #define MX31_INT_USB_HS2 36 | 154 | #define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) |
155 | #define MX31_INT_USB_OTG 37 | 155 | #define MX31_INT_NFC (NR_IRQS_LEGACY + 33) |
156 | #define MX31_INT_MSHC1 39 | 156 | #define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) |
157 | #define MX31_INT_MSHC2 40 | 157 | #define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) |
158 | #define MX31_INT_IPU_ERR 41 | 158 | #define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) |
159 | #define MX31_INT_IPU_SYN 42 | 159 | #define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) |
160 | #define MX31_INT_UART1 45 | 160 | #define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) |
161 | #define MX31_INT_UART4 46 | 161 | #define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) |
162 | #define MX31_INT_UART5 47 | 162 | #define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) |
163 | #define MX31_INT_ECT 48 | 163 | #define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) |
164 | #define MX31_INT_SCC_SCM 49 | 164 | #define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) |
165 | #define MX31_INT_SCC_SMN 50 | 165 | #define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) |
166 | #define MX31_INT_GPIO2 51 | 166 | #define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) |
167 | #define MX31_INT_GPIO1 52 | 167 | #define MX31_INT_ECT (NR_IRQS_LEGACY + 48) |
168 | #define MX31_INT_CCM 53 | 168 | #define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) |
169 | #define MX31_INT_PCMCIA 54 | 169 | #define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) |
170 | #define MX31_INT_WDOG 55 | 170 | #define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) |
171 | #define MX31_INT_GPIO3 56 | 171 | #define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) |
172 | #define MX31_INT_EXT_POWER 58 | 172 | #define MX31_INT_CCM (NR_IRQS_LEGACY + 53) |
173 | #define MX31_INT_EXT_TEMPER 59 | 173 | #define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) |
174 | #define MX31_INT_EXT_SENSOR60 60 | 174 | #define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) |
175 | #define MX31_INT_EXT_SENSOR61 61 | 175 | #define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) |
176 | #define MX31_INT_EXT_WDOG 62 | 176 | #define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) |
177 | #define MX31_INT_EXT_TV 63 | 177 | #define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) |
178 | #define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) | ||
179 | #define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) | ||
180 | #define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) | ||
181 | #define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) | ||
178 | 182 | ||
179 | #define MX31_DMA_REQ_SDHC1 20 | 183 | #define MX31_DMA_REQ_SDHC1 20 |
180 | #define MX31_DMA_REQ_SDHC2 21 | 184 | #define MX31_DMA_REQ_SDHC2 21 |