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-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h32
1 files changed, 29 insertions, 3 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index e2ae19f51710..bae9cd75beee 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -21,8 +21,12 @@
21 * MA 02110-1301, USA. 21 * MA 02110-1301, USA.
22 */ 22 */
23 23
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __MACH_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __MACH_MX27_H__
26
27#ifndef __ASSEMBLER__
28#include <linux/io.h>
29#endif
26 30
27#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
@@ -109,11 +113,31 @@
109#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) 113#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
110#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) 114#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
111 115
116#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
120
112#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 121#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
113 122
114/* IRAM */ 123/* IRAM */
115#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
116 125
126#define MX27_IO_ADDRESS(x) ( \
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130
131#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
138}
139#endif
140
117/* fixed interrupt numbers */ 141/* fixed interrupt numbers */
118#define MX27_INT_I2C2 1 142#define MX27_INT_I2C2 1
119#define MX27_INT_GPT6 2 143#define MX27_INT_GPT6 2
@@ -225,6 +249,7 @@
225extern int mx27_revision(void); 249extern int mx27_revision(void);
226#endif 250#endif
227 251
252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
228/* these should go away */ 253/* these should go away */
229#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR 254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
230#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR 255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
@@ -292,5 +317,6 @@ extern int mx27_revision(void);
292#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX 317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
293#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
294#define DMA_REQ_NFC MX27_DMA_REQ_NFC 319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
295 321
296#endif /* __ASM_ARCH_MXC_MX27_H__ */ 322#endif /* ifndef __MACH_MX27_H__ */