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Diffstat (limited to 'arch/arm/plat-mxc/gpio.c')
-rw-r--r--arch/arm/plat-mxc/gpio.c42
1 files changed, 28 insertions, 14 deletions
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7506d963be4b..cfc4a8b43e6a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
29static struct mxc_gpio_port *mxc_gpio_ports; 29static struct mxc_gpio_port *mxc_gpio_ports;
30static int gpio_table_size; 30static int gpio_table_size;
31 31
32#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
33
34#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
35#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
36#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
37#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47#define GPIO_INT_NONE 0x4
48
32/* Note: This driver assumes 32 GPIOs are handled in one register */ 49/* Note: This driver assumes 32 GPIOs are handled in one register */
33 50
34static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) 51static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
162 } 179 }
163} 180}
164 181
165#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
166/* MX1 and MX3 has one interrupt *per* gpio port */ 182/* MX1 and MX3 has one interrupt *per* gpio port */
167static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 183static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
168{ 184{
@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
174 190
175 mxc_gpio_irq_handler(port, irq_stat); 191 mxc_gpio_irq_handler(port, irq_stat);
176} 192}
177#endif
178 193
179#ifdef CONFIG_ARCH_MX2
180/* MX2 has one interrupt *for all* gpio ports */ 194/* MX2 has one interrupt *for all* gpio ports */
181static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 195static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
182{ 196{
@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
195 mxc_gpio_irq_handler(&port[i], irq_stat); 209 mxc_gpio_irq_handler(&port[i], irq_stat);
196 } 210 }
197} 211}
198#endif
199 212
200static struct irq_chip gpio_irq_chip = { 213static struct irq_chip gpio_irq_chip = {
201 .ack = gpio_ack_irq, 214 .ack = gpio_ack_irq,
@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
284 /* its a serious configuration bug when it fails */ 297 /* its a serious configuration bug when it fails */
285 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 298 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
286 299
287#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) 300 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
288 /* setup one handler for each entry */ 301 /* setup one handler for each entry */
289 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 302 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
290 set_irq_data(port[i].irq, &port[i]); 303 set_irq_data(port[i].irq, &port[i]);
291#endif 304 }
305 }
306
307 if (cpu_is_mx2()) {
308 /* setup one handler for all GPIO interrupts */
309 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
310 set_irq_data(port[0].irq, port);
292 } 311 }
293 312
294#ifdef CONFIG_ARCH_MX2
295 /* setup one handler for all GPIO interrupts */
296 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
297 set_irq_data(port[0].irq, port);
298#endif
299 return 0; 313 return 0;
300} 314}