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-rw-r--r--arch/arm/plat-mxc/ehci.c122
1 files changed, 112 insertions, 10 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 41599be882e8..cb0b63874482 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -25,25 +25,37 @@
25#define USBCTRL_OTGBASE_OFFSET 0x600 25#define USBCTRL_OTGBASE_OFFSET 0x600
26 26
27#define MX31_OTG_SIC_SHIFT 29 27#define MX31_OTG_SIC_SHIFT 29
28#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) 28#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
29#define MX31_OTG_PM_BIT (1 << 24) 29#define MX31_OTG_PM_BIT (1 << 24)
30 30
31#define MX31_H2_SIC_SHIFT 21 31#define MX31_H2_SIC_SHIFT 21
32#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) 32#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
33#define MX31_H2_PM_BIT (1 << 16) 33#define MX31_H2_PM_BIT (1 << 16)
34#define MX31_H2_DT_BIT (1 << 5) 34#define MX31_H2_DT_BIT (1 << 5)
35 35
36#define MX31_H1_SIC_SHIFT 13 36#define MX31_H1_SIC_SHIFT 13
37#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) 37#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
38#define MX31_H1_PM_BIT (1 << 8) 38#define MX31_H1_PM_BIT (1 << 8)
39#define MX31_H1_DT_BIT (1 << 4) 39#define MX31_H1_DT_BIT (1 << 4)
40 40
41#define MX35_OTG_SIC_SHIFT 29
42#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
43#define MX35_OTG_PM_BIT (1 << 24)
44
45#define MX35_H1_SIC_SHIFT 21
46#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
47#define MX35_H1_PM_BIT (1 << 8)
48#define MX35_H1_IPPUE_UP_BIT (1 << 7)
49#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
50#define MX35_H1_TLL_BIT (1 << 5)
51#define MX35_H1_USBTE_BIT (1 << 4)
52
41int mxc_set_usbcontrol(int port, unsigned int flags) 53int mxc_set_usbcontrol(int port, unsigned int flags)
42{ 54{
43 unsigned int v; 55 unsigned int v;
44 56#ifdef CONFIG_ARCH_MX3
45 if (cpu_is_mx31()) { 57 if (cpu_is_mx31()) {
46 v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + 58 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
47 USBCTRL_OTGBASE_OFFSET)); 59 USBCTRL_OTGBASE_OFFSET));
48 60
49 switch (port) { 61 switch (port) {
@@ -51,15 +63,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
51 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 63 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
52 v |= (flags & MXC_EHCI_INTERFACE_MASK) 64 v |= (flags & MXC_EHCI_INTERFACE_MASK)
53 << MX31_OTG_SIC_SHIFT; 65 << MX31_OTG_SIC_SHIFT;
54 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 66 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
55 v |= MX31_OTG_PM_BIT; 67 v |= MX31_OTG_PM_BIT;
56 68
57 break; 69 break;
58 case 1: /* H1 port */ 70 case 1: /* H1 port */
59 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); 71 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
60 v |= (flags & MXC_EHCI_INTERFACE_MASK) 72 v |= (flags & MXC_EHCI_INTERFACE_MASK)
61 << MX31_H1_SIC_SHIFT; 73 << MX31_H1_SIC_SHIFT;
62 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 74 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
63 v |= MX31_H1_PM_BIT; 75 v |= MX31_H1_PM_BIT;
64 76
65 if (!(flags & MXC_EHCI_TTL_ENABLED)) 77 if (!(flags & MXC_EHCI_TTL_ENABLED))
@@ -67,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
67 79
68 break; 80 break;
69 case 2: /* H2 port */ 81 case 2: /* H2 port */
70 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); 82 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
71 v |= (flags & MXC_EHCI_INTERFACE_MASK) 83 v |= (flags & MXC_EHCI_INTERFACE_MASK)
72 << MX31_H2_SIC_SHIFT; 84 << MX31_H2_SIC_SHIFT;
73 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 85 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
@@ -77,13 +89,103 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
77 v |= MX31_H2_DT_BIT; 89 v |= MX31_H2_DT_BIT;
78 90
79 break; 91 break;
92 default:
93 return -EINVAL;
80 } 94 }
81 95
82 writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + 96 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
83 USBCTRL_OTGBASE_OFFSET)); 97 USBCTRL_OTGBASE_OFFSET));
84 return 0; 98 return 0;
85 } 99 }
86 100
101 if (cpu_is_mx35()) {
102 v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
103 USBCTRL_OTGBASE_OFFSET));
104
105 switch (port) {
106 case 0: /* OTG port */
107 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
108 v |= (flags & MXC_EHCI_INTERFACE_MASK)
109 << MX35_OTG_SIC_SHIFT;
110 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
111 v |= MX35_OTG_PM_BIT;
112
113 break;
114 case 1: /* H1 port */
115 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
116 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
117 v |= (flags & MXC_EHCI_INTERFACE_MASK)
118 << MX35_H1_SIC_SHIFT;
119 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
120 v |= MX35_H1_PM_BIT;
121
122 if (!(flags & MXC_EHCI_TTL_ENABLED))
123 v |= MX35_H1_TLL_BIT;
124
125 if (flags & MXC_EHCI_INTERNAL_PHY)
126 v |= MX35_H1_USBTE_BIT;
127
128 if (flags & MXC_EHCI_IPPUE_DOWN)
129 v |= MX35_H1_IPPUE_DOWN_BIT;
130
131 if (flags & MXC_EHCI_IPPUE_UP)
132 v |= MX35_H1_IPPUE_UP_BIT;
133
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
140 USBCTRL_OTGBASE_OFFSET));
141 return 0;
142 }
143#endif /* CONFIG_ARCH_MX3 */
144#ifdef CONFIG_MACH_MX27
145 if (cpu_is_mx27()) {
146 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
147 * are identical
148 */
149 v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
150 USBCTRL_OTGBASE_OFFSET));
151 switch (port) {
152 case 0: /* OTG port */
153 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
154 v |= (flags & MXC_EHCI_INTERFACE_MASK)
155 << MX31_OTG_SIC_SHIFT;
156 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
157 v |= MX31_OTG_PM_BIT;
158 break;
159 case 1: /* H1 port */
160 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
161 v |= (flags & MXC_EHCI_INTERFACE_MASK)
162 << MX31_H1_SIC_SHIFT;
163 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
164 v |= MX31_H1_PM_BIT;
165
166 if (!(flags & MXC_EHCI_TTL_ENABLED))
167 v |= MX31_H1_DT_BIT;
168
169 break;
170 case 2: /* H2 port */
171 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
172 v |= (flags & MXC_EHCI_INTERFACE_MASK)
173 << MX31_H2_SIC_SHIFT;
174 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
175 v |= MX31_H2_PM_BIT;
176
177 if (!(flags & MXC_EHCI_TTL_ENABLED))
178 v |= MX31_H2_DT_BIT;
179
180 break;
181 default:
182 return -EINVAL;
183 }
184 writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
185 USBCTRL_OTGBASE_OFFSET));
186 return 0;
187 }
188#endif /* CONFIG_MACH_MX27 */
87 printk(KERN_WARNING 189 printk(KERN_WARNING
88 "%s() unable to setup USBCONTROL for this CPU\n", __func__); 190 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
89 return -EINVAL; 191 return -EINVAL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 18:05:17 -0500