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-rw-r--r--arch/arm/mm/Kconfig57
-rw-r--r--arch/arm/mm/Makefile1
-rw-r--r--arch/arm/mm/abort-ev6.S6
-rw-r--r--arch/arm/mm/cache-l2x0.c38
-rw-r--r--arch/arm/mm/init.c6
-rw-r--r--arch/arm/mm/mmap.c2
-rw-r--r--arch/arm/mm/mmu.c10
-rw-r--r--arch/arm/mm/proc-arm1020.S3
-rw-r--r--arch/arm/mm/proc-arm1020e.S3
-rw-r--r--arch/arm/mm/proc-arm1022.S3
-rw-r--r--arch/arm/mm/proc-arm1026.S3
-rw-r--r--arch/arm/mm/proc-arm6_7.S6
-rw-r--r--arch/arm/mm/proc-arm720.S3
-rw-r--r--arch/arm/mm/proc-arm740.S3
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S3
-rw-r--r--arch/arm/mm/proc-arm920.S37
-rw-r--r--arch/arm/mm/proc-arm922.S3
-rw-r--r--arch/arm/mm/proc-arm925.S3
-rw-r--r--arch/arm/mm/proc-arm926.S37
-rw-r--r--arch/arm/mm/proc-arm940.S3
-rw-r--r--arch/arm/mm/proc-arm946.S3
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S3
-rw-r--r--arch/arm/mm/proc-fa526.S3
-rw-r--r--arch/arm/mm/proc-feroceon.S3
-rw-r--r--arch/arm/mm/proc-mohawk.S3
-rw-r--r--arch/arm/mm/proc-sa110.S3
-rw-r--r--arch/arm/mm/proc-sa1100.S39
-rw-r--r--arch/arm/mm/proc-v6.S50
-rw-r--r--arch/arm/mm/proc-v7.S128
-rw-r--r--arch/arm/mm/proc-xsc3.S48
-rw-r--r--arch/arm/mm/proc-xscale.S45
-rw-r--r--arch/arm/mm/vmregion.c17
32 files changed, 483 insertions, 92 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9d30c6f804b9..89266382b536 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -390,7 +390,7 @@ config CPU_PJ4
390 390
391# ARMv6 391# ARMv6
392config CPU_V6 392config CPU_V6
393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE 393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
394 select CPU_32v6 394 select CPU_32v6
395 select CPU_ABRT_EV6 395 select CPU_ABRT_EV6
396 select CPU_PABRT_V6 396 select CPU_PABRT_V6
@@ -402,21 +402,23 @@ config CPU_V6
402 select CPU_TLB_V6 if MMU 402 select CPU_TLB_V6 if MMU
403 403
404# ARMv6k 404# ARMv6k
405config CPU_32v6K 405config CPU_V6K
406 bool "Support ARM V6K processor extensions" if !SMP 406 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
407 depends on CPU_V6 || CPU_V7 407 select CPU_32v6
408 default y if SMP && !(ARCH_MX3 || ARCH_OMAP2) 408 select CPU_32v6K
409 help 409 select CPU_ABRT_EV6
410 Say Y here if your ARMv6 processor supports the 'K' extension. 410 select CPU_PABRT_V6
411 This enables the kernel to use some instructions not present 411 select CPU_CACHE_V6
412 on previous processors, and as such a kernel build with this 412 select CPU_CACHE_VIPT
413 enabled will not boot on processors with do not support these 413 select CPU_CP15_MMU
414 instructions. 414 select CPU_HAS_ASID if MMU
415 select CPU_COPY_V6 if MMU
416 select CPU_TLB_V6 if MMU
415 417
416# ARMv7 418# ARMv7
417config CPU_V7 419config CPU_V7
418 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 420 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
419 select CPU_32v6K if !ARCH_OMAP2 421 select CPU_32v6K
420 select CPU_32v7 422 select CPU_32v7
421 select CPU_ABRT_EV7 423 select CPU_ABRT_EV7
422 select CPU_PABRT_V7 424 select CPU_PABRT_V7
@@ -433,25 +435,33 @@ config CPU_32v3
433 bool 435 bool
434 select TLS_REG_EMUL if SMP || !MMU 436 select TLS_REG_EMUL if SMP || !MMU
435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 437 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
438 select CPU_USE_DOMAINS if MMU
436 439
437config CPU_32v4 440config CPU_32v4
438 bool 441 bool
439 select TLS_REG_EMUL if SMP || !MMU 442 select TLS_REG_EMUL if SMP || !MMU
440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select CPU_USE_DOMAINS if MMU
441 445
442config CPU_32v4T 446config CPU_32v4T
443 bool 447 bool
444 select TLS_REG_EMUL if SMP || !MMU 448 select TLS_REG_EMUL if SMP || !MMU
445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 449 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450 select CPU_USE_DOMAINS if MMU
446 451
447config CPU_32v5 452config CPU_32v5
448 bool 453 bool
449 select TLS_REG_EMUL if SMP || !MMU 454 select TLS_REG_EMUL if SMP || !MMU
450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 455 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
456 select CPU_USE_DOMAINS if MMU
451 457
452config CPU_32v6 458config CPU_32v6
453 bool 459 bool
454 select TLS_REG_EMUL if !CPU_32v6K && !MMU 460 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 select CPU_USE_DOMAINS if CPU_V6 && MMU
462
463config CPU_32v6K
464 bool
455 465
456config CPU_32v7 466config CPU_32v7
457 bool 467 bool
@@ -607,8 +617,6 @@ config CPU_CP15_MPU
607 617
608config CPU_USE_DOMAINS 618config CPU_USE_DOMAINS
609 bool 619 bool
610 depends on MMU
611 default y if !CPU_32v6K
612 help 620 help
613 This option enables or disables the use of domain switching 621 This option enables or disables the use of domain switching
614 via the set_fs() function. 622 via the set_fs() function.
@@ -623,7 +631,7 @@ comment "Processor Features"
623 631
624config ARM_THUMB 632config ARM_THUMB
625 bool "Support Thumb user binaries" 633 bool "Support Thumb user binaries"
626 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON 634 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
627 default y 635 default y
628 help 636 help
629 Say Y if you want to include kernel support for running user space 637 Say Y if you want to include kernel support for running user space
@@ -644,7 +652,7 @@ config ARM_THUMBEE
644 652
645config SWP_EMULATE 653config SWP_EMULATE
646 bool "Emulate SWP/SWPB instructions" 654 bool "Emulate SWP/SWPB instructions"
647 depends on CPU_V7 && !CPU_V6 655 depends on !CPU_USE_DOMAINS && CPU_V7
648 select HAVE_PROC_CPU if PROC_FS 656 select HAVE_PROC_CPU if PROC_FS
649 default y if SMP 657 default y if SMP
650 help 658 help
@@ -681,7 +689,7 @@ config CPU_BIG_ENDIAN
681config CPU_ENDIAN_BE8 689config CPU_ENDIAN_BE8
682 bool 690 bool
683 depends on CPU_BIG_ENDIAN 691 depends on CPU_BIG_ENDIAN
684 default CPU_V6 || CPU_V7 692 default CPU_V6 || CPU_V6K || CPU_V7
685 help 693 help
686 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 694 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
687 695
@@ -747,7 +755,7 @@ config CPU_CACHE_ROUND_ROBIN
747 755
748config CPU_BPREDICT_DISABLE 756config CPU_BPREDICT_DISABLE
749 bool "Disable branch prediction" 757 bool "Disable branch prediction"
750 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 758 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
751 help 759 help
752 Say Y here to disable branch prediction. If unsure, say N. 760 Say Y here to disable branch prediction. If unsure, say N.
753 761
@@ -767,7 +775,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
767 775
768config DMA_CACHE_RWFO 776config DMA_CACHE_RWFO
769 bool "Enable read/write for ownership DMA cache maintenance" 777 bool "Enable read/write for ownership DMA cache maintenance"
770 depends on CPU_V6 && SMP 778 depends on CPU_V6K && SMP
771 default y 779 default y
772 help 780 help
773 The Snoop Control Unit on ARM11MPCore does not detect the 781 The Snoop Control Unit on ARM11MPCore does not detect the
@@ -823,7 +831,7 @@ config CACHE_L2X0
823config CACHE_PL310 831config CACHE_PL310
824 bool 832 bool
825 depends on CACHE_L2X0 833 depends on CACHE_L2X0
826 default y if CPU_V7 && !CPU_V6 834 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
827 help 835 help
828 This option enables optimisations for the PL310 cache 836 This option enables optimisations for the PL310 cache
829 controller. 837 controller.
@@ -845,16 +853,21 @@ config CACHE_XSC3L2
845 help 853 help
846 This option enables the L2 cache on XScale3. 854 This option enables the L2 cache on XScale3.
847 855
856config ARM_L1_CACHE_SHIFT_6
857 bool
858 help
859 Setting ARM L1 cache line size to 64 Bytes.
860
848config ARM_L1_CACHE_SHIFT 861config ARM_L1_CACHE_SHIFT
849 int 862 int
850 default 6 if ARM_L1_CACHE_SHIFT_6 863 default 6 if ARM_L1_CACHE_SHIFT_6
851 default 5 864 default 5
852 865
853config ARM_DMA_MEM_BUFFERABLE 866config ARM_DMA_MEM_BUFFERABLE
854 bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 867 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
855 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ 868 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
856 MACH_REALVIEW_PB11MP) 869 MACH_REALVIEW_PB11MP)
857 default y if CPU_V6 || CPU_V7 870 default y if CPU_V6 || CPU_V6K || CPU_V7
858 help 871 help
859 Historically, the kernel has used strongly ordered mappings to 872 Historically, the kernel has used strongly ordered mappings to
860 provide DMA coherent memory. With the advent of ARMv7, mapping 873 provide DMA coherent memory. With the advent of ARMv7, mapping
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 00d74a04af3a..bca7e61928c7 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -90,6 +90,7 @@ obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
90obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o 90obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o
91obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o 91obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
92obj-$(CONFIG_CPU_V6) += proc-v6.o 92obj-$(CONFIG_CPU_V6) += proc-v6.o
93obj-$(CONFIG_CPU_V6K) += proc-v6.o
93obj-$(CONFIG_CPU_V7) += proc-v7.o 94obj-$(CONFIG_CPU_V7) += proc-v7.o
94 95
95AFLAGS_proc-v6.o :=-Wa,-march=armv6 96AFLAGS_proc-v6.o :=-Wa,-march=armv6
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index f332df7f0d37..1478aa522144 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -20,11 +20,11 @@
20 */ 20 */
21 .align 5 21 .align 5
22ENTRY(v6_early_abort) 22ENTRY(v6_early_abort)
23#ifdef CONFIG_CPU_32v6K 23#ifdef CONFIG_CPU_V6
24 clrex
25#else
26 sub r1, sp, #4 @ Get unused stack location 24 sub r1, sp, #4 @ Get unused stack location
27 strex r0, r1, [r1] @ Clear the exclusive monitor 25 strex r0, r1, [r1] @ Clear the exclusive monitor
26#elif defined(CONFIG_CPU_32v6K)
27 clrex
28#endif 28#endif
29 mrc p15, 0, r1, c5, c0, 0 @ get FSR 29 mrc p15, 0, r1, c5, c0, 0 @ get FSR
30 mrc p15, 0, r0, c6, c0, 0 @ get FAR 30 mrc p15, 0, r0, c6, c0, 0 @ get FAR
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb95866..ef59099a5463 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
49static inline void cache_sync(void) 49static inline void cache_sync(void)
50{ 50{
51 void __iomem *base = l2x0_base; 51 void __iomem *base = l2x0_base;
52
53#ifdef CONFIG_ARM_ERRATA_753970
54 /* write to an unmmapped register */
55 writel_relaxed(0, base + L2X0_DUMMY_REG);
56#else
52 writel_relaxed(0, base + L2X0_CACHE_SYNC); 57 writel_relaxed(0, base + L2X0_CACHE_SYNC);
58#endif
53 cache_wait(base + L2X0_CACHE_SYNC, 1); 59 cache_wait(base + L2X0_CACHE_SYNC, 1);
54} 60}
55 61
@@ -67,18 +73,24 @@ static inline void l2x0_inv_line(unsigned long addr)
67 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 73 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
68} 74}
69 75
70#ifdef CONFIG_PL310_ERRATA_588369 76#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
71static void debug_writel(unsigned long val)
72{
73 extern void omap_smc1(u32 fn, u32 arg);
74 77
75 /* 78#define debug_writel(val) outer_cache.set_debug(val)
76 * Texas Instrument secure monitor api to modify the 79
77 * PL310 Debug Control Register. 80static void l2x0_set_debug(unsigned long val)
78 */ 81{
79 omap_smc1(0x100, val); 82 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
83}
84#else
85/* Optimised out for non-errata case */
86static inline void debug_writel(unsigned long val)
87{
80} 88}
81 89
90#define l2x0_set_debug NULL
91#endif
92
93#ifdef CONFIG_PL310_ERRATA_588369
82static inline void l2x0_flush_line(unsigned long addr) 94static inline void l2x0_flush_line(unsigned long addr)
83{ 95{
84 void __iomem *base = l2x0_base; 96 void __iomem *base = l2x0_base;
@@ -91,11 +103,6 @@ static inline void l2x0_flush_line(unsigned long addr)
91} 103}
92#else 104#else
93 105
94/* Optimised out for non-errata case */
95static inline void debug_writel(unsigned long val)
96{
97}
98
99static inline void l2x0_flush_line(unsigned long addr) 106static inline void l2x0_flush_line(unsigned long addr)
100{ 107{
101 void __iomem *base = l2x0_base; 108 void __iomem *base = l2x0_base;
@@ -119,9 +126,11 @@ static void l2x0_flush_all(void)
119 126
120 /* clean all ways */ 127 /* clean all ways */
121 spin_lock_irqsave(&l2x0_lock, flags); 128 spin_lock_irqsave(&l2x0_lock, flags);
129 debug_writel(0x03);
122 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 130 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
123 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 131 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
124 cache_sync(); 132 cache_sync();
133 debug_writel(0x00);
125 spin_unlock_irqrestore(&l2x0_lock, flags); 134 spin_unlock_irqrestore(&l2x0_lock, flags);
126} 135}
127 136
@@ -329,6 +338,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
329 outer_cache.flush_all = l2x0_flush_all; 338 outer_cache.flush_all = l2x0_flush_all;
330 outer_cache.inv_all = l2x0_inv_all; 339 outer_cache.inv_all = l2x0_inv_all;
331 outer_cache.disable = l2x0_disable; 340 outer_cache.disable = l2x0_disable;
341 outer_cache.set_debug = l2x0_set_debug;
332 342
333 printk(KERN_INFO "%s cache controller enabled\n", type); 343 printk(KERN_INFO "%s cache controller enabled\n", type);
334 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", 344 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 5164069ced42..cddd684364da 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -297,6 +297,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
297 memblock_reserve(__pa(_stext), _end - _stext); 297 memblock_reserve(__pa(_stext), _end - _stext);
298#endif 298#endif
299#ifdef CONFIG_BLK_DEV_INITRD 299#ifdef CONFIG_BLK_DEV_INITRD
300 if (phys_initrd_size &&
301 memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
302 pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
303 phys_initrd_start, phys_initrd_size);
304 phys_initrd_start = phys_initrd_size = 0;
305 }
300 if (phys_initrd_size) { 306 if (phys_initrd_size) {
301 memblock_reserve(phys_initrd_start, phys_initrd_size); 307 memblock_reserve(phys_initrd_start, phys_initrd_size);
302 308
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index b0a98305055c..afe209e1e1f8 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -31,7 +31,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
31 struct mm_struct *mm = current->mm; 31 struct mm_struct *mm = current->mm;
32 struct vm_area_struct *vma; 32 struct vm_area_struct *vma;
33 unsigned long start_addr; 33 unsigned long start_addr;
34#ifdef CONFIG_CPU_V6 34#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
35 unsigned int cache_type; 35 unsigned int cache_type;
36 int do_align = 0, aliasing = 0; 36 int do_align = 0, aliasing = 0;
37 37
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3c67e92f7d59..ff7b43b5885a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -827,16 +827,6 @@ static void __init sanity_check_meminfo(void)
827 * rather difficult. 827 * rather difficult.
828 */ 828 */
829 reason = "with VIPT aliasing cache"; 829 reason = "with VIPT aliasing cache";
830 } else if (is_smp() && tlb_ops_need_broadcast()) {
831 /*
832 * kmap_high needs to occasionally flush TLB entries,
833 * however, if the TLB entries need to be broadcast
834 * we may deadlock:
835 * kmap_high(irqs off)->flush_all_zero_pkmaps->
836 * flush_tlb_kernel_range->smp_call_function_many
837 * (must not be called with irqs off)
838 */
839 reason = "without hardware TLB ops broadcasting";
840 } 830 }
841 if (reason) { 831 if (reason) {
842 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", 832 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index bcf748d9f4e2..226e3d8351c2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -493,6 +493,9 @@ arm1020_processor_functions:
493 .word cpu_arm1020_dcache_clean_area 493 .word cpu_arm1020_dcache_clean_area
494 .word cpu_arm1020_switch_mm 494 .word cpu_arm1020_switch_mm
495 .word cpu_arm1020_set_pte_ext 495 .word cpu_arm1020_set_pte_ext
496 .word 0
497 .word 0
498 .word 0
496 .size arm1020_processor_functions, . - arm1020_processor_functions 499 .size arm1020_processor_functions, . - arm1020_processor_functions
497 500
498 .section ".rodata" 501 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index ab7ec26657ea..86d9c2cf0bce 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -474,6 +474,9 @@ arm1020e_processor_functions:
474 .word cpu_arm1020e_dcache_clean_area 474 .word cpu_arm1020e_dcache_clean_area
475 .word cpu_arm1020e_switch_mm 475 .word cpu_arm1020e_switch_mm
476 .word cpu_arm1020e_set_pte_ext 476 .word cpu_arm1020e_set_pte_ext
477 .word 0
478 .word 0
479 .word 0
477 .size arm1020e_processor_functions, . - arm1020e_processor_functions 480 .size arm1020e_processor_functions, . - arm1020e_processor_functions
478 481
479 .section ".rodata" 482 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 831c5e54e22f..83d3dd34f846 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -457,6 +457,9 @@ arm1022_processor_functions:
457 .word cpu_arm1022_dcache_clean_area 457 .word cpu_arm1022_dcache_clean_area
458 .word cpu_arm1022_switch_mm 458 .word cpu_arm1022_switch_mm
459 .word cpu_arm1022_set_pte_ext 459 .word cpu_arm1022_set_pte_ext
460 .word 0
461 .word 0
462 .word 0
460 .size arm1022_processor_functions, . - arm1022_processor_functions 463 .size arm1022_processor_functions, . - arm1022_processor_functions
461 464
462 .section ".rodata" 465 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index e3f7e9a166bf..686043ee7281 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -452,6 +452,9 @@ arm1026_processor_functions:
452 .word cpu_arm1026_dcache_clean_area 452 .word cpu_arm1026_dcache_clean_area
453 .word cpu_arm1026_switch_mm 453 .word cpu_arm1026_switch_mm
454 .word cpu_arm1026_set_pte_ext 454 .word cpu_arm1026_set_pte_ext
455 .word 0
456 .word 0
457 .word 0
455 .size arm1026_processor_functions, . - arm1026_processor_functions 458 .size arm1026_processor_functions, . - arm1026_processor_functions
456 459
457 .section .rodata 460 .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 6a7be1863edd..5f79dc4ce3fb 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -284,6 +284,9 @@ ENTRY(arm6_processor_functions)
284 .word cpu_arm6_dcache_clean_area 284 .word cpu_arm6_dcache_clean_area
285 .word cpu_arm6_switch_mm 285 .word cpu_arm6_switch_mm
286 .word cpu_arm6_set_pte_ext 286 .word cpu_arm6_set_pte_ext
287 .word 0
288 .word 0
289 .word 0
287 .size arm6_processor_functions, . - arm6_processor_functions 290 .size arm6_processor_functions, . - arm6_processor_functions
288 291
289/* 292/*
@@ -301,6 +304,9 @@ ENTRY(arm7_processor_functions)
301 .word cpu_arm7_dcache_clean_area 304 .word cpu_arm7_dcache_clean_area
302 .word cpu_arm7_switch_mm 305 .word cpu_arm7_switch_mm
303 .word cpu_arm7_set_pte_ext 306 .word cpu_arm7_set_pte_ext
307 .word 0
308 .word 0
309 .word 0
304 .size arm7_processor_functions, . - arm7_processor_functions 310 .size arm7_processor_functions, . - arm7_processor_functions
305 311
306 .section ".rodata" 312 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c285395f44b2..665266da143c 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -185,6 +185,9 @@ ENTRY(arm720_processor_functions)
185 .word cpu_arm720_dcache_clean_area 185 .word cpu_arm720_dcache_clean_area
186 .word cpu_arm720_switch_mm 186 .word cpu_arm720_switch_mm
187 .word cpu_arm720_set_pte_ext 187 .word cpu_arm720_set_pte_ext
188 .word 0
189 .word 0
190 .word 0
188 .size arm720_processor_functions, . - arm720_processor_functions 191 .size arm720_processor_functions, . - arm720_processor_functions
189 192
190 .section ".rodata" 193 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 38b27dcba727..6f9d12effee1 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -130,6 +130,9 @@ ENTRY(arm740_processor_functions)
130 .word cpu_arm740_dcache_clean_area 130 .word cpu_arm740_dcache_clean_area
131 .word cpu_arm740_switch_mm 131 .word cpu_arm740_switch_mm
132 .word 0 @ cpu_*_set_pte 132 .word 0 @ cpu_*_set_pte
133 .word 0
134 .word 0
135 .word 0
133 .size arm740_processor_functions, . - arm740_processor_functions 136 .size arm740_processor_functions, . - arm740_processor_functions
134 137
135 .section ".rodata" 138 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 0c9786de20af..e4c165ca6696 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -70,6 +70,9 @@ ENTRY(arm7tdmi_processor_functions)
70 .word cpu_arm7tdmi_dcache_clean_area 70 .word cpu_arm7tdmi_dcache_clean_area
71 .word cpu_arm7tdmi_switch_mm 71 .word cpu_arm7tdmi_switch_mm
72 .word 0 @ cpu_*_set_pte 72 .word 0 @ cpu_*_set_pte
73 .word 0
74 .word 0
75 .word 0
73 .size arm7tdmi_processor_functions, . - arm7tdmi_processor_functions 76 .size arm7tdmi_processor_functions, . - arm7tdmi_processor_functions
74 77
75 .section ".rodata" 78 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 6109f278a904..219980ec8b6e 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -387,6 +387,40 @@ ENTRY(cpu_arm920_set_pte_ext)
387#endif 387#endif
388 mov pc, lr 388 mov pc, lr
389 389
390/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
391.globl cpu_arm920_suspend_size
392.equ cpu_arm920_suspend_size, 4 * 3
393#ifdef CONFIG_PM
394ENTRY(cpu_arm920_do_suspend)
395 stmfd sp!, {r4 - r7, lr}
396 mrc p15, 0, r4, c13, c0, 0 @ PID
397 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
398 mrc p15, 0, r6, c2, c0, 0 @ TTB address
399 mrc p15, 0, r7, c1, c0, 0 @ Control register
400 stmia r0, {r4 - r7}
401 ldmfd sp!, {r4 - r7, pc}
402ENDPROC(cpu_arm920_do_suspend)
403
404ENTRY(cpu_arm920_do_resume)
405 mov ip, #0
406 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
407 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
408 ldmia r0, {r4 - r7}
409 mcr p15, 0, r4, c13, c0, 0 @ PID
410 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
411 mcr p15, 0, r6, c2, c0, 0 @ TTB address
412 mov r0, r7 @ control register
413 mov r2, r6, lsr #14 @ get TTB0 base
414 mov r2, r2, lsl #14
415 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
416 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
417 b cpu_resume_mmu
418ENDPROC(cpu_arm920_do_resume)
419#else
420#define cpu_arm920_do_suspend 0
421#define cpu_arm920_do_resume 0
422#endif
423
390 __CPUINIT 424 __CPUINIT
391 425
392 .type __arm920_setup, #function 426 .type __arm920_setup, #function
@@ -432,6 +466,9 @@ arm920_processor_functions:
432 .word cpu_arm920_dcache_clean_area 466 .word cpu_arm920_dcache_clean_area
433 .word cpu_arm920_switch_mm 467 .word cpu_arm920_switch_mm
434 .word cpu_arm920_set_pte_ext 468 .word cpu_arm920_set_pte_ext
469 .word cpu_arm920_suspend_size
470 .word cpu_arm920_do_suspend
471 .word cpu_arm920_do_resume
435 .size arm920_processor_functions, . - arm920_processor_functions 472 .size arm920_processor_functions, . - arm920_processor_functions
436 473
437 .section ".rodata" 474 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bb2f0f46a5e6..36154b1e792a 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -436,6 +436,9 @@ arm922_processor_functions:
436 .word cpu_arm922_dcache_clean_area 436 .word cpu_arm922_dcache_clean_area
437 .word cpu_arm922_switch_mm 437 .word cpu_arm922_switch_mm
438 .word cpu_arm922_set_pte_ext 438 .word cpu_arm922_set_pte_ext
439 .word 0
440 .word 0
441 .word 0
439 .size arm922_processor_functions, . - arm922_processor_functions 442 .size arm922_processor_functions, . - arm922_processor_functions
440 443
441 .section ".rodata" 444 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index c13e01accfe2..89c5e0009c4c 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -503,6 +503,9 @@ arm925_processor_functions:
503 .word cpu_arm925_dcache_clean_area 503 .word cpu_arm925_dcache_clean_area
504 .word cpu_arm925_switch_mm 504 .word cpu_arm925_switch_mm
505 .word cpu_arm925_set_pte_ext 505 .word cpu_arm925_set_pte_ext
506 .word 0
507 .word 0
508 .word 0
506 .size arm925_processor_functions, . - arm925_processor_functions 509 .size arm925_processor_functions, . - arm925_processor_functions
507 510
508 .section ".rodata" 511 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 42eb4315740b..6a4bdb2c94a7 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -401,6 +401,40 @@ ENTRY(cpu_arm926_set_pte_ext)
401#endif 401#endif
402 mov pc, lr 402 mov pc, lr
403 403
404/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
405.globl cpu_arm926_suspend_size
406.equ cpu_arm926_suspend_size, 4 * 3
407#ifdef CONFIG_PM
408ENTRY(cpu_arm926_do_suspend)
409 stmfd sp!, {r4 - r7, lr}
410 mrc p15, 0, r4, c13, c0, 0 @ PID
411 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
412 mrc p15, 0, r6, c2, c0, 0 @ TTB address
413 mrc p15, 0, r7, c1, c0, 0 @ Control register
414 stmia r0, {r4 - r7}
415 ldmfd sp!, {r4 - r7, pc}
416ENDPROC(cpu_arm926_do_suspend)
417
418ENTRY(cpu_arm926_do_resume)
419 mov ip, #0
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
421 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
422 ldmia r0, {r4 - r7}
423 mcr p15, 0, r4, c13, c0, 0 @ PID
424 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
425 mcr p15, 0, r6, c2, c0, 0 @ TTB address
426 mov r0, r7 @ control register
427 mov r2, r6, lsr #14 @ get TTB0 base
428 mov r2, r2, lsl #14
429 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
430 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
431 b cpu_resume_mmu
432ENDPROC(cpu_arm926_do_resume)
433#else
434#define cpu_arm926_do_suspend 0
435#define cpu_arm926_do_resume 0
436#endif
437
404 __CPUINIT 438 __CPUINIT
405 439
406 .type __arm926_setup, #function 440 .type __arm926_setup, #function
@@ -456,6 +490,9 @@ arm926_processor_functions:
456 .word cpu_arm926_dcache_clean_area 490 .word cpu_arm926_dcache_clean_area
457 .word cpu_arm926_switch_mm 491 .word cpu_arm926_switch_mm
458 .word cpu_arm926_set_pte_ext 492 .word cpu_arm926_set_pte_ext
493 .word cpu_arm926_suspend_size
494 .word cpu_arm926_do_suspend
495 .word cpu_arm926_do_resume
459 .size arm926_processor_functions, . - arm926_processor_functions 496 .size arm926_processor_functions, . - arm926_processor_functions
460 497
461 .section ".rodata" 498 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 7b11cdb9935f..26aea3f71c26 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -363,6 +363,9 @@ ENTRY(arm940_processor_functions)
363 .word cpu_arm940_dcache_clean_area 363 .word cpu_arm940_dcache_clean_area
364 .word cpu_arm940_switch_mm 364 .word cpu_arm940_switch_mm
365 .word 0 @ cpu_*_set_pte 365 .word 0 @ cpu_*_set_pte
366 .word 0
367 .word 0
368 .word 0
366 .size arm940_processor_functions, . - arm940_processor_functions 369 .size arm940_processor_functions, . - arm940_processor_functions
367 370
368 .section ".rodata" 371 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1a5bbf080342..8063345406fe 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -419,6 +419,9 @@ ENTRY(arm946_processor_functions)
419 .word cpu_arm946_dcache_clean_area 419 .word cpu_arm946_dcache_clean_area
420 .word cpu_arm946_switch_mm 420 .word cpu_arm946_switch_mm
421 .word 0 @ cpu_*_set_pte 421 .word 0 @ cpu_*_set_pte
422 .word 0
423 .word 0
424 .word 0
422 .size arm946_processor_functions, . - arm946_processor_functions 425 .size arm946_processor_functions, . - arm946_processor_functions
423 426
424 .section ".rodata" 427 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index db67e3134d7a..7b7ebd4d096d 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -70,6 +70,9 @@ ENTRY(arm9tdmi_processor_functions)
70 .word cpu_arm9tdmi_dcache_clean_area 70 .word cpu_arm9tdmi_dcache_clean_area
71 .word cpu_arm9tdmi_switch_mm 71 .word cpu_arm9tdmi_switch_mm
72 .word 0 @ cpu_*_set_pte 72 .word 0 @ cpu_*_set_pte
73 .word 0
74 .word 0
75 .word 0
73 .size arm9tdmi_processor_functions, . - arm9tdmi_processor_functions 76 .size arm9tdmi_processor_functions, . - arm9tdmi_processor_functions
74 77
75 .section ".rodata" 78 .section ".rodata"
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 7c9ad621f0e6..fc2a4ae15cf4 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -195,6 +195,9 @@ fa526_processor_functions:
195 .word cpu_fa526_dcache_clean_area 195 .word cpu_fa526_dcache_clean_area
196 .word cpu_fa526_switch_mm 196 .word cpu_fa526_switch_mm
197 .word cpu_fa526_set_pte_ext 197 .word cpu_fa526_set_pte_ext
198 .word 0
199 .word 0
200 .word 0
198 .size fa526_processor_functions, . - fa526_processor_functions 201 .size fa526_processor_functions, . - fa526_processor_functions
199 202
200 .section ".rodata" 203 .section ".rodata"
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index b4597edbff97..d3883eed7a4a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -554,6 +554,9 @@ feroceon_processor_functions:
554 .word cpu_feroceon_dcache_clean_area 554 .word cpu_feroceon_dcache_clean_area
555 .word cpu_feroceon_switch_mm 555 .word cpu_feroceon_switch_mm
556 .word cpu_feroceon_set_pte_ext 556 .word cpu_feroceon_set_pte_ext
557 .word 0
558 .word 0
559 .word 0
557 .size feroceon_processor_functions, . - feroceon_processor_functions 560 .size feroceon_processor_functions, . - feroceon_processor_functions
558 561
559 .section ".rodata" 562 .section ".rodata"
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 4458ee6aa713..9d4f2ae63370 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -388,6 +388,9 @@ mohawk_processor_functions:
388 .word cpu_mohawk_dcache_clean_area 388 .word cpu_mohawk_dcache_clean_area
389 .word cpu_mohawk_switch_mm 389 .word cpu_mohawk_switch_mm
390 .word cpu_mohawk_set_pte_ext 390 .word cpu_mohawk_set_pte_ext
391 .word 0
392 .word 0
393 .word 0
391 .size mohawk_processor_functions, . - mohawk_processor_functions 394 .size mohawk_processor_functions, . - mohawk_processor_functions
392 395
393 .section ".rodata" 396 .section ".rodata"
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 5aa8d59c2e85..46f09ed16b98 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -203,6 +203,9 @@ ENTRY(sa110_processor_functions)
203 .word cpu_sa110_dcache_clean_area 203 .word cpu_sa110_dcache_clean_area
204 .word cpu_sa110_switch_mm 204 .word cpu_sa110_switch_mm
205 .word cpu_sa110_set_pte_ext 205 .word cpu_sa110_set_pte_ext
206 .word 0
207 .word 0
208 .word 0
206 .size sa110_processor_functions, . - sa110_processor_functions 209 .size sa110_processor_functions, . - sa110_processor_functions
207 210
208 .section ".rodata" 211 .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 2ac4e6f10713..74483d1977fe 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -169,6 +169,42 @@ ENTRY(cpu_sa1100_set_pte_ext)
169#endif 169#endif
170 mov pc, lr 170 mov pc, lr
171 171
172.globl cpu_sa1100_suspend_size
173.equ cpu_sa1100_suspend_size, 4*4
174#ifdef CONFIG_PM
175ENTRY(cpu_sa1100_do_suspend)
176 stmfd sp!, {r4 - r7, lr}
177 mrc p15, 0, r4, c3, c0, 0 @ domain ID
178 mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
179 mrc p15, 0, r6, c13, c0, 0 @ PID
180 mrc p15, 0, r7, c1, c0, 0 @ control reg
181 stmia r0, {r4 - r7} @ store cp regs
182 ldmfd sp!, {r4 - r7, pc}
183ENDPROC(cpu_sa1100_do_suspend)
184
185ENTRY(cpu_sa1100_do_resume)
186 ldmia r0, {r4 - r7} @ load cp regs
187 mov r1, #0
188 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
190 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
191 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
192
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
194 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
195 mcr p15, 0, r6, c13, c0, 0 @ PID
196 mov r0, r7 @ control register
197 mov r2, r5, lsr #14 @ get TTB0 base
198 mov r2, r2, lsl #14
199 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
200 PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
201 b cpu_resume_mmu
202ENDPROC(cpu_sa1100_do_resume)
203#else
204#define cpu_sa1100_do_suspend 0
205#define cpu_sa1100_do_resume 0
206#endif
207
172 __CPUINIT 208 __CPUINIT
173 209
174 .type __sa1100_setup, #function 210 .type __sa1100_setup, #function
@@ -218,6 +254,9 @@ ENTRY(sa1100_processor_functions)
218 .word cpu_sa1100_dcache_clean_area 254 .word cpu_sa1100_dcache_clean_area
219 .word cpu_sa1100_switch_mm 255 .word cpu_sa1100_switch_mm
220 .word cpu_sa1100_set_pte_ext 256 .word cpu_sa1100_set_pte_ext
257 .word cpu_sa1100_suspend_size
258 .word cpu_sa1100_do_suspend
259 .word cpu_sa1100_do_resume
221 .size sa1100_processor_functions, . - sa1100_processor_functions 260 .size sa1100_processor_functions, . - sa1100_processor_functions
222 261
223 .section ".rodata" 262 .section ".rodata"
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 59a7e1ffe7bc..832b6bdc192c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -121,6 +121,53 @@ ENTRY(cpu_v6_set_pte_ext)
121#endif 121#endif
122 mov pc, lr 122 mov pc, lr
123 123
124/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
125.globl cpu_v6_suspend_size
126.equ cpu_v6_suspend_size, 4 * 8
127#ifdef CONFIG_PM
128ENTRY(cpu_v6_do_suspend)
129 stmfd sp!, {r4 - r11, lr}
130 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
131 mrc p15, 0, r5, c13, c0, 1 @ Context ID
132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
135 mrc p15, 0, r9, c1, c0, 1 @ auxillary control register
136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
137 mrc p15, 0, r11, c1, c0, 0 @ control register
138 stmia r0, {r4 - r11}
139 ldmfd sp!, {r4- r11, pc}
140ENDPROC(cpu_v6_do_suspend)
141
142ENTRY(cpu_v6_do_resume)
143 mov ip, #0
144 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
145 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
147 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
148 ldmia r0, {r4 - r11}
149 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
150 mcr p15, 0, r5, c13, c0, 1 @ Context ID
151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
154 mcr p15, 0, r9, c1, c0, 1 @ auxillary control register
155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
157 mcr p15, 0, ip, c7, c5, 4 @ ISB
158 mov r0, r11 @ control register
159 mov r2, r7, lsr #14 @ get TTB0 base
160 mov r2, r2, lsl #14
161 ldr r3, cpu_resume_l1_flags
162 b cpu_resume_mmu
163ENDPROC(cpu_v6_do_resume)
164cpu_resume_l1_flags:
165 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
166 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
167#else
168#define cpu_v6_do_suspend 0
169#define cpu_v6_do_resume 0
170#endif
124 171
125 172
126 .type cpu_v6_name, #object 173 .type cpu_v6_name, #object
@@ -206,6 +253,9 @@ ENTRY(v6_processor_functions)
206 .word cpu_v6_dcache_clean_area 253 .word cpu_v6_dcache_clean_area
207 .word cpu_v6_switch_mm 254 .word cpu_v6_switch_mm
208 .word cpu_v6_set_pte_ext 255 .word cpu_v6_set_pte_ext
256 .word cpu_v6_suspend_size
257 .word cpu_v6_do_suspend
258 .word cpu_v6_do_resume
209 .size v6_processor_functions, . - v6_processor_functions 259 .size v6_processor_functions, . - v6_processor_functions
210 260
211 .section ".rodata" 261 .section ".rodata"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b56b4e..262fa88a7439 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,10 +108,16 @@ ENTRY(cpu_v7_switch_mm)
108#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110#endif 110#endif
111#ifdef CONFIG_ARM_ERRATA_754322
112 dsb
113#endif
111 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
112 isb 115 isb
1131: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
114 isb 117 isb
118#ifdef CONFIG_ARM_ERRATA_754322
119 dsb
120#endif
115 mcr p15, 0, r1, c13, c0, 1 @ set context ID 121 mcr p15, 0, r1, c13, c0, 1 @ set context ID
116 isb 122 isb
117#endif 123#endif
@@ -171,6 +177,87 @@ cpu_v7_name:
171 .ascii "ARMv7 Processor" 177 .ascii "ARMv7 Processor"
172 .align 178 .align
173 179
180 /*
181 * Memory region attributes with SCTLR.TRE=1
182 *
183 * n = TEX[0],C,B
184 * TR = PRRR[2n+1:2n] - memory type
185 * IR = NMRR[2n+1:2n] - inner cacheable property
186 * OR = NMRR[2n+17:2n+16] - outer cacheable property
187 *
188 * n TR IR OR
189 * UNCACHED 000 00
190 * BUFFERABLE 001 10 00 00
191 * WRITETHROUGH 010 10 10 10
192 * WRITEBACK 011 10 11 11
193 * reserved 110
194 * WRITEALLOC 111 10 01 01
195 * DEV_SHARED 100 01
196 * DEV_NONSHARED 100 01
197 * DEV_WC 001 10
198 * DEV_CACHED 011 10
199 *
200 * Other attributes:
201 *
202 * DS0 = PRRR[16] = 0 - device shareable property
203 * DS1 = PRRR[17] = 1 - device shareable property
204 * NS0 = PRRR[18] = 0 - normal shareable property
205 * NS1 = PRRR[19] = 1 - normal shareable property
206 * NOS = PRRR[24+n] = 1 - not outer shareable
207 */
208.equ PRRR, 0xff0a81a8
209.equ NMRR, 0x40e040e0
210
211/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
212.globl cpu_v7_suspend_size
213.equ cpu_v7_suspend_size, 4 * 8
214#ifdef CONFIG_PM
215ENTRY(cpu_v7_do_suspend)
216 stmfd sp!, {r4 - r11, lr}
217 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
218 mrc p15, 0, r5, c13, c0, 1 @ Context ID
219 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
220 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
221 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
222 mrc p15, 0, r9, c1, c0, 0 @ Control register
223 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
224 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
225 stmia r0, {r4 - r11}
226 ldmfd sp!, {r4 - r11, pc}
227ENDPROC(cpu_v7_do_suspend)
228
229ENTRY(cpu_v7_do_resume)
230 mov ip, #0
231 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
232 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
233 ldmia r0, {r4 - r11}
234 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
235 mcr p15, 0, r5, c13, c0, 1 @ Context ID
236 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
240 mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register
241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
242 ldr r4, =PRRR @ PRRR
243 ldr r5, =NMRR @ NMRR
244 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
245 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
246 isb
247 mov r0, r9 @ control register
248 mov r2, r7, lsr #14 @ get TTB0 base
249 mov r2, r2, lsl #14
250 ldr r3, cpu_resume_l1_flags
251 b cpu_resume_mmu
252ENDPROC(cpu_v7_do_resume)
253cpu_resume_l1_flags:
254 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
255 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
256#else
257#define cpu_v7_do_suspend 0
258#define cpu_v7_do_resume 0
259#endif
260
174 __CPUINIT 261 __CPUINIT
175 262
176/* 263/*
@@ -264,6 +351,12 @@ __v7_setup:
264 orreq r10, r10, #1 << 6 @ set bit #6 351 orreq r10, r10, #1 << 6 @ set bit #6
265 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 352 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
266#endif 353#endif
354#ifdef CONFIG_ARM_ERRATA_751472
355 cmp r6, #0x30 @ present prior to r3p0
356 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
357 orrlt r10, r10, #1 << 11 @ set bit #11
358 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
359#endif
267 360
2683: mov r10, #0 3613: mov r10, #0
269#ifdef HARVARD_CACHE 362#ifdef HARVARD_CACHE
@@ -276,36 +369,8 @@ __v7_setup:
276 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
277 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
278 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 371 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
279 /* 372 ldr r5, =PRRR @ PRRR
280 * Memory region attributes with SCTLR.TRE=1 373 ldr r6, =NMRR @ NMRR
281 *
282 * n = TEX[0],C,B
283 * TR = PRRR[2n+1:2n] - memory type
284 * IR = NMRR[2n+1:2n] - inner cacheable property
285 * OR = NMRR[2n+17:2n+16] - outer cacheable property
286 *
287 * n TR IR OR
288 * UNCACHED 000 00
289 * BUFFERABLE 001 10 00 00
290 * WRITETHROUGH 010 10 10 10
291 * WRITEBACK 011 10 11 11
292 * reserved 110
293 * WRITEALLOC 111 10 01 01
294 * DEV_SHARED 100 01
295 * DEV_NONSHARED 100 01
296 * DEV_WC 001 10
297 * DEV_CACHED 011 10
298 *
299 * Other attributes:
300 *
301 * DS0 = PRRR[16] = 0 - device shareable property
302 * DS1 = PRRR[17] = 1 - device shareable property
303 * NS0 = PRRR[18] = 0 - normal shareable property
304 * NS1 = PRRR[19] = 1 - normal shareable property
305 * NOS = PRRR[24+n] = 1 - not outer shareable
306 */
307 ldr r5, =0xff0a81a8 @ PRRR
308 ldr r6, =0x40e040e0 @ NMRR
309 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
310 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 375 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
311#endif 376#endif
@@ -351,6 +416,9 @@ ENTRY(v7_processor_functions)
351 .word cpu_v7_dcache_clean_area 416 .word cpu_v7_dcache_clean_area
352 .word cpu_v7_switch_mm 417 .word cpu_v7_switch_mm
353 .word cpu_v7_set_pte_ext 418 .word cpu_v7_set_pte_ext
419 .word 0
420 .word 0
421 .word 0
354 .size v7_processor_functions, . - v7_processor_functions 422 .size v7_processor_functions, . - v7_processor_functions
355 423
356 .section ".rodata" 424 .section ".rodata"
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index ec26355cb7c2..63d8b2044e84 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -413,9 +413,52 @@ ENTRY(cpu_xsc3_set_pte_ext)
413 mov pc, lr 413 mov pc, lr
414 414
415 .ltorg 415 .ltorg
416
417 .align 416 .align
418 417
418.globl cpu_xsc3_suspend_size
419.equ cpu_xsc3_suspend_size, 4 * 8
420#ifdef CONFIG_PM
421ENTRY(cpu_xsc3_do_suspend)
422 stmfd sp!, {r4 - r10, lr}
423 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
424 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
425 mrc p15, 0, r6, c13, c0, 0 @ PID
426 mrc p15, 0, r7, c3, c0, 0 @ domain ID
427 mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
428 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
429 mrc p15, 0, r10, c1, c0, 0 @ control reg
430 bic r4, r4, #2 @ clear frequency change bit
431 stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs
432 ldmia sp!, {r4 - r10, pc}
433ENDPROC(cpu_xsc3_do_suspend)
434
435ENTRY(cpu_xsc3_do_resume)
436 ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs
437 mov ip, #0
438 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
439 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
440 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
441 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
442 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
443 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
444 mcr p15, 0, r6, c13, c0, 0 @ PID
445 mcr p15, 0, r7, c3, c0, 0 @ domain ID
446 mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
447 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
448
449 @ temporarily map resume_turn_on_mmu into the page table,
450 @ otherwise prefetch abort occurs after MMU is turned on
451 mov r0, r10 @ control register
452 mov r2, r8, lsr #14 @ get TTB0 base
453 mov r2, r2, lsl #14
454 ldr r3, =0x542e @ section flags
455 b cpu_resume_mmu
456ENDPROC(cpu_xsc3_do_resume)
457#else
458#define cpu_xsc3_do_suspend 0
459#define cpu_xsc3_do_resume 0
460#endif
461
419 __CPUINIT 462 __CPUINIT
420 463
421 .type __xsc3_setup, #function 464 .type __xsc3_setup, #function
@@ -476,6 +519,9 @@ ENTRY(xsc3_processor_functions)
476 .word cpu_xsc3_dcache_clean_area 519 .word cpu_xsc3_dcache_clean_area
477 .word cpu_xsc3_switch_mm 520 .word cpu_xsc3_switch_mm
478 .word cpu_xsc3_set_pte_ext 521 .word cpu_xsc3_set_pte_ext
522 .word cpu_xsc3_suspend_size
523 .word cpu_xsc3_do_suspend
524 .word cpu_xsc3_do_resume
479 .size xsc3_processor_functions, . - xsc3_processor_functions 525 .size xsc3_processor_functions, . - xsc3_processor_functions
480 526
481 .section ".rodata" 527 .section ".rodata"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 5a37c5e45c41..086038cd86ab 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -513,11 +513,49 @@ ENTRY(cpu_xscale_set_pte_ext)
513 xscale_set_pte_ext_epilogue 513 xscale_set_pte_ext_epilogue
514 mov pc, lr 514 mov pc, lr
515 515
516
517 .ltorg 516 .ltorg
518
519 .align 517 .align
520 518
519.globl cpu_xscale_suspend_size
520.equ cpu_xscale_suspend_size, 4 * 7
521#ifdef CONFIG_PM
522ENTRY(cpu_xscale_do_suspend)
523 stmfd sp!, {r4 - r10, lr}
524 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
525 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
526 mrc p15, 0, r6, c13, c0, 0 @ PID
527 mrc p15, 0, r7, c3, c0, 0 @ domain ID
528 mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
529 mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg
530 mrc p15, 0, r10, c1, c0, 0 @ control reg
531 bic r4, r4, #2 @ clear frequency change bit
532 stmia r0, {r4 - r10} @ store cp regs
533 ldmfd sp!, {r4 - r10, pc}
534ENDPROC(cpu_xscale_do_suspend)
535
536ENTRY(cpu_xscale_do_resume)
537 ldmia r0, {r4 - r10} @ load cp regs
538 mov ip, #0
539 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
540 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
541 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
542 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
543 mcr p15, 0, r6, c13, c0, 0 @ PID
544 mcr p15, 0, r7, c3, c0, 0 @ domain ID
545 mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
546 mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg
547 mov r0, r10 @ control register
548 mov r2, r8, lsr #14 @ get TTB0 base
549 mov r2, r2, lsl #14
550 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
551 PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
552 b cpu_resume_mmu
553ENDPROC(cpu_xscale_do_resume)
554#else
555#define cpu_xscale_do_suspend 0
556#define cpu_xscale_do_resume 0
557#endif
558
521 __CPUINIT 559 __CPUINIT
522 560
523 .type __xscale_setup, #function 561 .type __xscale_setup, #function
@@ -565,6 +603,9 @@ ENTRY(xscale_processor_functions)
565 .word cpu_xscale_dcache_clean_area 603 .word cpu_xscale_dcache_clean_area
566 .word cpu_xscale_switch_mm 604 .word cpu_xscale_switch_mm
567 .word cpu_xscale_set_pte_ext 605 .word cpu_xscale_set_pte_ext
606 .word cpu_xscale_suspend_size
607 .word cpu_xscale_do_suspend
608 .word cpu_xscale_do_resume
568 .size xscale_processor_functions, . - xscale_processor_functions 609 .size xscale_processor_functions, . - xscale_processor_functions
569 610
570 .section ".rodata" 611 .section ".rodata"
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
index 935993e1b1ef..036fdbfdd62f 100644
--- a/arch/arm/mm/vmregion.c
+++ b/arch/arm/mm/vmregion.c
@@ -38,7 +38,7 @@ struct arm_vmregion *
38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align, 38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
39 size_t size, gfp_t gfp) 39 size_t size, gfp_t gfp)
40{ 40{
41 unsigned long addr = head->vm_start, end = head->vm_end - size; 41 unsigned long start = head->vm_start, addr = head->vm_end;
42 unsigned long flags; 42 unsigned long flags;
43 struct arm_vmregion *c, *new; 43 struct arm_vmregion *c, *new;
44 44
@@ -54,21 +54,20 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
54 54
55 spin_lock_irqsave(&head->vm_lock, flags); 55 spin_lock_irqsave(&head->vm_lock, flags);
56 56
57 list_for_each_entry(c, &head->vm_list, vm_list) { 57 addr = rounddown(addr - size, align);
58 if ((addr + size) < addr) 58 list_for_each_entry_reverse(c, &head->vm_list, vm_list) {
59 goto nospc; 59 if (addr >= c->vm_end)
60 if ((addr + size) <= c->vm_start)
61 goto found; 60 goto found;
62 addr = ALIGN(c->vm_end, align); 61 addr = rounddown(c->vm_start - size, align);
63 if (addr > end) 62 if (addr < start)
64 goto nospc; 63 goto nospc;
65 } 64 }
66 65
67 found: 66 found:
68 /* 67 /*
69 * Insert this entry _before_ the one we found. 68 * Insert this entry after the one we found.
70 */ 69 */
71 list_add_tail(&new->vm_list, &c->vm_list); 70 list_add(&new->vm_list, &c->vm_list);
72 new->vm_start = addr; 71 new->vm_start = addr;
73 new->vm_end = addr + size; 72 new->vm_end = addr + size;
74 new->vm_active = 1; 73 new->vm_active = 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 20:59:24 -0500