7 files changed, 31 insertions, 26 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1f8fed94c2a4..ca8ecdee47d8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -446,7 +446,6 @@ config CPU_32v5
 
 config CPU_32v6
         bool
-        select CPU_USE_DOMAINS if CPU_V6 && MMU
         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 
 config CPU_32v6K
@@ -671,7 +670,7 @@ config ARM_VIRT_EXT
 
 config SWP_EMULATE
         bool "Emulate SWP/SWPB instructions"
-        depends on !CPU_USE_DOMAINS && CPU_V7
+        depends on CPU_V7
         default y if SMP
         select HAVE_PROC_CPU if PROC_FS
         help
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 48bc3c0a87ce..aae891820f8f 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -331,7 +331,9 @@ static void __init enable_l2(void)
                         enable_icache();
                 if (d)
                         enable_dcache();
-        }
+        } else
+                pr_err(FW_BUG
+                       "Feroceon L2: bootloader left the L2 cache on!\n");
 }
 
 void __init feroceon_l2_init(int __l2_wt_override)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 11b3914660d2..c9c6acdf90cc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -284,9 +284,6 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
-#ifdef CONFIG_HUGETLB_PAGE
-#warning ARM Coherent DMA allocator does not (yet) support huge TLB
-#endif
 
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
                                      pgprot_t prot, struct page **ret_page,
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a623cb3ad012..b68c6b22e1c8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -516,6 +516,16 @@ static void __init build_mem_type_table(void)
         s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
 
         /*
+         * We don't use domains on ARMv6 (since this causes problems with
+         * v6/v7 kernels), so we must use a separate memory type for user
+         * r/o, kernel r/w to map the vectors page.
+         */
+#ifndef CONFIG_ARM_LPAE
+        if (cpu_arch == CPU_ARCH_ARMv6)
+                vecs_pgprot |= L_PTE_MT_VECTORS;
+#endif
+
+        /*
          * ARMv6 and above have extended page tables.
          */
         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e3c48a3fe063..ee1d80593958 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -112,13 +112,9 @@
  *  100x   1   0   1    r/o     no acc
  *  10x0   1   0   1    r/o     no acc
  *  1011   0   0   1    r/w     no acc
- *  110x   0   1   0    r/w     r/o
- *  11x0   0   1   0    r/w     r/o
- *  1111   0   1   1    r/w     r/w
- *
- * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
  *  110x   1   1   1    r/o     r/o
  *  11x0   1   1   1    r/o     r/o
+ *  1111   0   1   1    r/w     r/w
  */
         .macro  armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -137,7 +133,7 @@
         .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
         .long   0x00                                            @ unused
         .long   0x00                                            @ unused
-        .long   0x00                                            @ unused
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX    @ L_PTE_MT_VECTORS
         .endm
 
         .macro  armv6_set_pte_ext pfx
@@ -158,24 +154,21 @@
 
         tst     r1, #L_PTE_USER
         orrne   r3, r3, #PTE_EXT_AP1
-#ifdef CONFIG_CPU_USE_DOMAINS
-        @ allow kernel read/write access to read-only user pages
         tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-#endif
+
+        @ user read-only -> kernel read-only
+        bicne   r3, r3, #PTE_EXT_AP0
 
         tst     r1, #L_PTE_XN
         orrne   r3, r3, #PTE_EXT_XN
 
-        orr     r3, r3, r2
+        eor     r3, r3, r2
 
         tst     r1, #L_PTE_YOUNG
         tstne   r1, #L_PTE_PRESENT
         moveq   r3, #0
-#ifndef CONFIG_CPU_USE_DOMAINS
         tstne   r1, #L_PTE_NONE
         movne   r3, #0
-#endif
 
         str     r3, [r0]
         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index bdd3be4be77a..1f52915f2b28 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -90,21 +90,14 @@ ENTRY(cpu_v7_set_pte_ext)
 
         tst     r1, #L_PTE_USER
         orrne   r3, r3, #PTE_EXT_AP1
-#ifdef CONFIG_CPU_USE_DOMAINS
-        @ allow kernel read/write access to read-only user pages
-        tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-#endif
 
         tst     r1, #L_PTE_XN
         orrne   r3, r3, #PTE_EXT_XN
 
         tst     r1, #L_PTE_YOUNG
         tstne   r1, #L_PTE_VALID
-#ifndef CONFIG_CPU_USE_DOMAINS
         eorne   r1, r1, #L_PTE_NONE
         tstne   r1, #L_PTE_NONE
-#endif
         moveq   r3, #0
 
  ARM(   str     r3, [r0, #2048]! )
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 74f6033e76dd..195731d3813b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -192,6 +192,7 @@ __v7_cr7mp_setup:
         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
         b       1f
 __v7_ca7mp_setup:
+__v7_ca12mp_setup:
 __v7_ca15mp_setup:
         mov     r10, #0
 1:
@@ -484,6 +485,16 @@ __v7_ca7mp_proc_info:
         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
         /*
+         * ARM Ltd. Cortex A12 processor.
+         */
+        .type   __v7_ca12mp_proc_info, #object
+__v7_ca12mp_proc_info:
+        .long   0x410fc0d0
+        .long   0xff0ffff0
+        __v7_proc __v7_ca12mp_setup
+        .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
+
+        /*
          * ARM Ltd. Cortex A15 processor.
          */
         .type   __v7_ca15mp_proc_info, #object