1 files changed, 67 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 846d279f3176..7cd0028cab8e 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,6 +169,63 @@ __v7_ca15mp_setup:
         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
         mcreq   p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+/* Auxiliary Debug Modes Control 1 Register */
+#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
+#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
+#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
+#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
+
+/* Auxiliary Debug Modes Control 2 Register */
+#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
+#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
+#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
+#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
+#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
+#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
+                            PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
+
+/* Auxiliary Functional Modes Control Register 0 */
+#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
+#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
+#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
+
+/* Auxiliary Debug Modes Control 0 Register */
+#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
+
+        /* Auxiliary Debug Modes Control 1 Register */
+        mrc     p15, 1, r0, c15, c1, 1
+        orr     r0, r0, #PJ4B_CLEAN_LINE
+        orr     r0, r0, #PJ4B_BCK_OFF_STREX
+        orr     r0, r0, #PJ4B_INTER_PARITY
+        bic     r0, r0, #PJ4B_STATIC_BP
+        mcr     p15, 1, r0, c15, c1, 1
+
+        /* Auxiliary Debug Modes Control 2 Register */
+        mrc     p15, 1, r0, c15, c1, 2
+        bic     r0, r0, #PJ4B_FAST_LDR
+        orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
+        mcr     p15, 1, r0, c15, c1, 2
+
+        /* Auxiliary Functional Modes Control Register 0 */
+        mrc     p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP
+        orr     r0, r0, #PJ4B_SMP_CFB
+#endif
+        orr     r0, r0, #PJ4B_L1_PAR_CHK
+        orr     r0, r0, #PJ4B_BROADCAST_CACHE
+        mcr     p15, 1, r0, c15, c2, 0
+
+        /* Auxiliary Debug Modes Control 0 Register */
+        mrc     p15, 1, r0, c15, c1, 0
+        orr     r0, r0, #PJ4B_WFI_WFE
+        mcr     p15, 1, r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
 __v7_setup:
         adr     r12, __v7_setup_stack           @ the local stack
         stmia   r12, {r0-r5, r7, r9, r11, lr}
@@ -342,6 +399,16 @@ __v7_ca9mp_proc_info:
         .long   0xff0ffff0
         __v7_proc __v7_ca9mp_setup
         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+        /*
+         * Marvell PJ4B processor.
+         */
+        .type   __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+        .long   0x562f5840
+        .long   0xfffffff0
+        __v7_proc __v7_pj4b_setup
+        .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 #endif  /* CONFIG_ARM_LPAE */
 
         /*