diff options
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f584d3f5b37c..2c73a7301ff7 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -75,14 +75,14 @@ ENTRY(cpu_v7_do_idle) | |||
75 | ENDPROC(cpu_v7_do_idle) | 75 | ENDPROC(cpu_v7_do_idle) |
76 | 76 | ||
77 | ENTRY(cpu_v7_dcache_clean_area) | 77 | ENTRY(cpu_v7_dcache_clean_area) |
78 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | 78 | ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW |
79 | ALT_UP(W(nop)) | ||
79 | dcache_line_size r2, r3 | 80 | dcache_line_size r2, r3 |
80 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 81 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
81 | add r0, r0, r2 | 82 | add r0, r0, r2 |
82 | subs r1, r1, r2 | 83 | subs r1, r1, r2 |
83 | bhi 1b | 84 | bhi 1b |
84 | dsb | 85 | dsb |
85 | #endif | ||
86 | mov pc, lr | 86 | mov pc, lr |
87 | ENDPROC(cpu_v7_dcache_clean_area) | 87 | ENDPROC(cpu_v7_dcache_clean_area) |
88 | 88 | ||
@@ -402,6 +402,8 @@ __v7_ca9mp_proc_info: | |||
402 | __v7_proc __v7_ca9mp_setup | 402 | __v7_proc __v7_ca9mp_setup |
403 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info | 403 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
404 | 404 | ||
405 | #endif /* CONFIG_ARM_LPAE */ | ||
406 | |||
405 | /* | 407 | /* |
406 | * Marvell PJ4B processor. | 408 | * Marvell PJ4B processor. |
407 | */ | 409 | */ |
@@ -411,7 +413,6 @@ __v7_pj4b_proc_info: | |||
411 | .long 0xfffffff0 | 413 | .long 0xfffffff0 |
412 | __v7_proc __v7_pj4b_setup | 414 | __v7_proc __v7_pj4b_setup |
413 | .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info | 415 | .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info |
414 | #endif /* CONFIG_ARM_LPAE */ | ||
415 | 416 | ||
416 | /* | 417 | /* |
417 | * ARM Ltd. Cortex A7 processor. | 418 | * ARM Ltd. Cortex A7 processor. |