1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 09d241ae2dbe..89f97ac648a9 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -43,7 +43,7 @@ ENTRY(cpu_sa1100_proc_init)
        mov     r0, #0
        mcr     p15, 0, r0, c15, c1, 2          @ Enable clock switching
        mcr     p15, 0, r0, c9, c0, 5           @ Allow read-buffer operations from userland
-        mov     pc, lr
+        ret     lr
 /*
 * cpu_sa1100_proc_fin()
@@ -58,7 +58,7 @@ ENTRY(cpu_sa1100_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        mov     pc, lr
+        ret     lr
 /*
 * cpu_sa1100_reset(loc)
@@ -82,7 +82,7 @@ ENTRY(cpu_sa1100_reset)
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-        mov     pc, r0
+        ret     r0
 ENDPROC(cpu_sa1100_reset)
        .popsection
@@ -113,7 +113,7 @@ ENTRY(cpu_sa1100_do_idle)
        mcr     p15, 0, r0, c15, c8, 2          @ wait for interrupt
        mov     r0, r0                          @ safety
        mcr     p15, 0, r0, c15, c1, 2          @ enable clock switching
-        mov     pc, lr
+        ret     lr
 /* ================================= CACHE ================================ */
@@ -131,7 +131,7 @@ ENTRY(cpu_sa1100_dcache_clean_area)
        add     r0, r0, #DCACHELINESIZE
        subs    r1, r1, #DCACHELINESIZE
        bhi     1b
-        mov     pc, lr
+        ret     lr
 /* =============================== PageTable ============================== */
@@ -152,7 +152,7 @@ ENTRY(cpu_sa1100_switch_mm)
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
        ldr     pc, [sp], #4
 #else
-        mov     pc, lr
+        ret     lr
 #endif
 /*
@@ -168,7 +168,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
-        mov     pc, lr
+        ret     lr
 .globl  cpu_sa1100_suspend_size
 .equ    cpu_sa1100_suspend_size, 4 * 3
@@ -211,7 +211,7 @@ __sa1100_setup:
        mrc     p15, 0, r0, c1, c0              @ get control register v4
        bic     r0, r0, r5
        orr     r0, r0, r6
-        mov     pc, lr
+        ret     lr
        .size   __sa1100_setup, . - __sa1100_setup
        /*

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 09d241ae2dbe..89f97ac648a9 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S
@@ -43,7 +43,7 @@ ENTRY(cpu_sa1100_proc_init)
43	mov r0, #0	43	mov r0, #0
44	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching	44	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45	mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland	45	mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
46	mov pc, lr	46	ret lr
47		47
48	/*	48	/*
49	* cpu_sa1100_proc_fin()	49	* cpu_sa1100_proc_fin()
@@ -58,7 +58,7 @@ ENTRY(cpu_sa1100_proc_fin)
58	bic r0, r0, #0x1000 @ ...i............	58	bic r0, r0, #0x1000 @ ...i............
59	bic r0, r0, #0x000e @ ............wca.	59	bic r0, r0, #0x000e @ ............wca.
60	mcr p15, 0, r0, c1, c0, 0 @ disable caches	60	mcr p15, 0, r0, c1, c0, 0 @ disable caches
61	mov pc, lr	61	ret lr
62		62
63	/*	63	/*
64	* cpu_sa1100_reset(loc)	64	* cpu_sa1100_reset(loc)
@@ -82,7 +82,7 @@ ENTRY(cpu_sa1100_reset)
82	bic ip, ip, #0x000f @ ............wcam	82	bic ip, ip, #0x000f @ ............wcam
83	bic ip, ip, #0x1100 @ ...i...s........	83	bic ip, ip, #0x1100 @ ...i...s........
84	mcr p15, 0, ip, c1, c0, 0 @ ctrl register	84	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85	mov pc, r0	85	ret r0
86	ENDPROC(cpu_sa1100_reset)	86	ENDPROC(cpu_sa1100_reset)
87	.popsection	87	.popsection
88		88
@@ -113,7 +113,7 @@ ENTRY(cpu_sa1100_do_idle)
113	mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt	113	mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
114	mov r0, r0 @ safety	114	mov r0, r0 @ safety
115	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching	115	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
116	mov pc, lr	116	ret lr
117		117
118	/* ================================= CACHE ================================ */	118	/* ================================= CACHE ================================ */
119		119
@@ -131,7 +131,7 @@ ENTRY(cpu_sa1100_dcache_clean_area)
131	add r0, r0, #DCACHELINESIZE	131	add r0, r0, #DCACHELINESIZE
132	subs r1, r1, #DCACHELINESIZE	132	subs r1, r1, #DCACHELINESIZE
133	bhi 1b	133	bhi 1b
134	mov pc, lr	134	ret lr
135		135
136	/* =============================== PageTable ============================== */	136	/* =============================== PageTable ============================== */
137		137
@@ -152,7 +152,7 @@ ENTRY(cpu_sa1100_switch_mm)
152	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs	152	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
153	ldr pc, [sp], #4	153	ldr pc, [sp], #4
154	#else	154	#else
155	mov pc, lr	155	ret lr
156	#endif	156	#endif
157		157
158	/*	158	/*
@@ -168,7 +168,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
168	mcr p15, 0, r0, c7, c10, 1 @ clean D entry	168	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169	mcr p15, 0, r0, c7, c10, 4 @ drain WB	169	mcr p15, 0, r0, c7, c10, 4 @ drain WB
170	#endif	170	#endif
171	mov pc, lr	171	ret lr
172		172
173	.globl cpu_sa1100_suspend_size	173	.globl cpu_sa1100_suspend_size
174	.equ cpu_sa1100_suspend_size, 4 * 3	174	.equ cpu_sa1100_suspend_size, 4 * 3
@@ -211,7 +211,7 @@ __sa1100_setup:
211	mrc p15, 0, r0, c1, c0 @ get control register v4	211	mrc p15, 0, r0, c1, c0 @ get control register v4
212	bic r0, r0, r5	212	bic r0, r0, r5
213	orr r0, r0, r6	213	orr r0, r0, r6
214	mov pc, lr	214	ret lr
215	.size __sa1100_setup, . - __sa1100_setup	215	.size __sa1100_setup, . - __sa1100_setup
216		216
217	/*	217	/*