1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c45319c8f1d9..8008a0461cf5 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -38,7 +38,7 @@
 ENTRY(cpu_sa110_proc_init)
        mov     r0, #0
        mcr     p15, 0, r0, c15, c1, 2          @ Enable clock switching
-        mov     pc, lr
+        ret     lr
 /*
 * cpu_sa110_proc_fin()
@@ -50,7 +50,7 @@ ENTRY(cpu_sa110_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        mov     pc, lr
+        ret     lr
 /*
 * cpu_sa110_reset(loc)
@@ -74,7 +74,7 @@ ENTRY(cpu_sa110_reset)
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-        mov     pc, r0
+        ret     r0
 ENDPROC(cpu_sa110_reset)
        .popsection
@@ -103,7 +103,7 @@ ENTRY(cpu_sa110_do_idle)
        mov     r0, r0                          @ safety
        mov     r0, r0                          @ safety
        mcr     p15, 0, r0, c15, c1, 2          @ enable clock switching
-        mov     pc, lr
+        ret     lr
 /* ================================= CACHE ================================ */
@@ -121,7 +121,7 @@ ENTRY(cpu_sa110_dcache_clean_area)
        add     r0, r0, #DCACHELINESIZE
        subs    r1, r1, #DCACHELINESIZE
        bhi     1b
-        mov     pc, lr
+        ret     lr
 /* =============================== PageTable ============================== */
@@ -141,7 +141,7 @@ ENTRY(cpu_sa110_switch_mm)
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
        ldr     pc, [sp], #4
 #else
-        mov     pc, lr
+        ret     lr
 #endif
 /*
@@ -157,7 +157,7 @@ ENTRY(cpu_sa110_set_pte_ext)
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
-        mov     pc, lr
+        ret     lr
        .type   __sa110_setup, #function
 __sa110_setup:
@@ -173,7 +173,7 @@ __sa110_setup:
        mrc     p15, 0, r0, c1, c0              @ get control register v4
        bic     r0, r0, r5
        orr     r0, r0, r6
-        mov     pc, lr
+        ret     lr
        .size   __sa110_setup, . - __sa110_setup
        /*

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index c45319c8f1d9..8008a0461cf5 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S
@@ -38,7 +38,7 @@
38	ENTRY(cpu_sa110_proc_init)	38	ENTRY(cpu_sa110_proc_init)
39	mov r0, #0	39	mov r0, #0
40	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching	40	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
41	mov pc, lr	41	ret lr
42		42
43	/*	43	/*
44	* cpu_sa110_proc_fin()	44	* cpu_sa110_proc_fin()
@@ -50,7 +50,7 @@ ENTRY(cpu_sa110_proc_fin)
50	bic r0, r0, #0x1000 @ ...i............	50	bic r0, r0, #0x1000 @ ...i............
51	bic r0, r0, #0x000e @ ............wca.	51	bic r0, r0, #0x000e @ ............wca.
52	mcr p15, 0, r0, c1, c0, 0 @ disable caches	52	mcr p15, 0, r0, c1, c0, 0 @ disable caches
53	mov pc, lr	53	ret lr
54		54
55	/*	55	/*
56	* cpu_sa110_reset(loc)	56	* cpu_sa110_reset(loc)
@@ -74,7 +74,7 @@ ENTRY(cpu_sa110_reset)
74	bic ip, ip, #0x000f @ ............wcam	74	bic ip, ip, #0x000f @ ............wcam
75	bic ip, ip, #0x1100 @ ...i...s........	75	bic ip, ip, #0x1100 @ ...i...s........
76	mcr p15, 0, ip, c1, c0, 0 @ ctrl register	76	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77	mov pc, r0	77	ret r0
78	ENDPROC(cpu_sa110_reset)	78	ENDPROC(cpu_sa110_reset)
79	.popsection	79	.popsection
80		80
@@ -103,7 +103,7 @@ ENTRY(cpu_sa110_do_idle)
103	mov r0, r0 @ safety	103	mov r0, r0 @ safety
104	mov r0, r0 @ safety	104	mov r0, r0 @ safety
105	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching	105	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
106	mov pc, lr	106	ret lr
107		107
108	/* ================================= CACHE ================================ */	108	/* ================================= CACHE ================================ */
109		109
@@ -121,7 +121,7 @@ ENTRY(cpu_sa110_dcache_clean_area)
121	add r0, r0, #DCACHELINESIZE	121	add r0, r0, #DCACHELINESIZE
122	subs r1, r1, #DCACHELINESIZE	122	subs r1, r1, #DCACHELINESIZE
123	bhi 1b	123	bhi 1b
124	mov pc, lr	124	ret lr
125		125
126	/* =============================== PageTable ============================== */	126	/* =============================== PageTable ============================== */
127		127
@@ -141,7 +141,7 @@ ENTRY(cpu_sa110_switch_mm)
141	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs	141	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
142	ldr pc, [sp], #4	142	ldr pc, [sp], #4
143	#else	143	#else
144	mov pc, lr	144	ret lr
145	#endif	145	#endif
146		146
147	/*	147	/*
@@ -157,7 +157,7 @@ ENTRY(cpu_sa110_set_pte_ext)
157	mcr p15, 0, r0, c7, c10, 1 @ clean D entry	157	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
158	mcr p15, 0, r0, c7, c10, 4 @ drain WB	158	mcr p15, 0, r0, c7, c10, 4 @ drain WB
159	#endif	159	#endif
160	mov pc, lr	160	ret lr
161		161
162	.type __sa110_setup, #function	162	.type __sa110_setup, #function
163	__sa110_setup:	163	__sa110_setup:
@@ -173,7 +173,7 @@ __sa110_setup:
173	mrc p15, 0, r0, c1, c0 @ get control register v4	173	mrc p15, 0, r0, c1, c0 @ get control register v4
174	bic r0, r0, r5	174	bic r0, r0, r5
175	orr r0, r0, r6	175	orr r0, r0, r6
176	mov pc, lr	176	ret lr
177	.size __sa110_setup, . - __sa110_setup	177	.size __sa110_setup, . - __sa110_setup
178		178
179	/*	179	/*