1 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 9e2c89eb2115..b13150052a76 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -59,3 +59,15 @@
         .word   \ucset
 #endif
         .endm
+
+/*
+ * cache_line_size - get the cache line size from the CSIDR register
+ * (available on ARMv7+). It assumes that the CSSR register was configured
+ * to access the L1 data cache CSIDR.
+ */
+        .macro  dcache_line_size, reg, tmp
+        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+        and     \tmp, \tmp, #7                  @ cache line size encoding
+        mov     \reg, #16                       @ size offset
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm