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-rw-r--r--arch/arm/mm/proc-arm946.S43
1 files changed, 34 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 40c0449a139b..1664b6aaff79 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range)
183 mov pc, lr 183 mov pc, lr
184 184
185/* 185/*
186 * flush_kern_dcache_page(void *page) 186 * flush_kern_dcache_area(void *addr, size_t size)
187 * 187 *
188 * Ensure no D cache aliasing occurs, either with itself or 188 * Ensure no D cache aliasing occurs, either with itself or
189 * the I cache 189 * the I cache
190 * 190 *
191 * - addr - page aligned address 191 * - addr - kernel address
192 * - size - region size
192 * (same as arm926) 193 * (same as arm926)
193 */ 194 */
194ENTRY(arm946_flush_kern_dcache_page) 195ENTRY(arm946_flush_kern_dcache_area)
195 add r1, r0, #PAGE_SZ 196 add r1, r0, r1
1961: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 1971: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
197 add r0, r0, #CACHE_DLINESIZE 198 add r0, r0, #CACHE_DLINESIZE
198 cmp r0, r1 199 cmp r0, r1
@@ -214,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_page)
214 * - end - virtual end address 215 * - end - virtual end address
215 * (same as arm926) 216 * (same as arm926)
216 */ 217 */
217ENTRY(arm946_dma_inv_range) 218arm946_dma_inv_range:
218#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 219#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
219 tst r0, #CACHE_DLINESIZE - 1 220 tst r0, #CACHE_DLINESIZE - 1
220 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 221 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -239,7 +240,7 @@ ENTRY(arm946_dma_inv_range)
239 * 240 *
240 * (same as arm926) 241 * (same as arm926)
241 */ 242 */
242ENTRY(arm946_dma_clean_range) 243arm946_dma_clean_range:
243#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 244#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
244 bic r0, r0, #CACHE_DLINESIZE - 1 245 bic r0, r0, #CACHE_DLINESIZE - 1
2451: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -274,15 +275,39 @@ ENTRY(arm946_dma_flush_range)
274 mcr p15, 0, r0, c7, c10, 4 @ drain WB 275 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 mov pc, lr 276 mov pc, lr
276 277
278/*
279 * dma_map_area(start, size, dir)
280 * - start - kernel virtual start address
281 * - size - size of region
282 * - dir - DMA direction
283 */
284ENTRY(arm946_dma_map_area)
285 add r1, r1, r0
286 cmp r2, #DMA_TO_DEVICE
287 beq arm946_dma_clean_range
288 bcs arm946_dma_inv_range
289 b arm946_dma_flush_range
290ENDPROC(arm946_dma_map_area)
291
292/*
293 * dma_unmap_area(start, size, dir)
294 * - start - kernel virtual start address
295 * - size - size of region
296 * - dir - DMA direction
297 */
298ENTRY(arm946_dma_unmap_area)
299 mov pc, lr
300ENDPROC(arm946_dma_unmap_area)
301
277ENTRY(arm946_cache_fns) 302ENTRY(arm946_cache_fns)
278 .long arm946_flush_kern_cache_all 303 .long arm946_flush_kern_cache_all
279 .long arm946_flush_user_cache_all 304 .long arm946_flush_user_cache_all
280 .long arm946_flush_user_cache_range 305 .long arm946_flush_user_cache_range
281 .long arm946_coherent_kern_range 306 .long arm946_coherent_kern_range
282 .long arm946_coherent_user_range 307 .long arm946_coherent_user_range
283 .long arm946_flush_kern_dcache_page 308 .long arm946_flush_kern_dcache_area
284 .long arm946_dma_inv_range 309 .long arm946_dma_map_area
285 .long arm946_dma_clean_range 310 .long arm946_dma_unmap_area
286 .long arm946_dma_flush_range 311 .long arm946_dma_flush_range
287 312
288 313