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-rw-r--r--arch/arm/mm/proc-arm926.S43
1 files changed, 34 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 1c4848704bb3..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -214,15 +214,16 @@ ENTRY(arm926_coherent_user_range)
214 mov pc, lr 214 mov pc, lr
215 215
216/* 216/*
217 * flush_kern_dcache_page(void *page) 217 * flush_kern_dcache_area(void *addr, size_t size)
218 * 218 *
219 * Ensure no D cache aliasing occurs, either with itself or 219 * Ensure no D cache aliasing occurs, either with itself or
220 * the I cache 220 * the I cache
221 * 221 *
222 * - addr - page aligned address 222 * - addr - kernel address
223 * - size - region size
223 */ 224 */
224ENTRY(arm926_flush_kern_dcache_page) 225ENTRY(arm926_flush_kern_dcache_area)
225 add r1, r0, #PAGE_SZ 226 add r1, r0, r1
2261: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 2271: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
227 add r0, r0, #CACHE_DLINESIZE 228 add r0, r0, #CACHE_DLINESIZE
228 cmp r0, r1 229 cmp r0, r1
@@ -245,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_page)
245 * 246 *
246 * (same as v4wb) 247 * (same as v4wb)
247 */ 248 */
248ENTRY(arm926_dma_inv_range) 249arm926_dma_inv_range:
249#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
250 tst r0, #CACHE_DLINESIZE - 1 251 tst r0, #CACHE_DLINESIZE - 1
251 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -270,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
270 * 271 *
271 * (same as v4wb) 272 * (same as v4wb)
272 */ 273 */
273ENTRY(arm926_dma_clean_range) 274arm926_dma_clean_range:
274#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
275 bic r0, r0, #CACHE_DLINESIZE - 1 276 bic r0, r0, #CACHE_DLINESIZE - 1
2761: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -303,15 +304,39 @@ ENTRY(arm926_dma_flush_range)
303 mcr p15, 0, r0, c7, c10, 4 @ drain WB 304 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 mov pc, lr 305 mov pc, lr
305 306
307/*
308 * dma_map_area(start, size, dir)
309 * - start - kernel virtual start address
310 * - size - size of region
311 * - dir - DMA direction
312 */
313ENTRY(arm926_dma_map_area)
314 add r1, r1, r0
315 cmp r2, #DMA_TO_DEVICE
316 beq arm926_dma_clean_range
317 bcs arm926_dma_inv_range
318 b arm926_dma_flush_range
319ENDPROC(arm926_dma_map_area)
320
321/*
322 * dma_unmap_area(start, size, dir)
323 * - start - kernel virtual start address
324 * - size - size of region
325 * - dir - DMA direction
326 */
327ENTRY(arm926_dma_unmap_area)
328 mov pc, lr
329ENDPROC(arm926_dma_unmap_area)
330
306ENTRY(arm926_cache_fns) 331ENTRY(arm926_cache_fns)
307 .long arm926_flush_kern_cache_all 332 .long arm926_flush_kern_cache_all
308 .long arm926_flush_user_cache_all 333 .long arm926_flush_user_cache_all
309 .long arm926_flush_user_cache_range 334 .long arm926_flush_user_cache_range
310 .long arm926_coherent_kern_range 335 .long arm926_coherent_kern_range
311 .long arm926_coherent_user_range 336 .long arm926_coherent_user_range
312 .long arm926_flush_kern_dcache_page 337 .long arm926_flush_kern_dcache_area
313 .long arm926_dma_inv_range 338 .long arm926_dma_map_area
314 .long arm926_dma_clean_range 339 .long arm926_dma_unmap_area
315 .long arm926_dma_flush_range 340 .long arm926_dma_flush_range
316 341
317ENTRY(cpu_arm926_dcache_clean_area) 342ENTRY(cpu_arm926_dcache_clean_area)