1 files changed, 17 insertions, 17 deletions

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 2a758b06c6f6..0c6d5ac5a6d4 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -65,7 +65,7 @@
  * cpu_arm922_proc_init()
  */
 ENTRY(cpu_arm922_proc_init)
-        mov     pc, lr
+        ret     lr
 
 /*
  * cpu_arm922_proc_fin()
@@ -75,7 +75,7 @@ ENTRY(cpu_arm922_proc_fin)
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        mov     pc, lr
+        ret     lr
 
 /*
  * cpu_arm922_reset(loc)
@@ -99,7 +99,7 @@ ENTRY(cpu_arm922_reset)
         bic     ip, ip, #0x000f                 @ ............wcam
         bic     ip, ip, #0x1100                 @ ...i...s........
         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-        mov     pc, r0
+        ret     r0
 ENDPROC(cpu_arm922_reset)
         .popsection
 
@@ -109,7 +109,7 @@ ENDPROC(cpu_arm922_reset)
         .align  5
 ENTRY(cpu_arm922_do_idle)
         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
-        mov     pc, lr
+        ret     lr
 
 
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -122,7 +122,7 @@ ENTRY(cpu_arm922_do_idle)
 ENTRY(arm922_flush_icache_all)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mov     pc, lr
+        ret     lr
 ENDPROC(arm922_flush_icache_all)
 
 /*
@@ -153,7 +153,7 @@ __flush_whole_cache:
         tst     r2, #VM_EXEC
         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      flush_user_cache_range(start, end, flags)
@@ -179,7 +179,7 @@ ENTRY(arm922_flush_user_cache_range)
         blo     1b
         tst     r2, #VM_EXEC
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      coherent_kern_range(start, end)
@@ -213,7 +213,7 @@ ENTRY(arm922_coherent_user_range)
         blo     1b
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     r0, #0
-        mov     pc, lr
+        ret     lr
 
 /*
  *      flush_kern_dcache_area(void *addr, size_t size)
@@ -233,7 +233,7 @@ ENTRY(arm922_flush_kern_dcache_area)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      dma_inv_range(start, end)
@@ -259,7 +259,7 @@ arm922_dma_inv_range:
         cmp     r0, r1
         blo     1b
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      dma_clean_range(start, end)
@@ -278,7 +278,7 @@ arm922_dma_clean_range:
         cmp     r0, r1
         blo     1b
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      dma_flush_range(start, end)
@@ -295,7 +295,7 @@ ENTRY(arm922_dma_flush_range)
         cmp     r0, r1
         blo     1b
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-        mov     pc, lr
+        ret     lr
 
 /*
  *      dma_map_area(start, size, dir)
@@ -318,7 +318,7 @@ ENDPROC(arm922_dma_map_area)
  *      - dir   - DMA direction
  */
 ENTRY(arm922_dma_unmap_area)
-        mov     pc, lr
+        ret     lr
 ENDPROC(arm922_dma_unmap_area)
 
         .globl  arm922_flush_kern_cache_louis
@@ -336,7 +336,7 @@ ENTRY(cpu_arm922_dcache_clean_area)
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
 #endif
-        mov     pc, lr
+        ret     lr
 
 /* =============================== PageTable ============================== */
 
@@ -371,7 +371,7 @@ ENTRY(cpu_arm922_switch_mm)
         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 #endif
-        mov     pc, lr
+        ret     lr
 
 /*
  * cpu_arm922_set_pte_ext(ptep, pte, ext)
@@ -386,7 +386,7 @@ ENTRY(cpu_arm922_set_pte_ext)
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif /* CONFIG_MMU */
-        mov     pc, lr
+        ret     lr
 
         .type   __arm922_setup, #function
 __arm922_setup:
@@ -401,7 +401,7 @@ __arm922_setup:
         mrc     p15, 0, r0, c1, c0              @ get control register v4
         bic     r0, r0, r5
         orr     r0, r0, r6
-        mov     pc, lr
+        ret     lr
         .size   __arm922_setup, . - __arm922_setup
 
         /*