diff options
Diffstat (limited to 'arch/arm/mm/proc-arm1020.S')
-rw-r--r-- | arch/arm/mm/proc-arm1020.S | 43 |
1 files changed, 34 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index d9fb4b98c49f..72507c630ceb 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S | |||
@@ -231,17 +231,18 @@ ENTRY(arm1020_coherent_user_range) | |||
231 | mov pc, lr | 231 | mov pc, lr |
232 | 232 | ||
233 | /* | 233 | /* |
234 | * flush_kern_dcache_page(void *page) | 234 | * flush_kern_dcache_area(void *addr, size_t size) |
235 | * | 235 | * |
236 | * Ensure no D cache aliasing occurs, either with itself or | 236 | * Ensure no D cache aliasing occurs, either with itself or |
237 | * the I cache | 237 | * the I cache |
238 | * | 238 | * |
239 | * - page - page aligned address | 239 | * - addr - kernel address |
240 | * - size - region size | ||
240 | */ | 241 | */ |
241 | ENTRY(arm1020_flush_kern_dcache_page) | 242 | ENTRY(arm1020_flush_kern_dcache_area) |
242 | mov ip, #0 | 243 | mov ip, #0 |
243 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 244 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
244 | add r1, r0, #PAGE_SZ | 245 | add r1, r0, r1 |
245 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | 246 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
246 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 247 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
247 | add r0, r0, #CACHE_DLINESIZE | 248 | add r0, r0, #CACHE_DLINESIZE |
@@ -264,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_page) | |||
264 | * | 265 | * |
265 | * (same as v4wb) | 266 | * (same as v4wb) |
266 | */ | 267 | */ |
267 | ENTRY(arm1020_dma_inv_range) | 268 | arm1020_dma_inv_range: |
268 | mov ip, #0 | 269 | mov ip, #0 |
269 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 270 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
270 | tst r0, #CACHE_DLINESIZE - 1 | 271 | tst r0, #CACHE_DLINESIZE - 1 |
@@ -294,7 +295,7 @@ ENTRY(arm1020_dma_inv_range) | |||
294 | * | 295 | * |
295 | * (same as v4wb) | 296 | * (same as v4wb) |
296 | */ | 297 | */ |
297 | ENTRY(arm1020_dma_clean_range) | 298 | arm1020_dma_clean_range: |
298 | mov ip, #0 | 299 | mov ip, #0 |
299 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 300 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
300 | bic r0, r0, #CACHE_DLINESIZE - 1 | 301 | bic r0, r0, #CACHE_DLINESIZE - 1 |
@@ -329,15 +330,39 @@ ENTRY(arm1020_dma_flush_range) | |||
329 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 330 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
330 | mov pc, lr | 331 | mov pc, lr |
331 | 332 | ||
333 | /* | ||
334 | * dma_map_area(start, size, dir) | ||
335 | * - start - kernel virtual start address | ||
336 | * - size - size of region | ||
337 | * - dir - DMA direction | ||
338 | */ | ||
339 | ENTRY(arm1020_dma_map_area) | ||
340 | add r1, r1, r0 | ||
341 | cmp r2, #DMA_TO_DEVICE | ||
342 | beq arm1020_dma_clean_range | ||
343 | bcs arm1020_dma_inv_range | ||
344 | b arm1020_dma_flush_range | ||
345 | ENDPROC(arm1020_dma_map_area) | ||
346 | |||
347 | /* | ||
348 | * dma_unmap_area(start, size, dir) | ||
349 | * - start - kernel virtual start address | ||
350 | * - size - size of region | ||
351 | * - dir - DMA direction | ||
352 | */ | ||
353 | ENTRY(arm1020_dma_unmap_area) | ||
354 | mov pc, lr | ||
355 | ENDPROC(arm1020_dma_unmap_area) | ||
356 | |||
332 | ENTRY(arm1020_cache_fns) | 357 | ENTRY(arm1020_cache_fns) |
333 | .long arm1020_flush_kern_cache_all | 358 | .long arm1020_flush_kern_cache_all |
334 | .long arm1020_flush_user_cache_all | 359 | .long arm1020_flush_user_cache_all |
335 | .long arm1020_flush_user_cache_range | 360 | .long arm1020_flush_user_cache_range |
336 | .long arm1020_coherent_kern_range | 361 | .long arm1020_coherent_kern_range |
337 | .long arm1020_coherent_user_range | 362 | .long arm1020_coherent_user_range |
338 | .long arm1020_flush_kern_dcache_page | 363 | .long arm1020_flush_kern_dcache_area |
339 | .long arm1020_dma_inv_range | 364 | .long arm1020_dma_map_area |
340 | .long arm1020_dma_clean_range | 365 | .long arm1020_dma_unmap_area |
341 | .long arm1020_dma_flush_range | 366 | .long arm1020_dma_flush_range |
342 | 367 | ||
343 | .align 5 | 368 | .align 5 |