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-rw-r--r--arch/arm/mm/copypage-xscale.c47
1 files changed, 26 insertions, 21 deletions
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index bad49331bbf9..d18f2397ee2d 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -15,8 +15,8 @@
15 */ 15 */
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/highmem.h>
18 19
19#include <asm/page.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
@@ -35,7 +35,7 @@
35static DEFINE_SPINLOCK(minicache_lock); 35static DEFINE_SPINLOCK(minicache_lock);
36 36
37/* 37/*
38 * XScale mini-dcache optimised copy_user_page 38 * XScale mini-dcache optimised copy_user_highpage
39 * 39 *
40 * We flush the destination cache lines just before we write the data into the 40 * We flush the destination cache lines just before we write the data into the
41 * corresponding address. Since the Dcache is read-allocate, this removes the 41 * corresponding address. Since the Dcache is read-allocate, this removes the
@@ -90,48 +90,53 @@ mc_copy_user_page(void *from, void *to)
90 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1)); 90 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
91} 91}
92 92
93void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) 93void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
94 unsigned long vaddr)
94{ 95{
95 struct page *page = virt_to_page(kfrom); 96 void *kto = kmap_atomic(to, KM_USER1);
96 97
97 if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) 98 if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
98 __flush_dcache_page(page_mapping(page), page); 99 __flush_dcache_page(page_mapping(from), from);
99 100
100 spin_lock(&minicache_lock); 101 spin_lock(&minicache_lock);
101 102
102 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); 103 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
103 flush_tlb_kernel_page(COPYPAGE_MINICACHE); 104 flush_tlb_kernel_page(COPYPAGE_MINICACHE);
104 105
105 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); 106 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
106 107
107 spin_unlock(&minicache_lock); 108 spin_unlock(&minicache_lock);
109
110 kunmap_atomic(kto, KM_USER1);
108} 111}
109 112
110/* 113/*
111 * XScale optimised clear_user_page 114 * XScale optimised clear_user_page
112 */ 115 */
113void __attribute__((naked)) 116void
114xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr) 117xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
115{ 118{
119 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
116 asm volatile( 120 asm volatile(
117 "mov r1, %0 \n\ 121 "mov r1, %2 \n\
118 mov r2, #0 \n\ 122 mov r2, #0 \n\
119 mov r3, #0 \n\ 123 mov r3, #0 \n\
1201: mov ip, r0 \n\ 1241: mov ip, %0 \n\
121 strd r2, [r0], #8 \n\ 125 strd r2, [%0], #8 \n\
122 strd r2, [r0], #8 \n\ 126 strd r2, [%0], #8 \n\
123 strd r2, [r0], #8 \n\ 127 strd r2, [%0], #8 \n\
124 strd r2, [r0], #8 \n\ 128 strd r2, [%0], #8 \n\
125 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ 129 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
126 subs r1, r1, #1 \n\ 130 subs r1, r1, #1 \n\
127 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ 131 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
128 bne 1b \n\ 132 bne 1b"
129 mov pc, lr" 133 : "=r" (ptr)
130 : 134 : "0" (kaddr), "I" (PAGE_SIZE / 32)
131 : "I" (PAGE_SIZE / 32)); 135 : "r1", "r2", "r3", "ip");
136 kunmap_atomic(kaddr, KM_USER0);
132} 137}
133 138
134struct cpu_user_fns xscale_mc_user_fns __initdata = { 139struct cpu_user_fns xscale_mc_user_fns __initdata = {
135 .cpu_clear_user_page = xscale_mc_clear_user_page, 140 .cpu_clear_user_highpage = xscale_mc_clear_user_highpage,
136 .cpu_copy_user_page = xscale_mc_copy_user_page, 141 .cpu_copy_user_highpage = xscale_mc_copy_user_highpage,
137}; 142};