1 files changed, 6 insertions, 6 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 778bcf88ee79..615c99e38ba1 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
        bgt     2b
        cmp     r2, #0
        bgt     1b
-       dsb
+       dsb     st
        isb
        mov     pc, lr
 ENDPROC(v7_invalidate_l1)
@@ -166,7 +166,7 @@ skip:
 finished:
         mov     r10, #0                         @ swith back to cache level 0
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
-        dsb
+        dsb     st
         isb
         mov     pc, lr
 ENDPROC(v7_flush_dcache_all)
@@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
         add     r0, r0, r2
         cmp     r0, r1
         blo     1b
-        dsb
+        dsb     st
         mov     pc, lr
 ENDPROC(v7_flush_kern_dcache_area)
 
@@ -368,7 +368,7 @@ v7_dma_inv_range:
         add     r0, r0, r2
         cmp     r0, r1
         blo     1b
-        dsb
+        dsb     st
         mov     pc, lr
 ENDPROC(v7_dma_inv_range)
 
@@ -390,7 +390,7 @@ v7_dma_clean_range:
         add     r0, r0, r2
         cmp     r0, r1
         blo     1b
-        dsb
+        dsb     st
         mov     pc, lr
 ENDPROC(v7_dma_clean_range)
 
@@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
         add     r0, r0, r2
         cmp     r0, r1
         blo     1b
-        dsb
+        dsb     st
         mov     pc, lr
 ENDPROC(v7_dma_flush_range)