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-rw-r--r--arch/arm/mm/cache-v4wt.S51
1 files changed, 32 insertions, 19 deletions
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index c54fa2cc40e6..45c70312f43b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range)
117 mov pc, lr 117 mov pc, lr
118 118
119/* 119/*
120 * flush_kern_dcache_page(void *page) 120 * flush_kern_dcache_area(void *addr, size_t size)
121 * 121 *
122 * Ensure no D cache aliasing occurs, either with itself or 122 * Ensure no D cache aliasing occurs, either with itself or
123 * the I cache 123 * the I cache
124 * 124 *
125 * - addr - page aligned address 125 * - addr - kernel address
126 * - size - region size
126 */ 127 */
127ENTRY(v4wt_flush_kern_dcache_page) 128ENTRY(v4wt_flush_kern_dcache_area)
128 mov r2, #0 129 mov r2, #0
129 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
130 add r1, r0, #PAGE_SZ 131 add r1, r0, r1
131 /* fallthrough */ 132 /* fallthrough */
132 133
133/* 134/*
@@ -141,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_page)
141 * - start - virtual start address 142 * - start - virtual start address
142 * - end - virtual end address 143 * - end - virtual end address
143 */ 144 */
144ENTRY(v4wt_dma_inv_range) 145v4wt_dma_inv_range:
145 bic r0, r0, #CACHE_DLINESIZE - 1 146 bic r0, r0, #CACHE_DLINESIZE - 1
1461: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 1471: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
147 add r0, r0, #CACHE_DLINESIZE 148 add r0, r0, #CACHE_DLINESIZE
148 cmp r0, r1 149 cmp r0, r1
149 blo 1b 150 blo 1b
150 /* FALLTHROUGH */
151
152/*
153 * dma_clean_range(start, end)
154 *
155 * Clean the specified virtual address range.
156 *
157 * - start - virtual start address
158 * - end - virtual end address
159 */
160ENTRY(v4wt_dma_clean_range)
161 mov pc, lr 151 mov pc, lr
162 152
163/* 153/*
@@ -171,6 +161,29 @@ ENTRY(v4wt_dma_clean_range)
171 .globl v4wt_dma_flush_range 161 .globl v4wt_dma_flush_range
172 .equ v4wt_dma_flush_range, v4wt_dma_inv_range 162 .equ v4wt_dma_flush_range, v4wt_dma_inv_range
173 163
164/*
165 * dma_unmap_area(start, size, dir)
166 * - start - kernel virtual start address
167 * - size - size of region
168 * - dir - DMA direction
169 */
170ENTRY(v4wt_dma_unmap_area)
171 add r1, r1, r0
172 teq r2, #DMA_TO_DEVICE
173 bne v4wt_dma_inv_range
174 /* FALLTHROUGH */
175
176/*
177 * dma_map_area(start, size, dir)
178 * - start - kernel virtual start address
179 * - size - size of region
180 * - dir - DMA direction
181 */
182ENTRY(v4wt_dma_map_area)
183 mov pc, lr
184ENDPROC(v4wt_dma_unmap_area)
185ENDPROC(v4wt_dma_map_area)
186
174 __INITDATA 187 __INITDATA
175 188
176 .type v4wt_cache_fns, #object 189 .type v4wt_cache_fns, #object
@@ -180,8 +193,8 @@ ENTRY(v4wt_cache_fns)
180 .long v4wt_flush_user_cache_range 193 .long v4wt_flush_user_cache_range
181 .long v4wt_coherent_kern_range 194 .long v4wt_coherent_kern_range
182 .long v4wt_coherent_user_range 195 .long v4wt_coherent_user_range
183 .long v4wt_flush_kern_dcache_page 196 .long v4wt_flush_kern_dcache_area
184 .long v4wt_dma_inv_range 197 .long v4wt_dma_map_area
185 .long v4wt_dma_clean_range 198 .long v4wt_dma_unmap_area
186 .long v4wt_dma_flush_range 199 .long v4wt_dma_flush_range
187 .size v4wt_cache_fns, . - v4wt_cache_fns 200 .size v4wt_cache_fns, . - v4wt_cache_fns