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-rw-r--r--arch/arm/mm/cache-v4.S52
1 files changed, 25 insertions, 27 deletions
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 3668611cb400..4810f7e3e813 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -82,28 +82,15 @@ ENTRY(v4_coherent_user_range)
82 mov pc, lr 82 mov pc, lr
83 83
84/* 84/*
85 * flush_kern_dcache_page(void *page) 85 * flush_kern_dcache_area(void *addr, size_t size)
86 * 86 *
87 * Ensure no D cache aliasing occurs, either with itself or 87 * Ensure no D cache aliasing occurs, either with itself or
88 * the I cache 88 * the I cache
89 * 89 *
90 * - addr - page aligned address 90 * - addr - kernel address
91 * - size - region size
91 */ 92 */
92ENTRY(v4_flush_kern_dcache_page) 93ENTRY(v4_flush_kern_dcache_area)
93 /* FALLTHROUGH */
94
95/*
96 * dma_inv_range(start, end)
97 *
98 * Invalidate (discard) the specified virtual address range.
99 * May not write back any entries. If 'start' or 'end'
100 * are not cache line aligned, those lines must be written
101 * back.
102 *
103 * - start - virtual start address
104 * - end - virtual end address
105 */
106ENTRY(v4_dma_inv_range)
107 /* FALLTHROUGH */ 94 /* FALLTHROUGH */
108 95
109/* 96/*
@@ -119,18 +106,29 @@ ENTRY(v4_dma_flush_range)
119 mov r0, #0 106 mov r0, #0
120 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 107 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
121#endif 108#endif
109 mov pc, lr
110
111/*
112 * dma_unmap_area(start, size, dir)
113 * - start - kernel virtual start address
114 * - size - size of region
115 * - dir - DMA direction
116 */
117ENTRY(v4_dma_unmap_area)
118 teq r2, #DMA_TO_DEVICE
119 bne v4_dma_flush_range
122 /* FALLTHROUGH */ 120 /* FALLTHROUGH */
123 121
124/* 122/*
125 * dma_clean_range(start, end) 123 * dma_map_area(start, size, dir)
126 * 124 * - start - kernel virtual start address
127 * Clean (write back) the specified virtual address range. 125 * - size - size of region
128 * 126 * - dir - DMA direction
129 * - start - virtual start address
130 * - end - virtual end address
131 */ 127 */
132ENTRY(v4_dma_clean_range) 128ENTRY(v4_dma_map_area)
133 mov pc, lr 129 mov pc, lr
130ENDPROC(v4_dma_unmap_area)
131ENDPROC(v4_dma_map_area)
134 132
135 __INITDATA 133 __INITDATA
136 134
@@ -141,8 +139,8 @@ ENTRY(v4_cache_fns)
141 .long v4_flush_user_cache_range 139 .long v4_flush_user_cache_range
142 .long v4_coherent_kern_range 140 .long v4_coherent_kern_range
143 .long v4_coherent_user_range 141 .long v4_coherent_user_range
144 .long v4_flush_kern_dcache_page 142 .long v4_flush_kern_dcache_area
145 .long v4_dma_inv_range 143 .long v4_dma_map_area
146 .long v4_dma_clean_range 144 .long v4_dma_unmap_area
147 .long v4_dma_flush_range 145 .long v4_dma_flush_range
148 .size v4_cache_fns, . - v4_cache_fns 146 .size v4_cache_fns, . - v4_cache_fns