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-rw-r--r--arch/arm/mm/cache-v3.S9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 8a4abebc478a..2a482731ea36 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -72,14 +72,15 @@ ENTRY(v3_coherent_user_range)
72 mov pc, lr 72 mov pc, lr
73 73
74/* 74/*
75 * flush_kern_dcache_page(void *page) 75 * flush_kern_dcache_area(void *page, size_t size)
76 * 76 *
77 * Ensure no D cache aliasing occurs, either with itself or 77 * Ensure no D cache aliasing occurs, either with itself or
78 * the I cache 78 * the I cache
79 * 79 *
80 * - addr - page aligned address 80 * - addr - kernel address
81 * - size - region size
81 */ 82 */
82ENTRY(v3_flush_kern_dcache_page) 83ENTRY(v3_flush_kern_dcache_area)
83 /* FALLTHROUGH */ 84 /* FALLTHROUGH */
84 85
85/* 86/*
@@ -129,7 +130,7 @@ ENTRY(v3_cache_fns)
129 .long v3_flush_user_cache_range 130 .long v3_flush_user_cache_range
130 .long v3_coherent_kern_range 131 .long v3_coherent_kern_range
131 .long v3_coherent_user_range 132 .long v3_coherent_user_range
132 .long v3_flush_kern_dcache_page 133 .long v3_flush_kern_dcache_area
133 .long v3_dma_inv_range 134 .long v3_dma_inv_range
134 .long v3_dma_clean_range 135 .long v3_dma_clean_range
135 .long v3_dma_flush_range 136 .long v3_dma_flush_range