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-rw-r--r--arch/arm/mm/cache-v3.S52
1 files changed, 25 insertions, 27 deletions
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 8a4abebc478a..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -72,28 +72,15 @@ ENTRY(v3_coherent_user_range)
72 mov pc, lr 72 mov pc, lr
73 73
74/* 74/*
75 * flush_kern_dcache_page(void *page) 75 * flush_kern_dcache_area(void *page, size_t size)
76 * 76 *
77 * Ensure no D cache aliasing occurs, either with itself or 77 * Ensure no D cache aliasing occurs, either with itself or
78 * the I cache 78 * the I cache
79 * 79 *
80 * - addr - page aligned address 80 * - addr - kernel address
81 * - size - region size
81 */ 82 */
82ENTRY(v3_flush_kern_dcache_page) 83ENTRY(v3_flush_kern_dcache_area)
83 /* FALLTHROUGH */
84
85/*
86 * dma_inv_range(start, end)
87 *
88 * Invalidate (discard) the specified virtual address range.
89 * May not write back any entries. If 'start' or 'end'
90 * are not cache line aligned, those lines must be written
91 * back.
92 *
93 * - start - virtual start address
94 * - end - virtual end address
95 */
96ENTRY(v3_dma_inv_range)
97 /* FALLTHROUGH */ 84 /* FALLTHROUGH */
98 85
99/* 86/*
@@ -107,18 +94,29 @@ ENTRY(v3_dma_inv_range)
107ENTRY(v3_dma_flush_range) 94ENTRY(v3_dma_flush_range)
108 mov r0, #0 95 mov r0, #0
109 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache 96 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
97 mov pc, lr
98
99/*
100 * dma_unmap_area(start, size, dir)
101 * - start - kernel virtual start address
102 * - size - size of region
103 * - dir - DMA direction
104 */
105ENTRY(v3_dma_unmap_area)
106 teq r2, #DMA_TO_DEVICE
107 bne v3_dma_flush_range
110 /* FALLTHROUGH */ 108 /* FALLTHROUGH */
111 109
112/* 110/*
113 * dma_clean_range(start, end) 111 * dma_map_area(start, size, dir)
114 * 112 * - start - kernel virtual start address
115 * Clean (write back) the specified virtual address range. 113 * - size - size of region
116 * 114 * - dir - DMA direction
117 * - start - virtual start address
118 * - end - virtual end address
119 */ 115 */
120ENTRY(v3_dma_clean_range) 116ENTRY(v3_dma_map_area)
121 mov pc, lr 117 mov pc, lr
118ENDPROC(v3_dma_unmap_area)
119ENDPROC(v3_dma_map_area)
122 120
123 __INITDATA 121 __INITDATA
124 122
@@ -129,8 +127,8 @@ ENTRY(v3_cache_fns)
129 .long v3_flush_user_cache_range 127 .long v3_flush_user_cache_range
130 .long v3_coherent_kern_range 128 .long v3_coherent_kern_range
131 .long v3_coherent_user_range 129 .long v3_coherent_user_range
132 .long v3_flush_kern_dcache_page 130 .long v3_flush_kern_dcache_area
133 .long v3_dma_inv_range 131 .long v3_dma_map_area
134 .long v3_dma_clean_range 132 .long v3_dma_unmap_area
135 .long v3_dma_flush_range 133 .long v3_dma_flush_range
136 .size v3_cache_fns, . - v3_cache_fns 134 .size v3_cache_fns, . - v3_cache_fns