1 files changed, 1 insertions, 28 deletions

diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1be0f4e5e6eb..b273739e6359 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -33,7 +33,7 @@
  * outer cache operations into the kernel image if the kernel has been
  * configured to support a pre-v7 CPU.
  */
-#if __LINUX_ARM_ARCH__ < 7
+#ifdef CONFIG_CPU_32v5
 /*
  * Low-level cache maintenance operations.
  */
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
         }
 #endif
 
-#ifdef CONFIG_CPU_32v6
-        /*
-         * Check whether this CPU lacks support for the v7 hierarchical
-         * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
-         * register indicates no support for the v7 hierarchical cache
-         * ops.)
-         */
-        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
-                /*
-                 * When Tauros2 is used in an ARMv6 system, the L2
-                 * enable bit is in the ARMv6 ARM-mandated position
-                 * (bit [26] of the System Control Register).
-                 */
-                if (!(get_cr() & 0x04000000)) {
-                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
-                        adjust_cr(0x04000000, 0x04000000);
-                }
-
-                mode = "ARMv6";
-                outer_cache.inv_range = tauros2_inv_range;
-                outer_cache.clean_range = tauros2_clean_range;
-                outer_cache.flush_range = tauros2_flush_range;
-                outer_cache.disable = tauros2_disable;
-                outer_cache.resume = tauros2_resume;
-        }
-#endif
-
 #ifdef CONFIG_CPU_32v7
         /*
          * Check whether this CPU has support for the v7 hierarchical