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-rw-r--r--arch/arm/mm/abort-lv4t.S7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index db743e510214..9fb7b0e25ea1 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -19,11 +19,16 @@
19 */ 19 */
20ENTRY(v4t_late_abort) 20ENTRY(v4t_late_abort)
21 tst r3, #PSR_T_BIT @ check for thumb mode 21 tst r3, #PSR_T_BIT @ check for thumb mode
22#ifdef CONFIG_CPU_CP15_MMU
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26#else
27 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
28 mov r1, #0
29#endif
24 bne .data_thumb_abort 30 bne .data_thumb_abort
25 ldr r8, [r2] @ read arm instruction 31 ldr r8, [r2] @ read arm instruction
26 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
27 tst r8, #1 << 20 @ L = 1 -> write? 32 tst r8, #1 << 20 @ L = 1 -> write?
28 orreq r1, r1, #1 << 11 @ yes. 33 orreq r1, r1, #1 << 11 @ yes.
29 and r7, r8, #15 << 24 34 and r7, r8, #15 << 24