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-rw-r--r--arch/arm/mm/abort-ev5tj.S25
1 files changed, 10 insertions, 15 deletions
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d601c8b..4006b7a61264 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v5tj_early_abort 5 * Function: v5tj_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r3 = saved SPSR 8 * : r4 = aborted context pc
9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -23,13 +20,11 @@ ENTRY(v5tj_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 22 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #PSR_J_BIT @ Java? 23 tst r5, #PSR_J_BIT @ Java?
27 movne pc, lr 24 bne do_DataAbort
28 do_thumb_abort 25 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
29 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r4] @ read aborted ARM instruction
30 do_ldrd_abort 27 do_ldrd_abort tmp=ip, insn=r3
31 tst r3, #1 << 20 @ L = 0 -> write 28 tst r3, #1 << 20 @ L = 0 -> write
32 orreq r1, r1, #1 << 11 @ yes. 29 orreq r1, r1, #1 << 11 @ yes.
33 mov pc, lr 30 b do_DataAbort
34
35