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-rw-r--r--arch/arm/mach-w90x900/cpu.c212
1 files changed, 212 insertions, 0 deletions
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
new file mode 100644
index 000000000000..921cef991bf0
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+++ b/arch/arm/mach-w90x900/cpu.c
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1/*
2 * linux/arch/arm/mach-w90x900/cpu.c
3 *
4 * Copyright (c) 2009 Nuvoton corporation.
5 *
6 * Wan ZongShun <mcuos.com@gmail.com>
7 *
8 * NUC900 series cpu common support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation;version 2 of the License.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <linux/serial_8250.h>
25#include <linux/delay.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30#include <asm/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/regs-serial.h>
34#include <mach/regs-clock.h>
35#include <mach/regs-ebi.h>
36
37#include "cpu.h"
38#include "clock.h"
39
40/* Initial IO mappings */
41
42static struct map_desc nuc900_iodesc[] __initdata = {
43 IODESC_ENT(IRQ),
44 IODESC_ENT(GCR),
45 IODESC_ENT(UART),
46 IODESC_ENT(TIMER),
47 IODESC_ENT(EBI),
48};
49
50/* Initial clock declarations. */
51static DEFINE_CLK(lcd, 0);
52static DEFINE_CLK(audio, 1);
53static DEFINE_CLK(fmi, 4);
54static DEFINE_SUBCLK(ms, 0);
55static DEFINE_SUBCLK(sd, 1);
56static DEFINE_CLK(dmac, 5);
57static DEFINE_CLK(atapi, 6);
58static DEFINE_CLK(emc, 7);
59static DEFINE_SUBCLK(rmii, 2);
60static DEFINE_CLK(usbd, 8);
61static DEFINE_CLK(usbh, 9);
62static DEFINE_CLK(g2d, 10);;
63static DEFINE_CLK(pwm, 18);
64static DEFINE_CLK(ps2, 24);
65static DEFINE_CLK(kpi, 25);
66static DEFINE_CLK(wdt, 26);
67static DEFINE_CLK(gdma, 27);
68static DEFINE_CLK(adc, 28);
69static DEFINE_CLK(usi, 29);
70static DEFINE_CLK(ext, 0);
71
72static struct clk_lookup nuc900_clkregs[] = {
73 DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
74 DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL),
75 DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
76 DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
77 DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
78 DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
79 DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
80 DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
81 DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
82 DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
83 DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
84 DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
85 DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
86 DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
87 DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
88 DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
89 DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
90 DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
91 DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
92 DEF_CLKLOOK(&clk_ext, NULL, "ext"),
93};
94
95/* Initial serial platform data */
96
97struct plat_serial8250_port nuc900_uart_data[] = {
98 NUC900_8250PORT(UART0),
99};
100
101struct platform_device nuc900_serial_device = {
102 .name = "serial8250",
103 .id = PLAT8250_DEV_PLATFORM,
104 .dev = {
105 .platform_data = nuc900_uart_data,
106 },
107};
108
109/*Set NUC900 series cpu frequence*/
110static int __init nuc900_set_clkval(unsigned int cpufreq)
111{
112 unsigned int pllclk, ahbclk, apbclk, val;
113
114 pllclk = 0;
115 ahbclk = 0;
116 apbclk = 0;
117
118 switch (cpufreq) {
119 case 66:
120 pllclk = PLL_66MHZ;
121 ahbclk = AHB_CPUCLK_1_1;
122 apbclk = APB_AHB_1_2;
123 break;
124
125 case 100:
126 pllclk = PLL_100MHZ;
127 ahbclk = AHB_CPUCLK_1_1;
128 apbclk = APB_AHB_1_2;
129 break;
130
131 case 120:
132 pllclk = PLL_120MHZ;
133 ahbclk = AHB_CPUCLK_1_2;
134 apbclk = APB_AHB_1_2;
135 break;
136
137 case 166:
138 pllclk = PLL_166MHZ;
139 ahbclk = AHB_CPUCLK_1_2;
140 apbclk = APB_AHB_1_2;
141 break;
142
143 case 200:
144 pllclk = PLL_200MHZ;
145 ahbclk = AHB_CPUCLK_1_2;
146 apbclk = APB_AHB_1_2;
147 break;
148 }
149
150 __raw_writel(pllclk, REG_PLLCON0);
151
152 val = __raw_readl(REG_CLKDIV);
153 val &= ~(0x03 << 24 | 0x03 << 26);
154 val |= (ahbclk << 24 | apbclk << 26);
155 __raw_writel(val, REG_CLKDIV);
156
157 return 0;
158}
159static int __init nuc900_set_cpufreq(char *str)
160{
161 unsigned long cpufreq, val;
162
163 if (!*str)
164 return 0;
165
166 strict_strtoul(str, 0, &cpufreq);
167
168 nuc900_clock_source(NULL, "ext");
169
170 nuc900_set_clkval(cpufreq);
171
172 mdelay(1);
173
174 val = __raw_readl(REG_CKSKEW);
175 val &= ~0xff;
176 val |= DEFAULTSKEW;
177 __raw_writel(val, REG_CKSKEW);
178
179 nuc900_clock_source(NULL, "pll0");
180
181 return 1;
182}
183
184__setup("cpufreq=", nuc900_set_cpufreq);
185
186/*Init NUC900 evb io*/
187
188void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
189{
190 unsigned long idcode = 0x0;
191
192 iotable_init(mach_desc, mach_size);
193 iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
194
195 idcode = __raw_readl(NUC900PDID);
196 if (idcode == NUC910_CPUID)
197 printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
198 else if (idcode == NUC920_CPUID)
199 printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
200 else if (idcode == NUC950_CPUID)
201 printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
202 else if (idcode == NUC960_CPUID)
203 printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
204}
205
206/*Init NUC900 clock*/
207
208void __init nuc900_init_clocks(void)
209{
210 clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
211}
212
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