1 files changed, 18 insertions, 10 deletions

diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6c4ffb6c5ad8..204038ef3795 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -45,6 +45,23 @@ static void __init ct_ca9x4_map_io(void)
         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
+static void __init ca9x4_l2_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
+
+        if (l2x0_base) {
+                /* set RAM latencies to 1 cycle for this core tile. */
+                writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
+                writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
+
+                l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
+        } else {
+                pr_err("L2C: unable to map L2 cache controller\n");
+        }
+#endif
+}
+
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
 
@@ -63,6 +80,7 @@ static void __init ct_ca9x4_init_irq(void)
         gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
                  ioremap(A9_MPCORE_GIC_CPU, SZ_256));
         ca9x4_twd_init();
+        ca9x4_l2_init();
 }
 
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -141,16 +159,6 @@ static void __init ct_ca9x4_init(void)
 {
         int i;
 
-#ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
-
-        /* set RAM latencies to 1 cycle for this core tile. */
-        writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
-        writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
-
-        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
-#endif
-
         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);