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-rw-r--r--arch/arm/mach-versatile/core.c70
-rw-r--r--arch/arm/mach-versatile/core.h20
-rw-r--r--arch/arm/mach-versatile/include/mach/system.h33
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c18
4 files changed, 49 insertions, 92 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b9303f3b..4f352e45be0a 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -582,58 +582,58 @@ static struct pl022_ssp_controller ssp0_plat_data = {
582 .num_chipselect = 1, 582 .num_chipselect = 1,
583}; 583};
584 584
585#define AACI_IRQ { IRQ_AACI, NO_IRQ } 585#define AACI_IRQ { IRQ_AACI }
586#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } 586#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
587#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } 587#define KMI0_IRQ { IRQ_SIC_KMI0 }
588#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } 588#define KMI1_IRQ { IRQ_SIC_KMI1 }
589 589
590/* 590/*
591 * These devices are connected directly to the multi-layer AHB switch 591 * These devices are connected directly to the multi-layer AHB switch
592 */ 592 */
593#define SMC_IRQ { NO_IRQ, NO_IRQ } 593#define SMC_IRQ { }
594#define MPMC_IRQ { NO_IRQ, NO_IRQ } 594#define MPMC_IRQ { }
595#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } 595#define CLCD_IRQ { IRQ_CLCDINT }
596#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } 596#define DMAC_IRQ { IRQ_DMAINT }
597 597
598/* 598/*
599 * These devices are connected via the core APB bridge 599 * These devices are connected via the core APB bridge
600 */ 600 */
601#define SCTL_IRQ { NO_IRQ, NO_IRQ } 601#define SCTL_IRQ { }
602#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } 602#define WATCHDOG_IRQ { IRQ_WDOGINT }
603#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } 603#define GPIO0_IRQ { IRQ_GPIOINT0 }
604#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } 604#define GPIO1_IRQ { IRQ_GPIOINT1 }
605#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } 605#define RTC_IRQ { IRQ_RTCINT }
606 606
607/* 607/*
608 * These devices are connected via the DMA APB bridge 608 * These devices are connected via the DMA APB bridge
609 */ 609 */
610#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } 610#define SCI_IRQ { IRQ_SCIINT }
611#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } 611#define UART0_IRQ { IRQ_UARTINT0 }
612#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } 612#define UART1_IRQ { IRQ_UARTINT1 }
613#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } 613#define UART2_IRQ { IRQ_UARTINT2 }
614#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } 614#define SSP_IRQ { IRQ_SSPINT }
615 615
616/* FPGA Primecells */ 616/* FPGA Primecells */
617AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 617APB_DEVICE(aaci, "fpga:04", AACI, NULL);
618AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data); 618APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
619AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); 619APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
620AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); 620APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
621 621
622/* DevChip Primecells */ 622/* DevChip Primecells */
623AMBA_DEVICE(smc, "dev:00", SMC, NULL); 623AHB_DEVICE(smc, "dev:00", SMC, NULL);
624AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL); 624AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
625AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); 625AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
626AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); 626AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
627AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); 627APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
628AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); 628APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
629AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); 629APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
630AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); 630APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
631AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); 631APB_DEVICE(rtc, "dev:e8", RTC, NULL);
632AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); 632APB_DEVICE(sci0, "dev:f0", SCI, NULL);
633AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); 633APB_DEVICE(uart0, "dev:f1", UART0, NULL);
634AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); 634APB_DEVICE(uart1, "dev:f2", UART1, NULL);
635AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); 635APB_DEVICE(uart2, "dev:f3", UART2, NULL);
636AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data); 636APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
637 637
638static struct amba_device *amba_devs[] __initdata = { 638static struct amba_device *amba_devs[] __initdata = {
639 &dmac_device, 639 &dmac_device,
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 2ef2f555f315..683e60776a85 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -36,20 +36,10 @@ extern unsigned int mmc_status(struct device *dev);
36extern struct of_dev_auxdata versatile_auxdata_lookup[]; 36extern struct of_dev_auxdata versatile_auxdata_lookup[];
37#endif 37#endif
38 38
39#define AMBA_DEVICE(name,busid,base,plat) \ 39#define APB_DEVICE(name, busid, base, plat) \
40static struct amba_device name##_device = { \ 40static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
41 .dev = { \ 41
42 .coherent_dma_mask = ~0, \ 42#define AHB_DEVICE(name, busid, base, plat) \
43 .init_name = busid, \ 43static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
44 .platform_data = plat, \
45 }, \
46 .res = { \
47 .start = VERSATILE_##base##_BASE, \
48 .end = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
49 .flags = IORESOURCE_MEM, \
50 }, \
51 .dma_mask = ~0, \
52 .irq = base##_IRQ, \
53}
54 44
55#endif 45#endif
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
deleted file mode 100644
index f3fa347895f0..000000000000
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/system.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30 cpu_do_idle();
31}
32
33#endif
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 9581c197500c..19738331bd3d 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -58,28 +58,28 @@ static struct pl061_platform_data gpio3_plat_data = {
58 .irq_base = IRQ_GPIO3_START, 58 .irq_base = IRQ_GPIO3_START,
59}; 59};
60 60
61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } 61#define UART3_IRQ { IRQ_SIC_UART3 }
62#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ } 62#define SCI1_IRQ { IRQ_SIC_SCI3 }
63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } 63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
64 64
65/* 65/*
66 * These devices are connected via the core APB bridge 66 * These devices are connected via the core APB bridge
67 */ 67 */
68#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } 68#define GPIO2_IRQ { IRQ_GPIOINT2 }
69#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } 69#define GPIO3_IRQ { IRQ_GPIOINT3 }
70 70
71/* 71/*
72 * These devices are connected via the DMA APB bridge 72 * These devices are connected via the DMA APB bridge
73 */ 73 */
74 74
75/* FPGA Primecells */ 75/* FPGA Primecells */
76AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); 76APB_DEVICE(uart3, "fpga:09", UART3, NULL);
77AMBA_DEVICE(sci1, "fpga:0a", SCI1, NULL); 77APB_DEVICE(sci1, "fpga:0a", SCI1, NULL);
78AMBA_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); 78APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
79 79
80/* DevChip Primecells */ 80/* DevChip Primecells */
81AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); 81APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
82AMBA_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); 82APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
83 83
84static struct amba_device *amba_devs[] __initdata = { 84static struct amba_device *amba_devs[] __initdata = {
85 &uart3_device, 85 &uart3_device,