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-rw-r--r--arch/arm/mach-ux500/Makefile3
-rw-r--r--arch/arm/mach-ux500/board-mop500.c2
-rw-r--r--arch/arm/mach-ux500/clock.c106
-rw-r--r--arch/arm/mach-ux500/clock.h22
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c4
-rw-r--r--arch/arm/mach-ux500/cpu.c6
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c109
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h12
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h3
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db8500.h154
10 files changed, 412 insertions, 9 deletions
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index c7bc4199e3a8..4556aea9c3c5 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o 8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o
9obj-$(CONFIG_MACH_U5500) += board-u5500.o 9obj-$(CONFIG_MACH_U5500) += board-u5500.o
10obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o 10obj-$(CONFIG_SMP) += platsmp.o headsmp.o
11obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 072196c57263..bb8d7b771817 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -50,7 +50,7 @@ struct pl022_config_chip ab4500_chip_info = {
50 50
51static struct spi_board_info u8500_spi_devices[] = { 51static struct spi_board_info u8500_spi_devices[] = {
52 { 52 {
53 .modalias = "ab4500", 53 .modalias = "ab8500",
54 .controller_data = &ab4500_chip_info, 54 .controller_data = &ab4500_chip_info,
55 .max_speed_hz = 12000000, 55 .max_speed_hz = 12000000,
56 .bus_num = 0, 56 .bus_num = 0,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 1b2c9890e8b4..fe84b9021c7a 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -16,6 +16,7 @@
16 16
17#include <asm/clkdev.h> 17#include <asm/clkdev.h>
18 18
19#include <plat/mtu.h>
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include "clock.h" 21#include "clock.h"
21 22
@@ -59,6 +60,9 @@
59#define PRCM_DMACLK_MGT 0x074 60#define PRCM_DMACLK_MGT 0x074
60#define PRCM_B2R2CLK_MGT 0x078 61#define PRCM_B2R2CLK_MGT 0x078
61#define PRCM_TVCLK_MGT 0x07C 62#define PRCM_TVCLK_MGT 0x07C
63#define PRCM_TCR 0x1C8
64#define PRCM_TCR_STOPPED (1 << 16)
65#define PRCM_TCR_DOZE_MODE (1 << 17)
62#define PRCM_UNIPROCLK_MGT 0x278 66#define PRCM_UNIPROCLK_MGT 0x278
63#define PRCM_SSPCLK_MGT 0x280 67#define PRCM_SSPCLK_MGT 0x280
64#define PRCM_RNGCLK_MGT 0x284 68#define PRCM_RNGCLK_MGT 0x284
@@ -120,10 +124,95 @@ void clk_disable(struct clk *clk)
120} 124}
121EXPORT_SYMBOL(clk_disable); 125EXPORT_SYMBOL(clk_disable);
122 126
127/*
128 * The MTU has a separate, rather complex muxing setup
129 * with alternative parents (peripheral cluster or
130 * ULP or fixed 32768 Hz) depending on settings
131 */
132static unsigned long clk_mtu_get_rate(struct clk *clk)
133{
134 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
135 + PRCM_TCR;
136 u32 tcr = readl(addr);
137 int mtu = (int) clk->data;
138 /*
139 * One of these is selected eventually
140 * TODO: Replace the constant with a reference
141 * to the ULP source once this is modeled.
142 */
143 unsigned long clk32k = 32768;
144 unsigned long mturate;
145 unsigned long retclk;
146
147 /* Get the rate from the parent as a default */
148 if (clk->parent_periph)
149 mturate = clk_get_rate(clk->parent_periph);
150 else if (clk->parent_cluster)
151 mturate = clk_get_rate(clk->parent_cluster);
152 else
153 /* We need to be connected SOMEWHERE */
154 BUG();
155
156 /*
157 * Are we in doze mode?
158 * In this mode the parent peripheral or the fixed 32768 Hz
159 * clock is fed into the block.
160 */
161 if (!(tcr & PRCM_TCR_DOZE_MODE)) {
162 /*
163 * Here we're using the clock input from the APE ULP
164 * clock domain. But first: are the timers stopped?
165 */
166 if (tcr & PRCM_TCR_STOPPED) {
167 clk32k = 0;
168 mturate = 0;
169 } else {
170 /* Else default mode: 0 and 2.4 MHz */
171 clk32k = 0;
172 if (cpu_is_u5500())
173 /* DB5500 divides by 8 */
174 mturate /= 8;
175 else if (cpu_is_u8500ed()) {
176 /*
177 * This clocking setting must not be used
178 * in the ED chip, it is simply not
179 * connected anywhere!
180 */
181 mturate = 0;
182 BUG();
183 } else
184 /*
185 * In this mode the ulp38m4 clock is divided
186 * by a factor 16, on the DB8500 typically
187 * 38400000 / 16 ~ 2.4 MHz.
188 * TODO: Replace the constant with a reference
189 * to the ULP source once this is modeled.
190 */
191 mturate = 38400000 / 16;
192 }
193 }
194
195 /* Return the clock selected for this MTU */
196 if (tcr & (1 << mtu))
197 retclk = clk32k;
198 else
199 retclk = mturate;
200
201 pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
202 return retclk;
203}
204
123unsigned long clk_get_rate(struct clk *clk) 205unsigned long clk_get_rate(struct clk *clk)
124{ 206{
125 unsigned long rate; 207 unsigned long rate;
126 208
209 /*
210 * If there is a custom getrate callback for this clock,
211 * it will take precedence.
212 */
213 if (clk->get_rate)
214 return clk->get_rate(clk);
215
127 if (clk->ops && clk->ops->get_rate) 216 if (clk->ops && clk->ops->get_rate)
128 return clk->ops->get_rate(clk); 217 return clk->ops->get_rate(clk);
129 218
@@ -341,8 +430,9 @@ static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
341 430
342/* Peripheral Cluster #6 */ 431/* Peripheral Cluster #6 */
343 432
344static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL); 433/* MTU ID in data */
345static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL); 434static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
435static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
346static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); 436static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
347static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); 437static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
348static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); 438static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
@@ -357,8 +447,9 @@ static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
357/* Peripheral Cluster #7 */ 447/* Peripheral Cluster #7 */
358 448
359static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); 449static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
360static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL); 450/* MTU ID in data */
361static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL); 451static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
452static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
362static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); 453static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
363static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); 454static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
364 455
@@ -411,7 +502,7 @@ static struct clk_lookup u8500_common_clks[] = {
411 CLK(apetraceclk, "apetrace", NULL), 502 CLK(apetraceclk, "apetrace", NULL),
412 CLK(mcdeclk, "mcde", NULL), 503 CLK(mcdeclk, "mcde", NULL),
413 CLK(ipi2clk, "ipi2", NULL), 504 CLK(ipi2clk, "ipi2", NULL),
414 CLK(dmaclk, "dma40", NULL), 505 CLK(dmaclk, "dma40.0", NULL),
415 CLK(b2r2clk, "b2r2", NULL), 506 CLK(b2r2clk, "b2r2", NULL),
416 CLK(tvclk, "tv", NULL), 507 CLK(tvclk, "tv", NULL),
417}; 508};
@@ -503,15 +594,17 @@ static struct clk_lookup u8500_v1_clks[] = {
503 CLK(uiccclk, "uicc", NULL), 594 CLK(uiccclk, "uicc", NULL),
504}; 595};
505 596
506static int __init clk_init(void) 597int __init clk_init(void)
507{ 598{
508 if (cpu_is_u8500ed()) { 599 if (cpu_is_u8500ed()) {
509 clk_prcmu_ops.enable = clk_prcmu_ed_enable; 600 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
510 clk_prcmu_ops.disable = clk_prcmu_ed_disable; 601 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
602 clk_per6clk.rate = 100000000;
511 } else if (cpu_is_u5500()) { 603 } else if (cpu_is_u5500()) {
512 /* Clock tree for U5500 not implemented yet */ 604 /* Clock tree for U5500 not implemented yet */
513 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; 605 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
514 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; 606 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
607 clk_per6clk.rate = 26000000;
515 } 608 }
516 609
517 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); 610 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
@@ -522,4 +615,3 @@ static int __init clk_init(void)
522 615
523 return 0; 616 return 0;
524} 617}
525arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index e4f99b65026f..a05802501527 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -28,6 +28,9 @@ struct clkops {
28 * @ops: pointer to clkops struct used to control this clock 28 * @ops: pointer to clkops struct used to control this clock
29 * @name: name, for debugging 29 * @name: name, for debugging
30 * @enabled: refcount. positive if enabled, zero if disabled 30 * @enabled: refcount. positive if enabled, zero if disabled
31 * @get_rate: custom callback for getting the clock rate
32 * @data: custom per-clock data for example for the get_rate
33 * callback
31 * @rate: fixed rate for clocks which don't implement 34 * @rate: fixed rate for clocks which don't implement
32 * ops->getrate 35 * ops->getrate
33 * @prcmu_cg_off: address offset of the combined enable/disable register 36 * @prcmu_cg_off: address offset of the combined enable/disable register
@@ -67,6 +70,8 @@ struct clk {
67 const struct clkops *ops; 70 const struct clkops *ops;
68 const char *name; 71 const char *name;
69 unsigned int enabled; 72 unsigned int enabled;
73 unsigned long (*get_rate)(struct clk *);
74 void *data;
70 75
71 unsigned long rate; 76 unsigned long rate;
72 struct list_head list; 77 struct list_head list;
@@ -117,9 +122,26 @@ struct clk clk_##_name = { \
117 .parent_periph = _kernclk \ 122 .parent_periph = _kernclk \
118 } 123 }
119 124
125#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
126struct clk clk_##_name = { \
127 .name = #_name, \
128 .ops = &clk_prcc_ops, \
129 .cluster = _pclust, \
130 .prcc_bus = _bus_en, \
131 .prcc_kernel = _kernel_en, \
132 .parent_cluster = &clk_per##_pclust##clk, \
133 .parent_periph = _kernclk, \
134 .get_rate = _callback, \
135 .data = (void *) _data \
136 }
137
138
120#define CLK(_clk, _devname, _conname) \ 139#define CLK(_clk, _devname, _conname) \
121 { \ 140 { \
122 .clk = &clk_##_clk, \ 141 .clk = &clk_##_clk, \
123 .dev_id = _devname, \ 142 .dev_id = _devname, \
124 .con_id = _conname, \ 143 .con_id = _conname, \
125 } 144 }
145
146int __init clk_db8500_ed_fixup(void);
147int __init clk_init(void);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index d04299f3b6b5..f21c444edd99 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -32,6 +32,7 @@ static struct platform_device *platform_devs[] __initdata = {
32 &u8500_gpio_devs[6], 32 &u8500_gpio_devs[6],
33 &u8500_gpio_devs[7], 33 &u8500_gpio_devs[7],
34 &u8500_gpio_devs[8], 34 &u8500_gpio_devs[8],
35 &u8500_dma40_device,
35}; 36};
36 37
37/* minimum static i/o mapping required to boot U8500 platforms */ 38/* minimum static i/o mapping required to boot U8500 platforms */
@@ -71,6 +72,9 @@ void __init u8500_init_devices(void)
71{ 72{
72 ux500_init_devices(); 73 ux500_init_devices();
73 74
75 if (cpu_is_u8500ed())
76 dma40_u8500ed_fixup();
77
74 /* Register the platform devices */ 78 /* Register the platform devices */
75 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 79 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
76 80
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d81ad023963c..e0fd747e447a 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -62,6 +62,12 @@ void __init ux500_init_irq(void)
62{ 62{
63 gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29); 63 gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
64 gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); 64 gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
65
66 /*
67 * Init clocks here so that they are available for system timer
68 * initialization.
69 */
70 clk_init();
65} 71}
66 72
67#ifdef CONFIG_CACHE_L2X0 73#ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 20334236afce..822903421943 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -12,9 +12,13 @@
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/amba/bus.h> 13#include <linux/amba/bus.h>
14 14
15#include <plat/ste_dma40.h>
16
15#include <mach/hardware.h> 17#include <mach/hardware.h>
16#include <mach/setup.h> 18#include <mach/setup.h>
17 19
20#include "ste-dma40-db8500.h"
21
18static struct nmk_gpio_platform_data u8500_gpio_data[] = { 22static struct nmk_gpio_platform_data u8500_gpio_data[] = {
19 GPIO_DATA("GPIO-0-31", 0), 23 GPIO_DATA("GPIO-0-31", 0),
20 GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */ 24 GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */
@@ -105,3 +109,108 @@ struct platform_device u8500_i2c4_device = {
105 .resource = u8500_i2c4_resources, 109 .resource = u8500_i2c4_resources,
106 .num_resources = ARRAY_SIZE(u8500_i2c4_resources), 110 .num_resources = ARRAY_SIZE(u8500_i2c4_resources),
107}; 111};
112
113static struct resource dma40_resources[] = {
114 [0] = {
115 .start = U8500_DMA_BASE,
116 .end = U8500_DMA_BASE + SZ_4K - 1,
117 .flags = IORESOURCE_MEM,
118 .name = "base",
119 },
120 [1] = {
121 .start = U8500_DMA_LCPA_BASE,
122 .end = U8500_DMA_LCPA_BASE + SZ_4K - 1,
123 .flags = IORESOURCE_MEM,
124 .name = "lcpa",
125 },
126 [2] = {
127 .start = U8500_DMA_LCLA_BASE,
128 .end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1,
129 .flags = IORESOURCE_MEM,
130 .name = "lcla",
131 },
132 [3] = {
133 .start = IRQ_DMA,
134 .end = IRQ_DMA,
135 .flags = IORESOURCE_IRQ}
136};
137
138/* Default configuration for physcial memcpy */
139struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
140 .channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE |
141 STEDMA40_LOW_PRIORITY_CHANNEL |
142 STEDMA40_PCHAN_BASIC_MODE),
143 .dir = STEDMA40_MEM_TO_MEM,
144
145 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
146 .src_info.data_width = STEDMA40_BYTE_WIDTH,
147 .src_info.psize = STEDMA40_PSIZE_PHY_1,
148
149 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
150 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
151 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
152
153};
154/* Default configuration for logical memcpy */
155struct stedma40_chan_cfg dma40_memcpy_conf_log = {
156 .channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE |
157 STEDMA40_LOW_PRIORITY_CHANNEL |
158 STEDMA40_LCHAN_SRC_LOG_DST_LOG |
159 STEDMA40_NO_TIM_FOR_LINK),
160 .dir = STEDMA40_MEM_TO_MEM,
161
162 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
163 .src_info.data_width = STEDMA40_BYTE_WIDTH,
164 .src_info.psize = STEDMA40_PSIZE_LOG_1,
165
166 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
167 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
168 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
169
170};
171
172/*
173 * Mapping between destination event lines and physical device address.
174 * The event line is tied to a device and therefor the address is constant.
175 */
176static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV];
177
178/* Mapping between source event lines and physical device address */
179static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
180
181/* Reserved event lines for memcpy only */
182static int dma40_memcpy_event[] = {
183 STEDMA40_MEMCPY_TX_1,
184 STEDMA40_MEMCPY_TX_2,
185 STEDMA40_MEMCPY_TX_3,
186 STEDMA40_MEMCPY_TX_4,
187};
188
189static struct stedma40_platform_data dma40_plat_data = {
190 .dev_len = STEDMA40_NR_DEV,
191 .dev_rx = dma40_rx_map,
192 .dev_tx = dma40_tx_map,
193 .memcpy = dma40_memcpy_event,
194 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
195 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
196 .memcpy_conf_log = &dma40_memcpy_conf_log,
197 .llis_per_log = 8,
198};
199
200struct platform_device u8500_dma40_device = {
201 .dev = {
202 .platform_data = &dma40_plat_data,
203 },
204 .name = "dma40",
205 .id = 0,
206 .num_resources = ARRAY_SIZE(dma40_resources),
207 .resource = dma40_resources
208};
209
210void dma40_u8500ed_fixup(void)
211{
212 dma40_plat_data.memcpy = NULL;
213 dma40_plat_data.memcpy_len = 0;
214 dma40_resources[0].start = U8500_DMA_BASE_ED;
215 dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
216}
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 9169e1e382a3..85fc6a80b386 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -7,6 +7,18 @@
7#ifndef __MACH_DB8500_REGS_H 7#ifndef __MACH_DB8500_REGS_H
8#define __MACH_DB8500_REGS_H 8#define __MACH_DB8500_REGS_H
9 9
10/* Base address and bank offsets for ESRAM */
11#define U8500_ESRAM_BASE 0x40000000
12#define U8500_ESRAM_BANK_SIZE 0x00020000
13#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
14#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
18/* Use bank 4 for DMA LCLA and LCPA */
19#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
20#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK4 + 0x4000)
21
10#define U8500_PER3_BASE 0x80000000 22#define U8500_PER3_BASE 0x80000000
11#define U8500_STM_BASE 0x80100000 23#define U8500_STM_BASE 0x80100000
12#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) 24#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 0422af00a56e..c2b2f2574947 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -25,5 +25,8 @@ extern struct platform_device ux500_i2c3_device;
25 25
26extern struct platform_device u8500_i2c0_device; 26extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device; 27extern struct platform_device u8500_i2c4_device;
28extern struct platform_device u8500_dma40_device;
29
30void dma40_u8500ed_fixup(void);
28 31
29#endif 32#endif
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
new file mode 100644
index 000000000000..e7016278dfa9
--- /dev/null
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -0,0 +1,154 @@
1/*
2 * arch/arm/mach-ux500/ste_dma40_db8500.h
3 * DB8500-SoC-specific configuration for DMA40
4 *
5 * Copyright (C) ST-Ericsson 2007-2010
6 * License terms: GNU General Public License (GPL) version 2
7 * Author: Per Friden <per.friden@stericsson.com>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9 */
10#ifndef STE_DMA40_DB8500_H
11#define STE_DMA40_DB8500_H
12
13#define STEDMA40_NR_DEV 64
14
15enum dma_src_dev_type {
16 STEDMA40_DEV_SPI0_RX = 0,
17 STEDMA40_DEV_SD_MMC0_RX = 1,
18 STEDMA40_DEV_SD_MMC1_RX = 2,
19 STEDMA40_DEV_SD_MMC2_RX = 3,
20 STEDMA40_DEV_I2C1_RX = 4,
21 STEDMA40_DEV_I2C3_RX = 5,
22 STEDMA40_DEV_I2C2_RX = 6,
23 STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */
24 STEDMA40_DEV_SSP0_RX = 8,
25 STEDMA40_DEV_SSP1_RX = 9,
26 STEDMA40_DEV_MCDE_RX = 10,
27 STEDMA40_DEV_UART2_RX = 11,
28 STEDMA40_DEV_UART1_RX = 12,
29 STEDMA40_DEV_UART0_RX = 13,
30 STEDMA40_DEV_MSP2_RX = 14,
31 STEDMA40_DEV_I2C0_RX = 15,
32 STEDMA40_DEV_USB_OTG_IEP_8 = 16,
33 STEDMA40_DEV_USB_OTG_IEP_1_9 = 17,
34 STEDMA40_DEV_USB_OTG_IEP_2_10 = 18,
35 STEDMA40_DEV_USB_OTG_IEP_3_11 = 19,
36 STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
37 STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
38 STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
39 STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
40 STEDMA40_DEV_SRC_SXA0_RX_TX = 24,
41 STEDMA40_DEV_SRC_SXA1_RX_TX = 25,
42 STEDMA40_DEV_SRC_SXA2_RX_TX = 26,
43 STEDMA40_DEV_SRC_SXA3_RX_TX = 27,
44 STEDMA40_DEV_SD_MM2_RX = 28,
45 STEDMA40_DEV_SD_MM0_RX = 29,
46 STEDMA40_DEV_MSP1_RX = 30,
47 /*
48 * This channel is either SlimBus or MSP,
49 * never both at the same time.
50 */
51 STEDMA40_SLIM0_CH0_RX = 31,
52 STEDMA40_DEV_MSP0_RX = 31,
53 STEDMA40_DEV_SD_MM1_RX = 32,
54 STEDMA40_DEV_SPI2_RX = 33,
55 STEDMA40_DEV_I2C3_RX2 = 34,
56 STEDMA40_DEV_SPI1_RX = 35,
57 STEDMA40_DEV_USB_OTG_IEP_4_12 = 36,
58 STEDMA40_DEV_USB_OTG_IEP_5_13 = 37,
59 STEDMA40_DEV_USB_OTG_IEP_6_14 = 38,
60 STEDMA40_DEV_USB_OTG_IEP_7_15 = 39,
61 STEDMA40_DEV_SPI3_RX = 40,
62 STEDMA40_DEV_SD_MM3_RX = 41,
63 STEDMA40_DEV_SD_MM4_RX = 42,
64 STEDMA40_DEV_SD_MM5_RX = 43,
65 STEDMA40_DEV_SRC_SXA4_RX_TX = 44,
66 STEDMA40_DEV_SRC_SXA5_RX_TX = 45,
67 STEDMA40_DEV_SRC_SXA6_RX_TX = 46,
68 STEDMA40_DEV_SRC_SXA7_RX_TX = 47,
69 STEDMA40_DEV_CAC1_RX = 48,
70 /* RX channels 49 and 50 are unused */
71 STEDMA40_DEV_MSHC_RX = 51,
72 STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52,
73 STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53,
74 STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54,
75 STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
76 /* RX channels 56 thru 60 are unused */
77 STEDMA40_DEV_CAC0_RX = 61,
78 /* RX channels 62 and 63 are unused */
79};
80
81enum dma_dest_dev_type {
82 STEDMA40_DEV_SPI0_TX = 0,
83 STEDMA40_DEV_SD_MMC0_TX = 1,
84 STEDMA40_DEV_SD_MMC1_TX = 2,
85 STEDMA40_DEV_SD_MMC2_TX = 3,
86 STEDMA40_DEV_I2C1_TX = 4,
87 STEDMA40_DEV_I2C3_TX = 5,
88 STEDMA40_DEV_I2C2_TX = 6,
89 STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */
90 STEDMA40_DEV_SSP0_TX = 8,
91 STEDMA40_DEV_SSP1_TX = 9,
92 /* TX channel 10 is unused */
93 STEDMA40_DEV_UART2_TX = 11,
94 STEDMA40_DEV_UART1_TX = 12,
95 STEDMA40_DEV_UART0_TX= 13,
96 STEDMA40_DEV_MSP2_TX = 14,
97 STEDMA40_DEV_I2C0_TX = 15,
98 STEDMA40_DEV_USB_OTG_OEP_8 = 16,
99 STEDMA40_DEV_USB_OTG_OEP_1_9 = 17,
100 STEDMA40_DEV_USB_OTG_OEP_2_10= 18,
101 STEDMA40_DEV_USB_OTG_OEP_3_11 = 19,
102 STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
103 STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
104 STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
105 STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
106 STEDMA40_DEV_DST_SXA0_RX_TX = 24,
107 STEDMA40_DEV_DST_SXA1_RX_TX = 25,
108 STEDMA40_DEV_DST_SXA2_RX_TX = 26,
109 STEDMA40_DEV_DST_SXA3_RX_TX = 27,
110 STEDMA40_DEV_SD_MM2_TX = 28,
111 STEDMA40_DEV_SD_MM0_TX = 29,
112 STEDMA40_DEV_MSP1_TX = 30,
113 /*
114 * This channel is either SlimBus or MSP,
115 * never both at the same time.
116 */
117 STEDMA40_SLIM0_CH0_TX = 31,
118 STEDMA40_DEV_MSP0_TX = 31,
119 STEDMA40_DEV_SD_MM1_TX = 32,
120 STEDMA40_DEV_SPI2_TX = 33,
121 /* Secondary I2C3 channel */
122 STEDMA40_DEV_I2C3_TX2 = 34,
123 STEDMA40_DEV_SPI1_TX = 35,
124 STEDMA40_DEV_USB_OTG_OEP_4_12 = 36,
125 STEDMA40_DEV_USB_OTG_OEP_5_13 = 37,
126 STEDMA40_DEV_USB_OTG_OEP_6_14 = 38,
127 STEDMA40_DEV_USB_OTG_OEP_7_15 = 39,
128 STEDMA40_DEV_SPI3_TX = 40,
129 STEDMA40_DEV_SD_MM3_TX = 41,
130 STEDMA40_DEV_SD_MM4_TX = 42,
131 STEDMA40_DEV_SD_MM5_TX = 43,
132 STEDMA40_DEV_DST_SXA4_RX_TX = 44,
133 STEDMA40_DEV_DST_SXA5_RX_TX = 45,
134 STEDMA40_DEV_DST_SXA6_RX_TX = 46,
135 STEDMA40_DEV_DST_SXA7_RX_TX = 47,
136 STEDMA40_DEV_CAC1_TX = 48,
137 STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,
138 STEDMA40_DEV_HAC1_TX = 50,
139 STEDMA40_MEMXCPY_TX_0 = 51,
140 STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,
141 STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,
142 STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,
143 STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55,
144 STEDMA40_MEMCPY_TX_1 = 56,
145 STEDMA40_MEMCPY_TX_2 = 57,
146 STEDMA40_MEMCPY_TX_3 = 58,
147 STEDMA40_MEMCPY_TX_4 = 59,
148 STEDMA40_MEMCPY_TX_5 = 60,
149 STEDMA40_DEV_CAC0_TX = 61,
150 STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
151 STEDMA40_DEV_HAC0_TX = 63,
152};
153
154#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 15:36:29 -0500