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-rw-r--r--arch/arm/mach-tegra/Kconfig3
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/board-harmony.c7
-rw-r--r--arch/arm/mach-tegra/gpio.c9
-rw-r--r--arch/arm/mach-tegra/include/mach/barriers.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/legacy_irq.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/smp.h14
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h (renamed from arch/arm/mach-tegra/include/mach/harmony_audio.h)5
-rw-r--r--arch/arm/mach-tegra/irq.c174
-rw-r--r--arch/arm/mach-tegra/legacy_irq.c215
-rw-r--r--arch/arm/mach-tegra/platsmp.c3
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
-rw-r--r--arch/arm/mach-tegra/timer.c16
13 files changed, 98 insertions, 389 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 3cdeffc97b44..5ec1846aa1d0 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -27,12 +27,14 @@ comment "Tegra board type"
27 27
28config MACH_HARMONY 28config MACH_HARMONY
29 bool "Harmony board" 29 bool "Harmony board"
30 select MACH_HAS_SND_SOC_TEGRA_WM8903
30 help 31 help
31 Support for nVidia Harmony development platform 32 Support for nVidia Harmony development platform
32 33
33config MACH_KAEN 34config MACH_KAEN
34 bool "Kaen board" 35 bool "Kaen board"
35 select MACH_SEABOARD 36 select MACH_SEABOARD
37 select MACH_HAS_SND_SOC_TEGRA_WM8903
36 help 38 help
37 Support for the Kaen version of Seaboard 39 Support for the Kaen version of Seaboard
38 40
@@ -43,6 +45,7 @@ config MACH_PAZ00
43 45
44config MACH_SEABOARD 46config MACH_SEABOARD
45 bool "Seaboard board" 47 bool "Seaboard board"
48 select MACH_HAS_SND_SOC_TEGRA_WM8903
46 help 49 help
47 Support for nVidia Seaboard development platform. It will 50 Support for nVidia Seaboard development platform. It will
48 also be included for some of the derivative boards that 51 also be included for some of the derivative boards that
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe05038c27..823c703e573c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
1obj-y += common.o 1obj-y += common.o
2obj-y += devices.o 2obj-y += devices.o
3obj-y += io.o 3obj-y += io.o
4obj-y += irq.o legacy_irq.o 4obj-y += irq.o
5obj-y += clock.o 5obj-y += clock.o
6obj-y += timer.o 6obj-y += timer.o
7obj-y += gpio.o 7obj-y += gpio.o
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 75c918a86a31..30e18bc60647 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -34,7 +34,7 @@
34#include <asm/mach/time.h> 34#include <asm/mach/time.h>
35#include <asm/setup.h> 35#include <asm/setup.h>
36 36
37#include <mach/harmony_audio.h> 37#include <mach/tegra_wm8903_pdata.h>
38#include <mach/iomap.h> 38#include <mach/iomap.h>
39#include <mach/irqs.h> 39#include <mach/irqs.h>
40#include <mach/sdhci.h> 40#include <mach/sdhci.h>
@@ -67,15 +67,16 @@ static struct platform_device debug_uart = {
67 }, 67 },
68}; 68};
69 69
70static struct harmony_audio_platform_data harmony_audio_pdata = { 70static struct tegra_wm8903_platform_data harmony_audio_pdata = {
71 .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, 71 .gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
72 .gpio_hp_det = TEGRA_GPIO_HP_DET, 72 .gpio_hp_det = TEGRA_GPIO_HP_DET,
73 .gpio_hp_mute = -1,
73 .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, 74 .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN,
74 .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, 75 .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN,
75}; 76};
76 77
77static struct platform_device harmony_audio_device = { 78static struct platform_device harmony_audio_device = {
78 .name = "tegra-snd-harmony", 79 .name = "tegra-snd-wm8903",
79 .id = 0, 80 .id = 0,
80 .dev = { 81 .dev = {
81 .platform_data = &harmony_audio_pdata, 82 .platform_data = &harmony_audio_pdata,
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 65a1aba6823d..919d63837736 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -24,6 +24,8 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26 26
27#include <asm/mach/irq.h>
28
27#include <mach/iomap.h> 29#include <mach/iomap.h>
28#include <mach/suspend.h> 30#include <mach/suspend.h>
29 31
@@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
221 int port; 223 int port;
222 int pin; 224 int pin;
223 int unmasked = 0; 225 int unmasked = 0;
226 struct irq_chip *chip = irq_desc_get_chip(desc);
224 227
225 desc->irq_data.chip->irq_ack(&desc->irq_data); 228 chained_irq_enter(chip, desc);
226 229
227 bank = irq_get_handler_data(irq); 230 bank = irq_get_handler_data(irq);
228 231
@@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
241 */ 244 */
242 if (lvl & (0x100 << pin)) { 245 if (lvl & (0x100 << pin)) {
243 unmasked = 1; 246 unmasked = 1;
244 desc->irq_data.chip->irq_unmask(&desc->irq_data); 247 chained_irq_exit(chip, desc);
245 } 248 }
246 249
247 generic_handle_irq(gpio_to_irq(gpio + pin)); 250 generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
249 } 252 }
250 253
251 if (!unmasked) 254 if (!unmasked)
252 desc->irq_data.chip->irq_unmask(&desc->irq_data); 255 chained_irq_exit(chip, desc);
253 256
254} 257}
255 258
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
index cc115174899b..425b42e91ef6 100644
--- a/arch/arm/mach-tegra/include/mach/barriers.h
+++ b/arch/arm/mach-tegra/include/mach/barriers.h
@@ -23,7 +23,7 @@
23 23
24#include <asm/outercache.h> 24#include <asm/outercache.h>
25 25
26#define rmb() dmb() 26#define rmb() dsb()
27#define wmb() do { dsb(); outer_sync(); } while (0) 27#define wmb() do { dsb(); outer_sync(); } while (0)
28#define mb() wmb() 28#define mb() wmb()
29 29
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index d898c0e3d905..000000000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/legacy_irq.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
19#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
20
21void tegra_legacy_mask_irq(unsigned int irq);
22void tegra_legacy_unmask_irq(unsigned int irq);
23void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
24void tegra_legacy_force_irq_set(unsigned int irq);
25void tegra_legacy_force_irq_clr(unsigned int irq);
26int tegra_legacy_force_irq_status(unsigned int irq);
27void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
28unsigned long tegra_legacy_vfiq(int nr);
29unsigned long tegra_legacy_class(int nr);
30int tegra_legacy_irq_set_wake(int irq, int enable);
31void tegra_legacy_irq_set_lp1_wake_mask(void);
32void tegra_legacy_irq_restore_mask(void);
33void tegra_init_legacy_irq(void);
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
deleted file mode 100644
index c8221b38ee7c..000000000000
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13
14#endif
diff --git a/arch/arm/mach-tegra/include/mach/harmony_audio.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
index af086500ab7d..9d293344a7ff 100644
--- a/arch/arm/mach-tegra/include/mach/harmony_audio.h
+++ b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-tegra/include/mach/harmony_audio.h 2 * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
3 * 3 *
4 * Copyright 2011 NVIDIA, Inc. 4 * Copyright 2011 NVIDIA, Inc.
5 * 5 *
@@ -14,9 +14,10 @@
14 * 14 *
15 */ 15 */
16 16
17struct harmony_audio_platform_data { 17struct tegra_wm8903_platform_data {
18 int gpio_spkr_en; 18 int gpio_spkr_en;
19 int gpio_hp_det; 19 int gpio_hp_det;
20 int gpio_hp_mute;
20 int gpio_int_mic_en; 21 int gpio_int_mic_en;
21 int gpio_ext_mic_en; 22 int gpio_ext_mic_en;
22}; 23};
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d8995b27..4956c3cea731 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2011 Google, Inc.
3 * 3 *
4 * Author: 4 * Author:
5 * Colin Cross <ccross@google.com> 5 * Colin Cross <ccross@android.com>
6 * 6 *
7 * Copyright (C) 2010, NVIDIA Corporation 7 * Copyright (C) 2010, NVIDIA Corporation
8 * 8 *
@@ -18,8 +18,6 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/interrupt.h> 21#include <linux/interrupt.h>
24#include <linux/irq.h> 22#include <linux/irq.h>
25#include <linux/io.h> 23#include <linux/io.h>
@@ -27,134 +25,110 @@
27#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
28 26
29#include <mach/iomap.h> 27#include <mach/iomap.h>
30#include <mach/legacy_irq.h>
31#include <mach/suspend.h>
32 28
33#include "board.h" 29#include "board.h"
34 30
35#define PMC_CTRL 0x0 31#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
36#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) 32#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
37#define PMC_WAKE_MASK 0xc 33#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
38#define PMC_WAKE_LEVEL 0x10 34
39#define PMC_WAKE_STATUS 0x14 35#define ICTLR_CPU_IEP_VFIQ 0x08
40#define PMC_SW_WAKE_STATUS 0x18 36#define ICTLR_CPU_IEP_FIR 0x14
41#define PMC_DPD_SAMPLE 0x20 37#define ICTLR_CPU_IEP_FIR_SET 0x18
38#define ICTLR_CPU_IEP_FIR_CLR 0x1c
39
40#define ICTLR_CPU_IER 0x20
41#define ICTLR_CPU_IER_SET 0x24
42#define ICTLR_CPU_IER_CLR 0x28
43#define ICTLR_CPU_IEP_CLASS 0x2C
44
45#define ICTLR_COP_IER 0x30
46#define ICTLR_COP_IER_SET 0x34
47#define ICTLR_COP_IER_CLR 0x38
48#define ICTLR_COP_IEP_CLASS 0x3c
49
50#define NUM_ICTLRS 4
51#define FIRST_LEGACY_IRQ 32
52
53static void __iomem *ictlr_reg_base[] = {
54 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
55 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
56 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
57 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
58};
42 59
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 60static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
61{
62 void __iomem *base;
63 u32 mask;
44 64
45static u32 tegra_lp0_wake_enb; 65 BUG_ON(irq < FIRST_LEGACY_IRQ ||
46static u32 tegra_lp0_wake_level; 66 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
47static u32 tegra_lp0_wake_level_any;
48 67
49static void (*tegra_gic_mask_irq)(struct irq_data *d); 68 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
50static void (*tegra_gic_unmask_irq)(struct irq_data *d); 69 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
51static void (*tegra_gic_ack_irq)(struct irq_data *d);
52 70
53/* ensures that sufficient time is passed for a register write to 71 __raw_writel(mask, base + reg);
54 * serialize into the 32KHz domain */
55static void pmc_32kwritel(u32 val, unsigned long offs)
56{
57 writel(val, pmc + offs);
58 udelay(130);
59} 72}
60 73
61int tegra_set_lp1_wake(int irq, int enable) 74static void tegra_mask(struct irq_data *d)
62{ 75{
63 return tegra_legacy_irq_set_wake(irq, enable); 76 if (d->irq < FIRST_LEGACY_IRQ)
77 return;
78
79 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
64} 80}
65 81
66void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) 82static void tegra_unmask(struct irq_data *d)
67{ 83{
68 u32 temp; 84 if (d->irq < FIRST_LEGACY_IRQ)
69 u32 status; 85 return;
70 u32 lvl;
71
72 wake_level &= wake_enb;
73 wake_any &= wake_enb;
74 86
75 wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); 87 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
76 wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
77
78 wake_enb |= tegra_lp0_wake_enb;
79
80 pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
81 temp = readl(pmc + PMC_CTRL);
82 temp |= PMC_CTRL_LATCH_WAKEUPS;
83 pmc_32kwritel(temp, PMC_CTRL);
84 temp &= ~PMC_CTRL_LATCH_WAKEUPS;
85 pmc_32kwritel(temp, PMC_CTRL);
86 status = readl(pmc + PMC_SW_WAKE_STATUS);
87 lvl = readl(pmc + PMC_WAKE_LEVEL);
88
89 /* flip the wakeup trigger for any-edge triggered pads
90 * which are currently asserting as wakeups */
91 lvl ^= status;
92 lvl &= wake_any;
93
94 wake_level |= lvl;
95
96 writel(wake_level, pmc + PMC_WAKE_LEVEL);
97 /* Enable DPD sample to trigger sampling pads data and direction
98 * in which pad will be driven during lp0 mode*/
99 writel(0x1, pmc + PMC_DPD_SAMPLE);
100
101 writel(wake_enb, pmc + PMC_WAKE_MASK);
102} 88}
103 89
104static void tegra_mask(struct irq_data *d) 90static void tegra_ack(struct irq_data *d)
105{ 91{
106 tegra_gic_mask_irq(d); 92 if (d->irq < FIRST_LEGACY_IRQ)
107 tegra_legacy_mask_irq(d->irq); 93 return;
108}
109 94
110static void tegra_unmask(struct irq_data *d) 95 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
111{
112 tegra_gic_unmask_irq(d);
113 tegra_legacy_unmask_irq(d->irq);
114} 96}
115 97
116static void tegra_ack(struct irq_data *d) 98static void tegra_eoi(struct irq_data *d)
117{ 99{
118 tegra_legacy_force_irq_clr(d->irq); 100 if (d->irq < FIRST_LEGACY_IRQ)
119 tegra_gic_ack_irq(d); 101 return;
102
103 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
120} 104}
121 105
122static int tegra_retrigger(struct irq_data *d) 106static int tegra_retrigger(struct irq_data *d)
123{ 107{
124 tegra_legacy_force_irq_set(d->irq); 108 if (d->irq < FIRST_LEGACY_IRQ)
109 return 0;
110
111 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
112
125 return 1; 113 return 1;
126} 114}
127 115
128static struct irq_chip tegra_irq = {
129 .name = "PPI",
130 .irq_ack = tegra_ack,
131 .irq_mask = tegra_mask,
132 .irq_unmask = tegra_unmask,
133 .irq_retrigger = tegra_retrigger,
134};
135
136void __init tegra_init_irq(void) 116void __init tegra_init_irq(void)
137{ 117{
138 struct irq_chip *gic; 118 int i;
139 unsigned int i;
140 int irq;
141 119
142 tegra_init_legacy_irq(); 120 for (i = 0; i < NUM_ICTLRS; i++) {
121 void __iomem *ictlr = ictlr_reg_base[i];
122 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
123 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
124 }
125
126 gic_arch_extn.irq_ack = tegra_ack;
127 gic_arch_extn.irq_eoi = tegra_eoi;
128 gic_arch_extn.irq_mask = tegra_mask;
129 gic_arch_extn.irq_unmask = tegra_unmask;
130 gic_arch_extn.irq_retrigger = tegra_retrigger;
143 131
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 132 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 133 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146
147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack;
151#ifdef CONFIG_SMP
152 tegra_irq.irq_set_affinity = gic->irq_set_affinity;
153#endif
154
155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i;
157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 set_irq_flags(irq, IRQF_VALID);
159 }
160} 134}
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index 38eb719a4f53..000000000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * arch/arm/mach-tegra/legacy_irq.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <mach/iomap.h>
21#include <mach/irqs.h>
22#include <mach/legacy_irq.h>
23
24#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
25#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
26#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
27
28#define ICTLR_CPU_IEP_VFIQ 0x08
29#define ICTLR_CPU_IEP_FIR 0x14
30#define ICTLR_CPU_IEP_FIR_SET 0x18
31#define ICTLR_CPU_IEP_FIR_CLR 0x1c
32
33#define ICTLR_CPU_IER 0x20
34#define ICTLR_CPU_IER_SET 0x24
35#define ICTLR_CPU_IER_CLR 0x28
36#define ICTLR_CPU_IEP_CLASS 0x2C
37
38#define ICTLR_COP_IER 0x30
39#define ICTLR_COP_IER_SET 0x34
40#define ICTLR_COP_IER_CLR 0x38
41#define ICTLR_COP_IEP_CLASS 0x3c
42
43#define NUM_ICTLRS 4
44
45static void __iomem *ictlr_reg_base[] = {
46 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
47 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
48 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
49 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
50};
51
52static u32 tegra_legacy_wake_mask[4];
53static u32 tegra_legacy_saved_mask[4];
54
55/* When going into deep sleep, the CPU is powered down, taking the GIC with it
56 In order to wake, the wake interrupts need to be enabled in the legacy
57 interrupt controller. */
58void tegra_legacy_unmask_irq(unsigned int irq)
59{
60 void __iomem *base;
61 pr_debug("%s: %d\n", __func__, irq);
62
63 irq -= 32;
64 base = ictlr_reg_base[irq>>5];
65 writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
66}
67
68void tegra_legacy_mask_irq(unsigned int irq)
69{
70 void __iomem *base;
71 pr_debug("%s: %d\n", __func__, irq);
72
73 irq -= 32;
74 base = ictlr_reg_base[irq>>5];
75 writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
76}
77
78void tegra_legacy_force_irq_set(unsigned int irq)
79{
80 void __iomem *base;
81 pr_debug("%s: %d\n", __func__, irq);
82
83 irq -= 32;
84 base = ictlr_reg_base[irq>>5];
85 writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
86}
87
88void tegra_legacy_force_irq_clr(unsigned int irq)
89{
90 void __iomem *base;
91 pr_debug("%s: %d\n", __func__, irq);
92
93 irq -= 32;
94 base = ictlr_reg_base[irq>>5];
95 writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
96}
97
98int tegra_legacy_force_irq_status(unsigned int irq)
99{
100 void __iomem *base;
101 pr_debug("%s: %d\n", __func__, irq);
102
103 irq -= 32;
104 base = ictlr_reg_base[irq>>5];
105 return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
106}
107
108void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
109{
110 void __iomem *base;
111 pr_debug("%s: %d\n", __func__, irq);
112
113 irq -= 32;
114 base = ictlr_reg_base[irq>>5];
115 writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
116}
117
118unsigned long tegra_legacy_vfiq(int nr)
119{
120 void __iomem *base;
121 base = ictlr_reg_base[nr];
122 return readl(base + ICTLR_CPU_IEP_VFIQ);
123}
124
125unsigned long tegra_legacy_class(int nr)
126{
127 void __iomem *base;
128 base = ictlr_reg_base[nr];
129 return readl(base + ICTLR_CPU_IEP_CLASS);
130}
131
132int tegra_legacy_irq_set_wake(int irq, int enable)
133{
134 irq -= 32;
135 if (enable)
136 tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
137 else
138 tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
139
140 return 0;
141}
142
143void tegra_legacy_irq_set_lp1_wake_mask(void)
144{
145 void __iomem *base;
146 int i;
147
148 for (i = 0; i < NUM_ICTLRS; i++) {
149 base = ictlr_reg_base[i];
150 tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
151 writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
152 }
153}
154
155void tegra_legacy_irq_restore_mask(void)
156{
157 void __iomem *base;
158 int i;
159
160 for (i = 0; i < NUM_ICTLRS; i++) {
161 base = ictlr_reg_base[i];
162 writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
163 }
164}
165
166void tegra_init_legacy_irq(void)
167{
168 int i;
169
170 for (i = 0; i < NUM_ICTLRS; i++) {
171 void __iomem *ictlr = ictlr_reg_base[i];
172 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
173 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
174 }
175}
176
177#ifdef CONFIG_PM
178static u32 cop_ier[NUM_ICTLRS];
179static u32 cpu_ier[NUM_ICTLRS];
180static u32 cpu_iep[NUM_ICTLRS];
181
182void tegra_irq_suspend(void)
183{
184 unsigned long flags;
185 int i;
186
187 local_irq_save(flags);
188 for (i = 0; i < NUM_ICTLRS; i++) {
189 void __iomem *ictlr = ictlr_reg_base[i];
190 cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
191 cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
192 cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
193 writel(~0, ictlr + ICTLR_COP_IER_CLR);
194 }
195 local_irq_restore(flags);
196}
197
198void tegra_irq_resume(void)
199{
200 unsigned long flags;
201 int i;
202
203 local_irq_save(flags);
204 for (i = 0; i < NUM_ICTLRS; i++) {
205 void __iomem *ictlr = ictlr_reg_base[i];
206 writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
207 writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
208 writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
209 writel(0, ictlr + ICTLR_COP_IEP_CLASS);
210 writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
211 writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
212 }
213 local_irq_restore(flags);
214}
215#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index ec1f68924edf..b8ae3c978dee 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/hardware/gic.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
@@ -122,6 +123,8 @@ void __init smp_init_cpus(void)
122 123
123 for (i = 0; i < ncores; i++) 124 for (i = 0; i < ncores; i++)
124 cpu_set(i, cpu_possible_map); 125 cpu_set(i, cpu_possible_map);
126
127 set_smp_cross_call(gic_raise_softirq);
125} 128}
126 129
127void __init platform_smp_prepare_cpus(unsigned int max_cpus) 130void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 4459470c052d..bb618075fab6 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -337,7 +337,7 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
337 const struct clk_mux_sel *sel; 337 const struct clk_mux_sel *sel;
338 int shift; 338 int shift;
339 339
340 val = clk_readl(c->reg + SUPER_CLK_MUX);; 340 val = clk_readl(c->reg + SUPER_CLK_MUX);
341 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && 341 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
342 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 342 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
343 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 343 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 0fcb1eb4214d..90350420c4e9 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -98,11 +98,6 @@ static void tegra_timer_set_mode(enum clock_event_mode mode,
98 } 98 }
99} 99}
100 100
101static cycle_t tegra_clocksource_read(struct clocksource *cs)
102{
103 return timer_readl(TIMERUS_CNTR_1US);
104}
105
106static struct clock_event_device tegra_clockevent = { 101static struct clock_event_device tegra_clockevent = {
107 .name = "timer0", 102 .name = "timer0",
108 .rating = 300, 103 .rating = 300,
@@ -111,14 +106,6 @@ static struct clock_event_device tegra_clockevent = {
111 .set_mode = tegra_timer_set_mode, 106 .set_mode = tegra_timer_set_mode,
112}; 107};
113 108
114static struct clocksource tegra_clocksource = {
115 .name = "timer_us",
116 .rating = 300,
117 .read = tegra_clocksource_read,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120};
121
122static DEFINE_CLOCK_DATA(cd); 109static DEFINE_CLOCK_DATA(cd);
123 110
124/* 111/*
@@ -234,7 +221,8 @@ static void __init tegra_init_timer(void)
234 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 221 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
235 1000000, SC_MULT, SC_SHIFT); 222 1000000, SC_MULT, SC_SHIFT);
236 223
237 if (clocksource_register_hz(&tegra_clocksource, 1000000)) { 224 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
225 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
238 printk(KERN_ERR "Failed to register clocksource\n"); 226 printk(KERN_ERR "Failed to register clocksource\n");
239 BUG(); 227 BUG();
240 } 228 }