10 files changed, 63 insertions, 41 deletions

diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 3cdc1bb8254c..d195db09ea32 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -62,7 +62,11 @@ int __init harmony_pcie_init(void)
                 goto err_reg;
         }
 
-        regulator_enable(regulator);
+        err = regulator_enable(regulator);
+        if (err) {
+                pr_err("%s: regulator_enable failed: %d\n", __func__, err);
+                goto err_en;
+        }
 
         err = tegra_pcie_init(true, true);
         if (err) {
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
 
 err_pcie:
         regulator_disable(regulator);
+err_en:
         regulator_put(regulator);
 err_reg:
         gpio_free(en_vdd_1v05);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 36dc2befa9d8..9387daeeadc8 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -99,12 +99,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 
         smp_wmb();
 
-        save_cpu_arch_register();
-
         cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 
-        restore_cpu_arch_register();
-
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
         return true;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d..045c16f2dd51 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2c6b3d55213b..e78d52d83acd 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
         if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
                 timeout = jiffies + msecs_to_jiffies(50);
                 do {
-                        if (!tegra_powergate_is_powered(pwrgateid))
+                        if (tegra_powergate_is_powered(pwrgateid))
                                 goto remove_clamps;
                         udelay(10);
                 } while (time_before(jiffies, timeout));
@@ -124,6 +124,9 @@ remove_clamps:
 
         /* Remove I/O clamps. */
         ret = tegra_powergate_remove_clamping(pwrgateid);
+        if (ret)
+                return ret;
+
         udelay(10);
 
         /* Clear flow controller CSR. */
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 523604de666f..04a8e06f59a9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -46,26 +46,11 @@
 #define PMC_CPUPWROFF_TIMER     0xcc
 
 #ifdef CONFIG_PM_SLEEP
-static unsigned int g_diag_reg;
 static DEFINE_SPINLOCK(tegra_lp2_lock);
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-void save_cpu_arch_register(void)
-{
-        /* read diagnostic register */
-        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-        return;
-}
-
-void restore_cpu_arch_register(void)
-{
-        /* write diagnostic register */
-        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-        return;
-}
-
 static void set_power_timers(unsigned long us_on, unsigned long us_off)
 {
         unsigned long long ticks;
@@ -119,8 +104,6 @@ static void restore_cpu_complex(void)
         tegra_cpu_clock_resume();
 
         flowctrl_cpu_suspend_exit(cpu);
-
-        restore_cpu_arch_register();
 }
 
 /*
@@ -145,8 +128,6 @@ static void suspend_cpu_complex(void)
         tegra_cpu_clock_suspend();
 
         flowctrl_cpu_suspend_enter(cpu);
-
-        save_cpu_arch_register();
 }
 
 void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@@ -181,6 +162,11 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id)
         return last_cpu;
 }
 
+int tegra_cpu_do_idle(void)
+{
+        return cpu_do_idle();
+}
+
 static int tegra_sleep_cpu(unsigned long v2p)
 {
         /* Switch to the identity mapping. */
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index c6bc8f85759c..af9067e2867c 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -22,6 +22,7 @@
 #include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/seq_file.h>
@@ -75,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state)
 
         if (status == new_state) {
                 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
-                return -EINVAL;
+                return 0;
         }
 
         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
@@ -168,6 +169,7 @@ err_clk:
 err_power:
         return ret;
 }
+EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
 
 int tegra_cpu_powergate_id(int cpuid)
 {
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ceade4a..e6de88a2ea06 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,12 +41,10 @@
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
 
         cpu_id  r0
         cmp     r0, #0                          @ CPU0?
+ THUMB( it      ne )
         bne     cpu_resume                      @ no
 
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -99,6 +97,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
  *
  * Register usage within the reset handler:
  *
+ *      Others: scratch
+ *      R6  = SoC ID << 8
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -114,6 +114,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
 ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
+        and     r6, r6, #0xff00
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+t20_check:
+        cmp     r6, #(0x20 << 8)
+        bne     after_t20_check
+t20_errata:
+        # Tegra20 is a Cortex-A9 r1p1
+        mrc     p15, 0, r0, c1, c0, 0   @ read system control register
+        orr     r0, r0, #1 << 14        @ erratum 716044
+        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 4         @ erratum 742230
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t20_check:
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+t30_check:
+        cmp     r6, #(0x30 << 8)
+        bne     after_t30_check
+t30_errata:
+        # Tegra30 is a Cortex-A9 r2p9
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 6         @ erratum 743622
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t30_check:
+#endif
+after_errata:
         mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
         and     r10, r10, #0x3                  @ R10 = CPU number
         mov     r11, #1
@@ -129,16 +163,13 @@ ENTRY(__tegra_cpu_reset_handler)
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #(0x20 << 8)
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r6, TEGRA_PMC_BASE
+        mov32   r5, TEGRA_PMC_BASE
         mov     r0, #0
         cmp     r10, #0
-        strne   r0, [r6, #PMC_SCRATCH41]
+        strne   r0, [r5, #PMC_SCRATCH41]
 1:
 #endif
 
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 9f6bfafdd512..e3f2417c420e 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
         mov     r3, #CPU_RESETTABLE
         str     r3, [r0]
 
-        bl      cpu_do_idle
+        bl      tegra_cpu_do_idle
 
         /*
          * cpu may be reset while in wfi, which will return through
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 63a15bd9b653..d29dfcce948d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown)
                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
                 FLOW_CTRL_CSR_ENABLE
         mov     r4, #(1 << 4)
-        orr     r12, r12, r4, lsl r3
+ ARM(   orr     r12, r12, r4, lsl r3    )
+ THUMB( lsl     r4, r4, r3              )
+ THUMB( orr     r12, r12, r4            )
         str     r12, [r1]
 
         /* Halt this CPU. */
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4ffae541726e..bb308eab9079 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -92,7 +92,7 @@
 
 #ifdef CONFIG_CACHE_L2X0
 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
-        adr     \tmp1, \phys_l2x0_saved_regs
+        W(adr)  \tmp1, \phys_l2x0_saved_regs
         ldr     \tmp1, [\tmp1]
         ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
         ldr     \tmp3, [\tmp2, #L2X0_CTRL]