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Diffstat (limited to 'arch/arm/mach-tegra/tegra20_clocks_data.c')
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 1eb50674721e..1a35c003fba8 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -583,6 +583,34 @@ static struct clk_tegra tegra_cclk_hw = {
583DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk, 583DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
584 mux_cclk_p, NULL); 584 mux_cclk_p, NULL);
585 585
586static const char *mux_twd[] = {
587 "cclk",
588};
589
590static struct clk *mux_twd_p[] = {
591 &tegra_cclk,
592};
593
594static struct clk tegra_clk_twd;
595static struct clk_tegra tegra_clk_twd_hw = {
596 .hw = {
597 .clk = &tegra_clk_twd,
598 },
599 .max_rate = 1000000000,
600 .mul = 1,
601 .div = 4,
602};
603
604static struct clk tegra_clk_twd = {
605 .name = "twd",
606 .ops = &tegra_twd_ops,
607 .hw = &tegra_clk_twd_hw.hw,
608 .parent = &tegra_cclk,
609 .parent_names = mux_twd,
610 .parents = mux_twd_p,
611 .num_parents = ARRAY_SIZE(mux_twd),
612};
613
586static struct clk tegra_sclk; 614static struct clk tegra_sclk;
587static struct clk_tegra tegra_sclk_hw = { 615static struct clk_tegra tegra_sclk_hw = {
588 .hw = { 616 .hw = {
@@ -1027,6 +1055,7 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
1027 CLK_DUPLICATE("cop", "tegra-avp", "cop"), 1055 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1028 CLK_DUPLICATE("vde", "tegra-aes", "vde"), 1056 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1029 CLK_DUPLICATE("cclk", NULL, "cpu"), 1057 CLK_DUPLICATE("cclk", NULL, "cpu"),
1058 CLK_DUPLICATE("twd", "smp_twd", NULL),
1030}; 1059};
1031 1060
1032#define CLK(dev, con, ck) \ 1061#define CLK(dev, con, ck) \
@@ -1057,6 +1086,7 @@ static struct clk *tegra_ptr_clks[] = {
1057 &tegra_pll_x, 1086 &tegra_pll_x,
1058 &tegra_pll_e, 1087 &tegra_pll_e,
1059 &tegra_cclk, 1088 &tegra_cclk,
1089 &tegra_clk_twd,
1060 &tegra_sclk, 1090 &tegra_sclk,
1061 &tegra_hclk, 1091 &tegra_hclk,
1062 &tegra_pclk, 1092 &tegra_pclk,