diff options
Diffstat (limited to 'arch/arm/mach-tegra/sleep.h')
-rw-r--r-- | arch/arm/mach-tegra/sleep.h | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index e25a7cd703d9..9821ee725420 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
@@ -17,7 +17,7 @@ | |||
17 | #ifndef __MACH_TEGRA_SLEEP_H | 17 | #ifndef __MACH_TEGRA_SLEEP_H |
18 | #define __MACH_TEGRA_SLEEP_H | 18 | #define __MACH_TEGRA_SLEEP_H |
19 | 19 | ||
20 | #include <mach/iomap.h> | 20 | #include "iomap.h" |
21 | 21 | ||
22 | #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ | 22 | #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ |
23 | + IO_CPU_VIRT) | 23 | + IO_CPU_VIRT) |
@@ -71,7 +71,41 @@ | |||
71 | str \tmp2, [\tmp1] @ invalidate SCU tags for CPU | 71 | str \tmp2, [\tmp1] @ invalidate SCU tags for CPU |
72 | dsb | 72 | dsb |
73 | .endm | 73 | .endm |
74 | |||
75 | /* Macro to resume & re-enable L2 cache */ | ||
76 | #ifndef L2X0_CTRL_EN | ||
77 | #define L2X0_CTRL_EN 1 | ||
78 | #endif | ||
79 | |||
80 | #ifdef CONFIG_CACHE_L2X0 | ||
81 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs | ||
82 | adr \tmp1, \phys_l2x0_saved_regs | ||
83 | ldr \tmp1, [\tmp1] | ||
84 | ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] | ||
85 | ldr \tmp3, [\tmp2, #L2X0_CTRL] | ||
86 | tst \tmp3, #L2X0_CTRL_EN | ||
87 | bne exit_l2_resume | ||
88 | ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] | ||
89 | str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] | ||
90 | ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] | ||
91 | str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] | ||
92 | ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] | ||
93 | str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] | ||
94 | ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] | ||
95 | str \tmp3, [\tmp2, #L2X0_POWER_CTRL] | ||
96 | ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] | ||
97 | str \tmp3, [\tmp2, #L2X0_AUX_CTRL] | ||
98 | mov \tmp3, #L2X0_CTRL_EN | ||
99 | str \tmp3, [\tmp2, #L2X0_CTRL] | ||
100 | exit_l2_resume: | ||
101 | .endm | ||
102 | #else /* CONFIG_CACHE_L2X0 */ | ||
103 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs | ||
104 | .endm | ||
105 | #endif /* CONFIG_CACHE_L2X0 */ | ||
74 | #else | 106 | #else |
107 | void tegra_resume(void); | ||
108 | int tegra_sleep_cpu_finish(unsigned long); | ||
75 | 109 | ||
76 | #ifdef CONFIG_HOTPLUG_CPU | 110 | #ifdef CONFIG_HOTPLUG_CPU |
77 | void tegra20_hotplug_init(void); | 111 | void tegra20_hotplug_init(void); |
@@ -81,5 +115,8 @@ static inline void tegra20_hotplug_init(void) {} | |||
81 | static inline void tegra30_hotplug_init(void) {} | 115 | static inline void tegra30_hotplug_init(void) {} |
82 | #endif | 116 | #endif |
83 | 117 | ||
118 | int tegra30_sleep_cpu_secondary_finish(unsigned long); | ||
119 | void tegra30_tear_down_cpu(void); | ||
120 | |||
84 | #endif | 121 | #endif |
85 | #endif | 122 | #endif |