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-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h54
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h325
-rw-r--r--arch/arm/mach-tegra/include/mach/irammap.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/powergate.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra-ahb.h19
-rw-r--r--arch/arm/mach-tegra/include/mach/uncompress.h4
7 files changed, 6 insertions, 437 deletions
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 8ce0661b8a3d..44ca7b1d8b8a 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -26,8 +26,8 @@
26 26
27#include <linux/serial_reg.h> 27#include <linux/serial_reg.h>
28 28
29#include <mach/iomap.h> 29#include "../../iomap.h"
30#include <mach/irammap.h> 30#include "../../irammap.h"
31 31
32 .macro addruart, rp, rv, tmp 32 .macro addruart, rp, rv, tmp
33 adr \rp, 99f @ actual addr of 99f 33 adr \rp, 99f @ actual addr of 99f
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
deleted file mode 100644
index 3081cc6dda3b..000000000000
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/dma.h
3 *
4 * Copyright (c) 2008-2009, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_DMA_H
22#define __MACH_TEGRA_DMA_H
23
24#include <linux/list.h>
25
26#define TEGRA_DMA_REQ_SEL_CNTR 0
27#define TEGRA_DMA_REQ_SEL_I2S_2 1
28#define TEGRA_DMA_REQ_SEL_I2S_1 2
29#define TEGRA_DMA_REQ_SEL_SPD_I 3
30#define TEGRA_DMA_REQ_SEL_UI_I 4
31#define TEGRA_DMA_REQ_SEL_MIPI 5
32#define TEGRA_DMA_REQ_SEL_I2S2_2 6
33#define TEGRA_DMA_REQ_SEL_I2S2_1 7
34#define TEGRA_DMA_REQ_SEL_UARTA 8
35#define TEGRA_DMA_REQ_SEL_UARTB 9
36#define TEGRA_DMA_REQ_SEL_UARTC 10
37#define TEGRA_DMA_REQ_SEL_SPI 11
38#define TEGRA_DMA_REQ_SEL_AC97 12
39#define TEGRA_DMA_REQ_SEL_ACMODEM 13
40#define TEGRA_DMA_REQ_SEL_SL4B 14
41#define TEGRA_DMA_REQ_SEL_SL2B1 15
42#define TEGRA_DMA_REQ_SEL_SL2B2 16
43#define TEGRA_DMA_REQ_SEL_SL2B3 17
44#define TEGRA_DMA_REQ_SEL_SL2B4 18
45#define TEGRA_DMA_REQ_SEL_UARTD 19
46#define TEGRA_DMA_REQ_SEL_UARTE 20
47#define TEGRA_DMA_REQ_SEL_I2C 21
48#define TEGRA_DMA_REQ_SEL_I2C2 22
49#define TEGRA_DMA_REQ_SEL_I2C3 23
50#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
51#define TEGRA_DMA_REQ_SEL_OWR 25
52#define TEGRA_DMA_REQ_SEL_INVALID 31
53
54#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
deleted file mode 100644
index fee3a94c4549..000000000000
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ /dev/null
@@ -1,325 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IOMAP_H
22#define __MACH_TEGRA_IOMAP_H
23
24#include <asm/sizes.h>
25
26#define TEGRA_IRAM_BASE 0x40000000
27#define TEGRA_IRAM_SIZE SZ_256K
28
29#define TEGRA_HOST1X_BASE 0x50000000
30#define TEGRA_HOST1X_SIZE 0x24000
31
32#define TEGRA_ARM_PERIF_BASE 0x50040000
33#define TEGRA_ARM_PERIF_SIZE SZ_8K
34
35#define TEGRA_ARM_PL310_BASE 0x50043000
36#define TEGRA_ARM_PL310_SIZE SZ_4K
37
38#define TEGRA_ARM_INT_DIST_BASE 0x50041000
39#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
40
41#define TEGRA_MPE_BASE 0x54040000
42#define TEGRA_MPE_SIZE SZ_256K
43
44#define TEGRA_VI_BASE 0x54080000
45#define TEGRA_VI_SIZE SZ_256K
46
47#define TEGRA_ISP_BASE 0x54100000
48#define TEGRA_ISP_SIZE SZ_256K
49
50#define TEGRA_DISPLAY_BASE 0x54200000
51#define TEGRA_DISPLAY_SIZE SZ_256K
52
53#define TEGRA_DISPLAY2_BASE 0x54240000
54#define TEGRA_DISPLAY2_SIZE SZ_256K
55
56#define TEGRA_HDMI_BASE 0x54280000
57#define TEGRA_HDMI_SIZE SZ_256K
58
59#define TEGRA_GART_BASE 0x58000000
60#define TEGRA_GART_SIZE SZ_32M
61
62#define TEGRA_RES_SEMA_BASE 0x60001000
63#define TEGRA_RES_SEMA_SIZE SZ_4K
64
65#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
66#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
67
68#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
69#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
70
71#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
72#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
73
74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
76
77#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
78#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
79
80#define TEGRA_TMR1_BASE 0x60005000
81#define TEGRA_TMR1_SIZE SZ_8
82
83#define TEGRA_TMR2_BASE 0x60005008
84#define TEGRA_TMR2_SIZE SZ_8
85
86#define TEGRA_TMRUS_BASE 0x60005010
87#define TEGRA_TMRUS_SIZE SZ_64
88
89#define TEGRA_TMR3_BASE 0x60005050
90#define TEGRA_TMR3_SIZE SZ_8
91
92#define TEGRA_TMR4_BASE 0x60005058
93#define TEGRA_TMR4_SIZE SZ_8
94
95#define TEGRA_CLK_RESET_BASE 0x60006000
96#define TEGRA_CLK_RESET_SIZE SZ_4K
97
98#define TEGRA_FLOW_CTRL_BASE 0x60007000
99#define TEGRA_FLOW_CTRL_SIZE 20
100
101#define TEGRA_AHB_DMA_BASE 0x60008000
102#define TEGRA_AHB_DMA_SIZE SZ_4K
103
104#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
105#define TEGRA_AHB_DMA_CH0_SIZE 32
106
107#define TEGRA_APB_DMA_BASE 0x6000A000
108#define TEGRA_APB_DMA_SIZE SZ_4K
109
110#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
111#define TEGRA_APB_DMA_CH0_SIZE 32
112
113#define TEGRA_AHB_GIZMO_BASE 0x6000C004
114#define TEGRA_AHB_GIZMO_SIZE 0x10C
115
116#define TEGRA_SB_BASE 0x6000C200
117#define TEGRA_SB_SIZE 256
118
119#define TEGRA_STATMON_BASE 0x6000C400
120#define TEGRA_STATMON_SIZE SZ_1K
121
122#define TEGRA_GPIO_BASE 0x6000D000
123#define TEGRA_GPIO_SIZE SZ_4K
124
125#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
126#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
127
128#define TEGRA_APB_MISC_BASE 0x70000000
129#define TEGRA_APB_MISC_SIZE SZ_4K
130
131#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
132#define TEGRA_APB_MISC_DAS_SIZE SZ_128
133
134#define TEGRA_AC97_BASE 0x70002000
135#define TEGRA_AC97_SIZE SZ_512
136
137#define TEGRA_SPDIF_BASE 0x70002400
138#define TEGRA_SPDIF_SIZE SZ_512
139
140#define TEGRA_I2S1_BASE 0x70002800
141#define TEGRA_I2S1_SIZE SZ_256
142
143#define TEGRA_I2S2_BASE 0x70002A00
144#define TEGRA_I2S2_SIZE SZ_256
145
146#define TEGRA_UARTA_BASE 0x70006000
147#define TEGRA_UARTA_SIZE SZ_64
148
149#define TEGRA_UARTB_BASE 0x70006040
150#define TEGRA_UARTB_SIZE SZ_64
151
152#define TEGRA_UARTC_BASE 0x70006200
153#define TEGRA_UARTC_SIZE SZ_256
154
155#define TEGRA_UARTD_BASE 0x70006300
156#define TEGRA_UARTD_SIZE SZ_256
157
158#define TEGRA_UARTE_BASE 0x70006400
159#define TEGRA_UARTE_SIZE SZ_256
160
161#define TEGRA_NAND_BASE 0x70008000
162#define TEGRA_NAND_SIZE SZ_256
163
164#define TEGRA_HSMMC_BASE 0x70008500
165#define TEGRA_HSMMC_SIZE SZ_256
166
167#define TEGRA_SNOR_BASE 0x70009000
168#define TEGRA_SNOR_SIZE SZ_4K
169
170#define TEGRA_PWFM_BASE 0x7000A000
171#define TEGRA_PWFM_SIZE SZ_256
172
173#define TEGRA_PWFM0_BASE 0x7000A000
174#define TEGRA_PWFM0_SIZE 4
175
176#define TEGRA_PWFM1_BASE 0x7000A010
177#define TEGRA_PWFM1_SIZE 4
178
179#define TEGRA_PWFM2_BASE 0x7000A020
180#define TEGRA_PWFM2_SIZE 4
181
182#define TEGRA_PWFM3_BASE 0x7000A030
183#define TEGRA_PWFM3_SIZE 4
184
185#define TEGRA_MIPI_BASE 0x7000B000
186#define TEGRA_MIPI_SIZE SZ_256
187
188#define TEGRA_I2C_BASE 0x7000C000
189#define TEGRA_I2C_SIZE SZ_256
190
191#define TEGRA_TWC_BASE 0x7000C100
192#define TEGRA_TWC_SIZE SZ_256
193
194#define TEGRA_SPI_BASE 0x7000C380
195#define TEGRA_SPI_SIZE 48
196
197#define TEGRA_I2C2_BASE 0x7000C400
198#define TEGRA_I2C2_SIZE SZ_256
199
200#define TEGRA_I2C3_BASE 0x7000C500
201#define TEGRA_I2C3_SIZE SZ_256
202
203#define TEGRA_OWR_BASE 0x7000C600
204#define TEGRA_OWR_SIZE 80
205
206#define TEGRA_DVC_BASE 0x7000D000
207#define TEGRA_DVC_SIZE SZ_512
208
209#define TEGRA_SPI1_BASE 0x7000D400
210#define TEGRA_SPI1_SIZE SZ_512
211
212#define TEGRA_SPI2_BASE 0x7000D600
213#define TEGRA_SPI2_SIZE SZ_512
214
215#define TEGRA_SPI3_BASE 0x7000D800
216#define TEGRA_SPI3_SIZE SZ_512
217
218#define TEGRA_SPI4_BASE 0x7000DA00
219#define TEGRA_SPI4_SIZE SZ_512
220
221#define TEGRA_RTC_BASE 0x7000E000
222#define TEGRA_RTC_SIZE SZ_256
223
224#define TEGRA_KBC_BASE 0x7000E200
225#define TEGRA_KBC_SIZE SZ_256
226
227#define TEGRA_PMC_BASE 0x7000E400
228#define TEGRA_PMC_SIZE SZ_256
229
230#define TEGRA_MC_BASE 0x7000F000
231#define TEGRA_MC_SIZE SZ_1K
232
233#define TEGRA_EMC_BASE 0x7000F400
234#define TEGRA_EMC_SIZE SZ_1K
235
236#define TEGRA_FUSE_BASE 0x7000F800
237#define TEGRA_FUSE_SIZE SZ_1K
238
239#define TEGRA_KFUSE_BASE 0x7000FC00
240#define TEGRA_KFUSE_SIZE SZ_1K
241
242#define TEGRA_CSITE_BASE 0x70040000
243#define TEGRA_CSITE_SIZE SZ_256K
244
245#define TEGRA_USB_BASE 0xC5000000
246#define TEGRA_USB_SIZE SZ_16K
247
248#define TEGRA_USB2_BASE 0xC5004000
249#define TEGRA_USB2_SIZE SZ_16K
250
251#define TEGRA_USB3_BASE 0xC5008000
252#define TEGRA_USB3_SIZE SZ_16K
253
254#define TEGRA_SDMMC1_BASE 0xC8000000
255#define TEGRA_SDMMC1_SIZE SZ_512
256
257#define TEGRA_SDMMC2_BASE 0xC8000200
258#define TEGRA_SDMMC2_SIZE SZ_512
259
260#define TEGRA_SDMMC3_BASE 0xC8000400
261#define TEGRA_SDMMC3_SIZE SZ_512
262
263#define TEGRA_SDMMC4_BASE 0xC8000600
264#define TEGRA_SDMMC4_SIZE SZ_512
265
266#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
267# define TEGRA_DEBUG_UART_BASE 0
268#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
269# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
270#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
271# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
272#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
273# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
274#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
275# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
276#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
277# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
278#endif
279
280/* On TEGRA, many peripherals are very closely packed in
281 * two 256MB io windows (that actually only use about 64KB
282 * at the start of each).
283 *
284 * We will just map the first 1MB of each window (to minimize
285 * pt entries needed) and provide a macro to transform physical
286 * io addresses to an appropriate void __iomem *.
287 *
288 */
289
290#define IO_IRAM_PHYS 0x40000000
291#define IO_IRAM_VIRT IOMEM(0xFE400000)
292#define IO_IRAM_SIZE SZ_256K
293
294#define IO_CPU_PHYS 0x50040000
295#define IO_CPU_VIRT IOMEM(0xFE000000)
296#define IO_CPU_SIZE SZ_16K
297
298#define IO_PPSB_PHYS 0x60000000
299#define IO_PPSB_VIRT IOMEM(0xFE200000)
300#define IO_PPSB_SIZE SZ_1M
301
302#define IO_APB_PHYS 0x70000000
303#define IO_APB_VIRT IOMEM(0xFE300000)
304#define IO_APB_SIZE SZ_1M
305
306#define TEGRA_PCIE_BASE 0x80000000
307#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
308
309#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
310#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
311
312#define IO_TO_VIRT(n) ( \
313 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
314 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
315 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
316 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
317 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
318 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
319 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
320 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
321 NULL)
322
323#define IO_ADDRESS(n) (IO_TO_VIRT(n))
324
325#endif
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/include/mach/irammap.h
deleted file mode 100644
index 0cbe63261854..000000000000
--- a/arch/arm/mach-tegra/include/mach/irammap.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_IRAMMAP_H
18#define __MACH_TEGRA_IRAMMAP_H
19
20#include <asm/sizes.h>
21
22/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
25
26/*
27 * These locations are written to by uncompress.h, and read by debug-macro.S.
28 * The first word holds the cookie value if the data is valid. The second
29 * word holds the UART physical address.
30 */
31#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
32#define TEGRA_IRAM_DEBUG_UART_SIZE 8
33#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 4752b1a68f35..06763fe7529d 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -20,6 +20,8 @@
20#ifndef _MACH_TEGRA_POWERGATE_H_ 20#ifndef _MACH_TEGRA_POWERGATE_H_
21#define _MACH_TEGRA_POWERGATE_H_ 21#define _MACH_TEGRA_POWERGATE_H_
22 22
23struct clk;
24
23#define TEGRA_POWERGATE_CPU 0 25#define TEGRA_POWERGATE_CPU 0
24#define TEGRA_POWERGATE_3D 1 26#define TEGRA_POWERGATE_3D 1
25#define TEGRA_POWERGATE_VENC 2 27#define TEGRA_POWERGATE_VENC 2
diff --git a/arch/arm/mach-tegra/include/mach/tegra-ahb.h b/arch/arm/mach-tegra/include/mach/tegra-ahb.h
deleted file mode 100644
index e0f8c84b1d8c..000000000000
--- a/arch/arm/mach-tegra/include/mach/tegra-ahb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __MACH_TEGRA_AHB_H__
15#define __MACH_TEGRA_AHB_H__
16
17extern int tegra_ahb_enable_smmu(struct device_node *ahb);
18
19#endif /* __MACH_TEGRA_AHB_H__ */
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 937c4c50219e..27725750ca3e 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,8 +28,8 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/serial_reg.h> 29#include <linux/serial_reg.h>
30 30
31#include <mach/iomap.h> 31#include "../../iomap.h"
32#include <mach/irammap.h> 32#include "../../irammap.h"
33 33
34#define BIT(x) (1 << (x)) 34#define BIT(x) (1 << (x))
35#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 35#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
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