1 files changed, 42 insertions, 13 deletions

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20f396d740fa..a2eb90169aed 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-tegra/board-harmony.c
+ * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -21,8 +21,10 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/system.h>
@@ -31,18 +33,31 @@
 #include "clock.h"
 #include "fuse.h"
 
+#ifdef CONFIG_OF
+static const struct of_device_id tegra_dt_irq_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { }
+};
+
+void __init tegra_dt_init_irq(void)
+{
+        tegra_init_irq();
+        of_irq_init(tegra_dt_irq_match);
+}
+#endif
+
 void tegra_assert_system_reset(char mode, const char *cmd)
 {
-        void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+        void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
         u32 reg;
 
-        /* use *_related to avoid spinlock since caches are off */
         reg = readl_relaxed(reset);
-        reg |= 0x04;
+        reg |= 0x10;
         writel_relaxed(reg, reset);
 }
 
-static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "clk_m",      NULL,           0,              true },
         { "pll_p",      "clk_m",        216000000,      true },
@@ -58,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { "cpu",        NULL,           0,              true },
         { NULL,         NULL,           0,              0},
 };
+#endif
 
-static void __init tegra_init_cache(void)
+static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+        u32 aux_ctrl, cache_type;
+
+        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 
-        writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
+        cache_type = readl(p + L2X0_CACHE_TYPE);
+        aux_ctrl = (cache_type & 0x700) << (17-8);
+        aux_ctrl |= 0x6C000001;
 
-        l2x0_init(p, 0x6C080001, 0x8200c3fe);
+        l2x0_init(p, aux_ctrl, 0x8200c3fe);
 #endif
 
 }
 
-void __init tegra_init_early(void)
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
 {
         tegra_init_fuse();
-        tegra_init_clock();
-        tegra_clk_init_from_table(common_clk_init_table);
-        tegra_init_cache();
+        tegra2_init_clocks();
+        tegra_clk_init_from_table(tegra20_clk_init_table);
+        tegra_init_cache(0x331, 0x441);
+}
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void __init tegra30_init_early(void)
+{
+        tegra_init_cache(0x441, 0x551);
 }
+#endif