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Diffstat (limited to 'arch/arm/mach-stmp37xx/include/mach/regs-pwm.h')
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pwm.h51
1 files changed, 0 insertions, 51 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
deleted file mode 100644
index 15966a1b62e0..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * stmp37xx: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22
23#define HW_PWM_CTRL 0x0
24#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
25#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
26
27#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
28#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
29#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
30#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
31
32#define HW_PWM_ACTIVEn 0x10
33#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
34#define BP_PWM_ACTIVEn_ACTIVE 0
35#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
36#define BP_PWM_ACTIVEn_INACTIVE 16
37
38#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
39#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
40#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
41#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
42
43#define HW_PWM_PERIODn 0x20
44#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
45#define BP_PWM_PERIODn_PERIOD 0
46#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
47#define BP_PWM_PERIODn_ACTIVE_STATE 16
48#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
49#define BP_PWM_PERIODn_INACTIVE_STATE 18
50#define BM_PWM_PERIODn_CDIV 0x00700000
51#define BP_PWM_PERIODn_CDIV 20