diff options
Diffstat (limited to 'arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h')
-rw-r--r-- | arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..72514e8b0737 --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * stmp37xx: LCDIF register definitions | ||
3 | * | ||
4 | * Copyright (c) 2008 Freescale Semiconductor | ||
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) | ||
22 | #define REGS_LCDIF_PHYS 0x80030000 | ||
23 | #define REGS_LCDIF_SIZE 0x2000 | ||
24 | |||
25 | #define HW_LCDIF_CTRL 0x0 | ||
26 | #define BM_LCDIF_CTRL_COUNT 0x0000FFFF | ||
27 | #define BP_LCDIF_CTRL_COUNT 0 | ||
28 | #define BM_LCDIF_CTRL_RUN 0x00010000 | ||
29 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000 | ||
30 | #define BM_LCDIF_CTRL_DATA_SELECT 0x00040000 | ||
31 | #define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000 | ||
32 | #define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000 | ||
33 | #define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000 | ||
34 | #define BP_LCDIF_CTRL_DATA_SWIZZLE 21 | ||
35 | #define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000 | ||
36 | #define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000 | ||
37 | #define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 | ||
38 | #define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000 | ||
39 | #define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 | ||
40 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
41 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
42 | |||
43 | #define HW_LCDIF_CTRL1 0x10 | ||
44 | #define BM_LCDIF_CTRL1_RESET 0x00000001 | ||
45 | #define BP_LCDIF_CTRL1_RESET 0 | ||
46 | #define BM_LCDIF_CTRL1_MODE86 0x00000002 | ||
47 | #define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 | ||
48 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 | ||
49 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 | ||
50 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 | ||
51 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 | ||
52 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 | ||
53 | #define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 | ||
54 | #define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 | ||
55 | |||
56 | #define HW_LCDIF_TIMING 0x20 | ||
57 | |||
58 | #define HW_LCDIF_VDCTRL0 0x30 | ||
59 | #define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF | ||
60 | #define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0 | ||
61 | #define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 | ||
62 | #define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 | ||
63 | #define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 | ||
64 | #define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 | ||
65 | #define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 | ||
66 | #define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 | ||
67 | #define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 | ||
68 | #define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 | ||
69 | |||
70 | #define HW_LCDIF_VDCTRL1 0x40 | ||
71 | #define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF | ||
72 | #define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 | ||
73 | #define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000 | ||
74 | #define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 | ||
75 | |||
76 | #define HW_LCDIF_VDCTRL2 0x50 | ||
77 | #define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF | ||
78 | #define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0 | ||
79 | #define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800 | ||
80 | #define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 | ||
81 | #define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000 | ||
82 | #define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 | ||
83 | |||
84 | #define HW_LCDIF_VDCTRL3 0x60 | ||
85 | #define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF | ||
86 | #define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 | ||
87 | #define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000 | ||
88 | #define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 | ||
89 | #define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000 | ||