1 files changed, 46 insertions, 129 deletions
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index a835f5b6b182..7fd621532def 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,153 +14,70 @@
 #ifndef __MACH_SPEAR6XX_H
 #define __MACH_SPEAR6XX_H
-#include <mach/hardware.h>
+#include <asm/memory.h>
 #include <mach/spear600.h>
-#define SPEAR6XX_ML_SDRAM_BASE          0x00000000
+#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
-#define SPEAR6XX_ML_SDRAM_SIZE          0x40000000
 /* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE              0xD0000000
+#define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-#define SPEAR6XX_ICM1_SIZE              0x08000000
-#define SPEAR6XX_ICM1_UART0_BASE        0xD0000000
+#define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
 #define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-#define SPEAR6XX_ICM1_UART0_SIZE        0x00080000
-#define SPEAR6XX_ICM1_UART1_BASE        0xD0080000
-#define SPEAR6XX_ICM1_UART1_SIZE        0x00080000
-#define SPEAR6XX_ICM1_SSP0_BASE         0xD0100000
-#define SPEAR6XX_ICM1_SSP0_SIZE         0x00080000
-#define SPEAR6XX_ICM1_SSP1_BASE         0xD0180000
-#define SPEAR6XX_ICM1_SSP1_SIZE         0x00080000
-#define SPEAR6XX_ICM1_I2C_BASE          0xD0200000
-#define SPEAR6XX_ICM1_I2C_SIZE          0x00080000
-#define SPEAR6XX_ICM1_JPEG_BASE         0xD0800000
+#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_JPEG_SIZE         0x00800000
+#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
+#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_IRDA_BASE         0xD1000000
+#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_IRDA_SIZE         0x00800000
+#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
+#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         0xD1800000
+#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_FSMC_SIZE         0x00800000
+#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
+#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
-#define SPEAR6XX_ICM1_NAND_BASE         0xD2000000
-#define SPEAR6XX_ICM1_NAND_SIZE         0x00800000
-#define SPEAR6XX_ICM1_SRAM_BASE         0xD2800000
-#define SPEAR6XX_ICM1_SRAM_SIZE         0x00800000
 /* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              0xD8000000
+#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_SIZE              0x08000000
+#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
+#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_TMR0_BASE         0xD8000000
+#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_TMR0_SIZE         0x00080000
+#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
+#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
-#define SPEAR6XX_ICM2_TMR1_BASE         0xD8080000
-#define SPEAR6XX_ICM2_TMR1_SIZE         0x00080000
-#define SPEAR6XX_ICM2_GPIO_BASE         0xD8100000
-#define SPEAR6XX_ICM2_GPIO_SIZE         0x00080000
-#define SPEAR6XX_ICM2_SPI2_BASE         0xD8180000
-#define SPEAR6XX_ICM2_SPI2_SIZE         0x00080000
-#define SPEAR6XX_ICM2_ADC_BASE          0xD8200000
-#define SPEAR6XX_ICM2_ADC_SIZE          0x00080000
 /* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE            0xF0000000
+#define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define SPEAR6XX_ML_CPU_SIZE            0x08000000
+#define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
+#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_TMR_BASE           0xF0000000
+#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
-#define SPEAR6XX_CPU_TMR_SIZE           0x00100000
-#define SPEAR6XX_CPU_GPIO_BASE          0xF0100000
-#define SPEAR6XX_CPU_GPIO_SIZE          0x00100000
-#define SPEAR6XX_CPU_VIC_SEC_BASE       0xF1000000
 #define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_SEC_SIZE       0x00100000
+#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       0xF1100000
 #define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_SIZE       0x00100000
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              0xF8000000
+#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SIZE              0x08000000
+#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
+#define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         0xF8000000
+#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
-#define SPEAR6XX_ICM3_SMEM_SIZE         0x04000000
+#define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
+#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE     0xFC000000
+#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_SMI_CTRL_SIZE     0x00200000
+#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
+#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_CLCD_BASE         0xFC200000
+#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
-#define SPEAR6XX_ICM3_CLCD_SIZE         0x00200000
+#define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define SPEAR6XX_ICM3_DMA_BASE          0xFC400000
-#define SPEAR6XX_ICM3_DMA_SIZE          0x00200000
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   0xFC600000
-#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE   0x00200000
-#define SPEAR6XX_ICM3_TMR_BASE          0xFC800000
-#define SPEAR6XX_ICM3_TMR_SIZE          0x00080000
-#define SPEAR6XX_ICM3_WDT_BASE          0xFC880000
-#define SPEAR6XX_ICM3_WDT_SIZE          0x00080000
-#define SPEAR6XX_ICM3_RTC_BASE          0xFC900000
-#define SPEAR6XX_ICM3_RTC_SIZE          0x00080000
-#define SPEAR6XX_ICM3_GPIO_BASE         0xFC980000
-#define SPEAR6XX_ICM3_GPIO_SIZE         0x00080000
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE     0xFCA00000
 #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_SYS_CTRL_SIZE     0x00080000
+#define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define SPEAR6XX_ICM3_MISC_REG_BASE     0xFCA80000
 #define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_SIZE     0x00080000
 /* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              0xE0000000
+#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_SIZE              0x08000000
+#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
+#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         0xE0800000
+#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_GMAC_SIZE         0x00800000
+#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
+#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    0xE1000000
+#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USBD_FIFO_SIZE    0x00100000
+#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
+#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     0xE1100000
+#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
-#define SPEAR6XX_ICM4_USBD_CSR_SIZE     0x00100000
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    0xE1200000
-#define SPEAR6XX_ICM4_USBD_PLDT_SIZE    0x00100000
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    0xE1800000
-#define SPEAR6XX_ICM4_USB_EHCI0_SIZE    0x00100000
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    0xE1900000
-#define SPEAR6XX_ICM4_USB_OHCI0_SIZE    0x00100000
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    0xE2000000
-#define SPEAR6XX_ICM4_USB_EHCI1_SIZE    0x00100000
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    0xE2100000
-#define SPEAR6XX_ICM4_USB_OHCI1_SIZE    0x00100000
-#define SPEAR6XX_ICM4_USB_ARB_BASE      0xE2800000
-#define SPEAR6XX_ICM4_USB_ARB_SIZE      0x00010000
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE

diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index a835f5b6b182..7fd621532def 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,153 +14,70 @@
14	#ifndef __MACH_SPEAR6XX_H	14	#ifndef __MACH_SPEAR6XX_H
15	#define __MACH_SPEAR6XX_H	15	#define __MACH_SPEAR6XX_H
16		16
17	#include <mach/hardware.h>	17	#include <asm/memory.h>
18	#include <mach/spear600.h>	18	#include <mach/spear600.h>
19		19
20	#define SPEAR6XX_ML_SDRAM_BASE 0x00000000	20	#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21	#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000
22
23	/* ICM1 - Low speed connection */	21	/* ICM1 - Low speed connection */
24	#define SPEAR6XX_ICM1_BASE 0xD0000000	22	#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
25	#define SPEAR6XX_ICM1_SIZE 0x08000000
26		23
27	#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000	24	#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
28	#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)	25	#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
29	#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000
30
31	#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
32	#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000
33
34	#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
35	#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000
36
37	#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
38	#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000
39
40	#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
41	#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000
42		26
43	#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000	27	#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
44	#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000	28	#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
45		29	#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
46	#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000	30	#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
47	#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000	31	#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
48		32	#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
49	#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000	33	#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
50	#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000	34	#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
51		35	#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
52	#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
53	#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000
54
55	#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
56	#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000
57		36
58	/* ICM2 - Application Subsystem */	37	/* ICM2 - Application Subsystem */
59	#define SPEAR6XX_ICM2_BASE 0xD8000000	38	#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
60	#define SPEAR6XX_ICM2_SIZE 0x08000000	39	#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
61		40	#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
62	#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000	41	#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
63	#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000	42	#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
64		43	#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
65	#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
66	#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000
67
68	#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
69	#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
70
71	#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
72	#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000
73
74	#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
75	#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
76		44
77	/* ML-1, 2 - Multi Layer CPU Subsystem */	45	/* ML-1, 2 - Multi Layer CPU Subsystem */
78	#define SPEAR6XX_ML_CPU_BASE 0xF0000000	46	#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
79	#define SPEAR6XX_ML_CPU_SIZE 0x08000000	47	#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
80		48	#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
81	#define SPEAR6XX_CPU_TMR_BASE 0xF0000000	49	#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
82	#define SPEAR6XX_CPU_TMR_SIZE 0x00100000
83
84	#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
85	#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000
86
87	#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
88	#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)	50	#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
89	#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000	51	#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
90
91	#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
92	#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)	52	#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
93	#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000
94		53
95	/* ICM3 - Basic Subsystem */	54	/* ICM3 - Basic Subsystem */
96	#define SPEAR6XX_ICM3_BASE 0xF8000000	55	#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
97	#define SPEAR6XX_ICM3_SIZE 0x08000000	56	#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
98		57	#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
99	#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000	58	#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
100	#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000	59	#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
101		60	#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
102	#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000	61	#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
103	#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000	62	#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
104		63	#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
105	#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000	64	#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
106	#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000	65	#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
107
108	#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
109	#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000
110
111	#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
112	#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
113
114	#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
115	#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000
116
117	#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
118	#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000
119
120	#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
121	#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000
122
123	#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
124	#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000
125
126	#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
127	#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)	66	#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
128	#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000	67	#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
129
130	#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
131	#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)	68	#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
132	#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000
133		69
134	/* ICM4 - High Speed Connection */	70	/* ICM4 - High Speed Connection */
135	#define SPEAR6XX_ICM4_BASE 0xE0000000	71	#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
136	#define SPEAR6XX_ICM4_SIZE 0x08000000	72	#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
137		73	#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
138	#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000	74	#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
139	#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000	75	#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
140		76	#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
141	#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000	77	#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
142	#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000	78	#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
143		79	#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
144	#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000	80	#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
145	#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000
146
147	#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
148	#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000
149
150	#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
151	#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000
152
153	#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
154	#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000
155
156	#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
157	#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000
158
159	#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
160	#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000
161
162	#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
163	#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000
164		81
165	/* Debug uart for linux, will be used for debug and uncompress messages */	82	/* Debug uart for linux, will be used for debug and uncompress messages */
166	#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE	83	#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE